GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
@@ -0,0 +1,156 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Form ABI specifications:
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* int __aeabi_idiv(int numerator, int denominator);
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* unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator);
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*
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* typedef struct { int quot; int rem; } idiv_return;
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* typedef struct { unsigned quot; unsigned rem; } uidiv_return;
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*
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* __value_in_regs idiv_return __aeabi_idivmod(int numerator,
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* int *denominator);
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* __value_in_regs uidiv_return __aeabi_uidivmod(unsigned *numerator,
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* unsigned denominator);
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*/
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/* struct qr - stores quotient/remainder to handle divmod EABI interfaces. */
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struct qr {
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unsigned int q; /* computed quotient */
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unsigned int r; /* computed remainder */
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unsigned int q_n; /* specifies if quotient shall be negative */
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unsigned int r_n; /* specifies if remainder shall be negative */
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};
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static void uint_div_qr(unsigned int numerator, unsigned int denominator,
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struct qr *qr);
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/* returns in R0 and R1 by tail calling an asm function */
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unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator);
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unsigned int __aeabi_uidiv(unsigned int numerator, unsigned int denominator);
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/* returns in R0 and R1 by tail calling an asm function */
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signed int __aeabi_idivmod(signed int numerator, signed int denominator);
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signed int __aeabi_idiv(signed int numerator, signed int denominator);
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/*
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* __ste_idivmod_ret_t __aeabi_idivmod(signed numerator, signed denominator)
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* Numerator and Denominator are received in R0 and R1.
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* Where __ste_idivmod_ret_t is returned in R0 and R1.
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*
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* __ste_uidivmod_ret_t __aeabi_uidivmod(unsigned numerator,
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* unsigned denominator)
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* Numerator and Denominator are received in R0 and R1.
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* Where __ste_uidivmod_ret_t is returned in R0 and R1.
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*/
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#ifdef __GNUC__
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signed int ret_idivmod_values(signed int quotient, signed int remainder);
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unsigned int ret_uidivmod_values(unsigned int quotient, unsigned int remainder);
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#else
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#error "Compiler not supported"
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#endif
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static void division_qr(unsigned int n, unsigned int p, struct qr *qr)
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{
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unsigned int i = 1, q = 0;
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if (p == 0) {
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qr->r = 0xFFFFFFFF; /* division by 0 */
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return;
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}
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while ((p >> 31) == 0) {
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i = i << 1; /* count the max division steps */
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p = p << 1; /* increase p until it has maximum size*/
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}
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while (i > 0) {
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q = q << 1; /* write bit in q at index (size-1) */
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if (n >= p) {
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n -= p;
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q++;
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}
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p = p >> 1; /* decrease p */
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i = i >> 1; /* decrease remaining size in q */
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}
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qr->r = n;
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qr->q = q;
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}
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static void uint_div_qr(unsigned int numerator, unsigned int denominator,
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struct qr *qr)
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{
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division_qr(numerator, denominator, qr);
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/* negate quotient and/or remainder according to requester */
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if (qr->q_n)
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qr->q = -qr->q;
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if (qr->r_n)
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qr->r = -qr->r;
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}
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unsigned int __aeabi_uidiv(unsigned int numerator, unsigned int denominator)
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{
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struct qr qr = { .q_n = 0, .r_n = 0 };
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uint_div_qr(numerator, denominator, &qr);
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return qr.q;
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}
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unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator)
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{
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struct qr qr = { .q_n = 0, .r_n = 0 };
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uint_div_qr(numerator, denominator, &qr);
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return ret_uidivmod_values(qr.q, qr.r);
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}
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signed int __aeabi_idiv(signed int numerator, signed int denominator)
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{
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struct qr qr = { .q_n = 0, .r_n = 0 };
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if (((numerator < 0) && (denominator > 0)) ||
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((numerator > 0) && (denominator < 0)))
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qr.q_n = 1; /* quotient shall be negate */
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if (numerator < 0) {
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numerator = -numerator;
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qr.r_n = 1; /* remainder shall be negate */
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}
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if (denominator < 0)
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denominator = -denominator;
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uint_div_qr(numerator, denominator, &qr);
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return qr.q;
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}
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signed int __aeabi_idivmod(signed int numerator, signed int denominator)
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{
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struct qr qr = { .q_n = 0, .r_n = 0 };
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if (((numerator < 0) && (denominator > 0)) ||
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((numerator > 0) && (denominator < 0)))
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qr.q_n = 1; /* quotient shall be negate */
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if (numerator < 0) {
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numerator = -numerator;
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qr.r_n = 1; /* remainder shall be negate */
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}
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if (denominator < 0)
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denominator = -denominator;
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uint_div_qr(numerator, denominator, &qr);
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return ret_idivmod_values(qr.q, qr.r);
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}
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@@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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/*
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* EABI wrappers from the udivmod and idivmod functions
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*/
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.globl ret_uidivmod_values
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.globl ret_idivmod_values
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/*
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* signed ret_idivmod_values(signed quot, signed rem);
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* return quotient and remaining the EABI way (regs r0,r1)
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*/
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func ret_idivmod_values
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bx lr
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endfunc ret_idivmod_values
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/*
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* unsigned ret_uidivmod_values(unsigned quot, unsigned rem);
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* return quotient and remaining the EABI way (regs r0,r1)
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*/
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func ret_uidivmod_values
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bx lr
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endfunc ret_uidivmod_values
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@@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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/* Symbols needed by armclang */
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.globl __0printf
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.globl __1printf
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.globl __2printf
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func __0printf
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__1printf:
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__2printf:
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b printf
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endfunc __0printf
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@@ -0,0 +1,233 @@
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/*
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* Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl flush_dcache_range
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.globl clean_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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.globl dcsw_op_all
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.globl dcsw_op_level1
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.globl dcsw_op_level2
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.globl dcsw_op_level3
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/*
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* This macro can be used for implementing various data cache operations `op`
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*/
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.macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2
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/* Exit early if size is zero */
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cmp r1, #0
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beq exit_loop_\op
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dcache_line_size r2, r3
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add r1, r0, r1
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sub r3, r2, #1
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bic r0, r0, r3
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loop_\op:
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stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
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add r0, r0, r2
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cmp r0, r1
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blo loop_\op
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dsb sy
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exit_loop_\op:
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bx lr
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.endm
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/* ------------------------------------------
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* Clean+Invalidate from base address till
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* size. 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func flush_dcache_range
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do_dcache_maintenance_by_mva cimvac, DCCIMVAC
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endfunc flush_dcache_range
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/* ------------------------------------------
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* Clean from base address till size.
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* 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func clean_dcache_range
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do_dcache_maintenance_by_mva cmvac, DCCMVAC
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endfunc clean_dcache_range
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/* ------------------------------------------
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* Invalidate from base address till
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* size. 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func inv_dcache_range
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do_dcache_maintenance_by_mva imvac, DCIMVAC
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endfunc inv_dcache_range
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/* ----------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* r1: The cache level to begin operation from
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* r2: clidr_el1
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* r3: The last cache level to operate on
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* and will carry out the operation on each data cache from level 0
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* to the level in r3 in sequence
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*
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* The dcsw_op macro sets up the r2 and r3 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ----------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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ldcopr r2, CLIDR
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ubfx r3, r2, \shift, \fw
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lsl r3, r3, \ls
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mov r1, #0
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b do_dcsw_op
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.endm
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func do_dcsw_op
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push {r4-r12, lr}
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ldcopr r8, ID_MMFR4 // stash FEAT_CCIDX identifier in r8
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ubfx r8, r8, #ID_MMFR4_CCIDX_SHIFT, #ID_MMFR4_CCIDX_LENGTH
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adr r11, dcsw_loop_table // compute cache op based on the operation type
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add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions
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loop1:
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add r10, r1, r1, LSR #1 // Work out 3x current cache level
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mov r12, r2, LSR r10 // extract cache type bits from clidr
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and r12, r12, #7 // mask the bits for current cache only
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cmp r12, #2 // see what cache we have at this level
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blo level_done // no cache or only instruction cache at this level
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stcopr r1, CSSELR // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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ldcopr r12, CCSIDR // read the new ccsidr
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and r10, r12, #7 // extract the length of the cache lines
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add r10, r10, #4 // add 4 (r10 = line length offset)
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cmp r8, #0 // check for FEAT_CCIDX for Associativity
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beq 1f
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ubfx r4, r12, #3, #21 // r4 = associativity CCSIDR[23:3]
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b 2f
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1:
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ubfx r4, r12, #3, #10 // r4 = associativity CCSIDR[12:3]
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2:
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clz r5, r4 // r5 = the bit position of the way size increment
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mov r9, r4 // r9 working copy of the aligned max way number
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loop2:
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cmp r8, #0 // check for FEAT_CCIDX for NumSets
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beq 3f
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ldcopr r12, CCSIDR2 // FEAT_CCIDX numsets is in CCSIDR2
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ubfx r7, r12, #0, #24 // r7 = numsets CCSIDR2[23:0]
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b loop3
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3:
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ubfx r7, r12, #13, #15 // r7 = numsets CCSIDR[27:13]
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loop3:
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orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
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orr r0, r0, r7, LSL r10 // factor in the set number
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blx r6
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subs r7, r7, #1 // decrement the set number
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bhs loop3
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subs r9, r9, #1 // decrement the way number
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bhs loop2
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level_done:
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add r1, r1, #2 // increment the cache number
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cmp r3, r1
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// Ensure completion of previous cache maintenance instruction. Note
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// this also mitigates erratum 814220 on Cortex-A7
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dsb sy
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bhi loop1
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mov r6, #0
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stcopr r6, CSSELR //select cache level 0 in csselr
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dsb sy
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isb
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pop {r4-r12, pc}
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dcsw_loop_table:
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stcopr r0, DCISW
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bx lr
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stcopr r0, DCCISW
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bx lr
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stcopr r0, DCCSW
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bx lr
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endfunc do_dcsw_op
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/* ---------------------------------------------------------------
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* Data cache operations by set/way till PoU.
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*
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* The function requires :
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_louis
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_louis
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/* ---------------------------------------------------------------
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* Data cache operations by set/way till PoC.
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*
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* The function requires :
|
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_all
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_all
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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* level specified
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op_level level
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ldcopr r2, CLIDR
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mov r3, \level
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sub r1, r3, #2
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b do_dcsw_op
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.endm
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/* ---------------------------------------------------------------
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||||
* Data cache operations by set/way for level 1 cache
|
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*
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* The main function, do_dcsw_op requires:
|
||||
* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
|
||||
* as defined in arch.h
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||||
* ---------------------------------------------------------------
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*/
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func dcsw_op_level1
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dcsw_op_level #(1 << LEVEL_SHIFT)
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endfunc dcsw_op_level1
|
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|
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/* ---------------------------------------------------------------
|
||||
* Data cache operations by set/way for level 2 cache
|
||||
*
|
||||
* The main function, do_dcsw_op requires:
|
||||
* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
|
||||
* as defined in arch.h
|
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level2
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dcsw_op_level #(2 << LEVEL_SHIFT)
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endfunc dcsw_op_level2
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|
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/* ---------------------------------------------------------------
|
||||
* Data cache operations by set/way for level 3 cache
|
||||
*
|
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* The main function, do_dcsw_op requires:
|
||||
* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
|
||||
* as defined in arch.h
|
||||
* ---------------------------------------------------------------
|
||||
*/
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func dcsw_op_level3
|
||||
dcsw_op_level #(3 << LEVEL_SHIFT)
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||||
endfunc dcsw_op_level3
|
||||
@@ -0,0 +1,315 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include <common/bl_common.h>
|
||||
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||
|
||||
.globl smc
|
||||
.globl zeromem
|
||||
.globl zero_normalmem
|
||||
.globl memcpy4
|
||||
.globl disable_mmu_icache_secure
|
||||
.globl disable_mmu_secure
|
||||
.globl fixup_gdt_reloc
|
||||
|
||||
#define PAGE_START_MASK ~(PAGE_SIZE_MASK)
|
||||
|
||||
func smc
|
||||
/*
|
||||
* For AArch32 only r0-r3 will be in the registers;
|
||||
* rest r4-r6 will be pushed on to the stack. So here, we'll
|
||||
* have to load them from the stack to registers r4-r6 explicitly.
|
||||
* Clobbers: r4-r6
|
||||
*/
|
||||
ldm sp, {r4, r5, r6}
|
||||
smc #0
|
||||
endfunc smc
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
* void zeromem(void *mem, unsigned int length)
|
||||
*
|
||||
* Initialise a region in normal memory to 0. This functions complies with the
|
||||
* AAPCS and can be called from C code.
|
||||
*
|
||||
* -----------------------------------------------------------------------
|
||||
*/
|
||||
func zeromem
|
||||
/*
|
||||
* Readable names for registers
|
||||
*
|
||||
* Registers r0, r1 and r2 are also set by zeromem which
|
||||
* branches into the fallback path directly, so cursor, length and
|
||||
* stop_address should not be retargeted to other registers.
|
||||
*/
|
||||
cursor .req r0 /* Start address and then current address */
|
||||
length .req r1 /* Length in bytes of the region to zero out */
|
||||
/*
|
||||
* Reusing the r1 register as length is only used at the beginning of
|
||||
* the function.
|
||||
*/
|
||||
stop_address .req r1 /* Address past the last zeroed byte */
|
||||
zeroreg1 .req r2 /* Source register filled with 0 */
|
||||
zeroreg2 .req r3 /* Source register filled with 0 */
|
||||
tmp .req r12 /* Temporary scratch register */
|
||||
|
||||
mov zeroreg1, #0
|
||||
|
||||
/* stop_address is the address past the last to zero */
|
||||
add stop_address, cursor, length
|
||||
|
||||
/*
|
||||
* Length cannot be used anymore as it shares the same register with
|
||||
* stop_address.
|
||||
*/
|
||||
.unreq length
|
||||
|
||||
/*
|
||||
* If the start address is already aligned to 8 bytes, skip this loop.
|
||||
*/
|
||||
tst cursor, #(8-1)
|
||||
beq .Lzeromem_8bytes_aligned
|
||||
|
||||
/* Calculate the next address aligned to 8 bytes */
|
||||
orr tmp, cursor, #(8-1)
|
||||
adds tmp, tmp, #1
|
||||
/* If it overflows, fallback to byte per byte zeroing */
|
||||
beq .Lzeromem_1byte_aligned
|
||||
/* If the next aligned address is after the stop address, fall back */
|
||||
cmp tmp, stop_address
|
||||
bhs .Lzeromem_1byte_aligned
|
||||
|
||||
/* zero byte per byte */
|
||||
1:
|
||||
strb zeroreg1, [cursor], #1
|
||||
cmp cursor, tmp
|
||||
bne 1b
|
||||
|
||||
/* zero 8 bytes at a time */
|
||||
.Lzeromem_8bytes_aligned:
|
||||
|
||||
/* Calculate the last 8 bytes aligned address. */
|
||||
bic tmp, stop_address, #(8-1)
|
||||
|
||||
cmp cursor, tmp
|
||||
bhs 2f
|
||||
|
||||
mov zeroreg2, #0
|
||||
1:
|
||||
stmia cursor!, {zeroreg1, zeroreg2}
|
||||
cmp cursor, tmp
|
||||
blo 1b
|
||||
2:
|
||||
|
||||
/* zero byte per byte */
|
||||
.Lzeromem_1byte_aligned:
|
||||
cmp cursor, stop_address
|
||||
beq 2f
|
||||
1:
|
||||
strb zeroreg1, [cursor], #1
|
||||
cmp cursor, stop_address
|
||||
bne 1b
|
||||
2:
|
||||
bx lr
|
||||
|
||||
.unreq cursor
|
||||
/*
|
||||
* length is already unreq'ed to reuse the register for another
|
||||
* variable.
|
||||
*/
|
||||
.unreq stop_address
|
||||
.unreq zeroreg1
|
||||
.unreq zeroreg2
|
||||
.unreq tmp
|
||||
endfunc zeromem
|
||||
|
||||
/*
|
||||
* AArch32 does not have special ways of zeroing normal memory as AArch64 does
|
||||
* using the DC ZVA instruction, so we just alias zero_normalmem to zeromem.
|
||||
*/
|
||||
.equ zero_normalmem, zeromem
|
||||
|
||||
/* --------------------------------------------------------------------------
|
||||
* void memcpy4(void *dest, const void *src, unsigned int length)
|
||||
*
|
||||
* Copy length bytes from memory area src to memory area dest.
|
||||
* The memory areas should not overlap.
|
||||
* Destination and source addresses must be 4-byte aligned.
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
func memcpy4
|
||||
#if ENABLE_ASSERTIONS
|
||||
orr r3, r0, r1
|
||||
tst r3, #0x3
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
/* copy 4 bytes at a time */
|
||||
m_loop4:
|
||||
cmp r2, #4
|
||||
blo m_loop1
|
||||
ldr r3, [r1], #4
|
||||
str r3, [r0], #4
|
||||
subs r2, r2, #4
|
||||
bne m_loop4
|
||||
bx lr
|
||||
|
||||
/* copy byte per byte */
|
||||
m_loop1:
|
||||
ldrb r3, [r1], #1
|
||||
strb r3, [r0], #1
|
||||
subs r2, r2, #1
|
||||
bne m_loop1
|
||||
bx lr
|
||||
endfunc memcpy4
|
||||
|
||||
/* ---------------------------------------------------------------------------
|
||||
* Disable the MMU in Secure State
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
func disable_mmu_secure
|
||||
mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
|
||||
do_disable_mmu:
|
||||
#if ERRATA_A9_794073
|
||||
stcopr r0, BPIALL
|
||||
dsb
|
||||
#endif
|
||||
ldcopr r0, SCTLR
|
||||
bic r0, r0, r1
|
||||
stcopr r0, SCTLR
|
||||
isb // ensure MMU is off
|
||||
dsb sy
|
||||
bx lr
|
||||
endfunc disable_mmu_secure
|
||||
|
||||
|
||||
func disable_mmu_icache_secure
|
||||
ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
|
||||
b do_disable_mmu
|
||||
endfunc disable_mmu_icache_secure
|
||||
|
||||
/* ---------------------------------------------------------------------------
|
||||
* Helper to fixup Global Descriptor table (GDT) and dynamic relocations
|
||||
* (.rel.dyn) at runtime.
|
||||
*
|
||||
* This function is meant to be used when the firmware is compiled with -fpie
|
||||
* and linked with -pie options. We rely on the linker script exporting
|
||||
* appropriate markers for start and end of the section. For GOT, we
|
||||
* expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect
|
||||
* __RELA_START__ and __RELA_END__.
|
||||
*
|
||||
* The function takes the limits of the memory to apply fixups to as
|
||||
* arguments (which is usually the limits of the relocable BL image).
|
||||
* r0 - the start of the fixup region
|
||||
* r1 - the limit of the fixup region
|
||||
* These addresses have to be 4KB page aligned.
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Relocation codes */
|
||||
#define R_ARM_RELATIVE 23
|
||||
|
||||
func fixup_gdt_reloc
|
||||
mov r6, r0
|
||||
mov r7, r1
|
||||
|
||||
#if ENABLE_ASSERTIONS
|
||||
/* Test if the limits are 4K aligned */
|
||||
orr r0, r0, r1
|
||||
mov r1, #(PAGE_SIZE_MASK)
|
||||
tst r0, r1
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
/*
|
||||
* Calculate the offset based on return address in lr.
|
||||
* Assume that this function is called within a page at the start of
|
||||
* fixup region.
|
||||
*/
|
||||
ldr r1, =PAGE_START_MASK
|
||||
and r2, lr, r1
|
||||
subs r0, r2, r6 /* Diff(S) = Current Address - Compiled Address */
|
||||
beq 3f /* Diff(S) = 0. No relocation needed */
|
||||
|
||||
ldr r1, =__GOT_START__
|
||||
add r1, r1, r0
|
||||
ldr r2, =__GOT_END__
|
||||
add r2, r2, r0
|
||||
|
||||
/*
|
||||
* GOT is an array of 32_bit addresses which must be fixed up as
|
||||
* new_addr = old_addr + Diff(S).
|
||||
* The new_addr is the address currently the binary is executing from
|
||||
* and old_addr is the address at compile time.
|
||||
*/
|
||||
1: ldr r3, [r1]
|
||||
|
||||
/* Skip adding offset if address is < lower limit */
|
||||
cmp r3, r6
|
||||
blo 2f
|
||||
|
||||
/* Skip adding offset if address is > upper limit */
|
||||
cmp r3, r7
|
||||
bhi 2f
|
||||
add r3, r3, r0
|
||||
str r3, [r1]
|
||||
|
||||
2: add r1, r1, #4
|
||||
cmp r1, r2
|
||||
blo 1b
|
||||
|
||||
/* Starting dynamic relocations. Use ldr to get RELA_START and END */
|
||||
3: ldr r1, =__RELA_START__
|
||||
add r1, r1, r0
|
||||
ldr r2, =__RELA_END__
|
||||
add r2, r2, r0
|
||||
|
||||
/*
|
||||
* According to ELF-32 specification, the RELA data structure is as
|
||||
* follows:
|
||||
* typedef struct {
|
||||
* Elf32_Addr r_offset;
|
||||
* Elf32_Xword r_info;
|
||||
* } Elf32_Rela;
|
||||
*
|
||||
* r_offset is address of reference
|
||||
* r_info is symbol index and type of relocation (in this case
|
||||
* code 23 which corresponds to R_ARM_RELATIVE).
|
||||
*
|
||||
* Size of Elf32_Rela structure is 8 bytes.
|
||||
*/
|
||||
|
||||
/* Skip R_ARM_NONE entry with code 0 */
|
||||
1: ldr r3, [r1, #4]
|
||||
ands r3, r3, #0xff
|
||||
beq 2f
|
||||
|
||||
#if ENABLE_ASSERTIONS
|
||||
/* Assert that the relocation type is R_ARM_RELATIVE */
|
||||
cmp r3, #R_ARM_RELATIVE
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
ldr r3, [r1] /* r_offset */
|
||||
add r3, r0, r3 /* Diff(S) + r_offset */
|
||||
ldr r4, [r3]
|
||||
|
||||
/* Skip adding offset if address is < lower limit */
|
||||
cmp r4, r6
|
||||
blo 2f
|
||||
|
||||
/* Skip adding offset if address is > upper limit */
|
||||
cmp r4, r7
|
||||
bhi 2f
|
||||
|
||||
add r4, r0, r4
|
||||
str r4, [r3]
|
||||
|
||||
2: add r1, r1, #8
|
||||
cmp r1, r2
|
||||
blo 1b
|
||||
bx lr
|
||||
endfunc fixup_gdt_reloc
|
||||
Reference in New Issue
Block a user