GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_features.h>
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#include <common/bl_common.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <lib/xlat_tables/xlat_tables_arch.h>
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#include <plat/common/common_def.h>
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#include "../xlat_tables_private.h"
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#define XLAT_TABLE_LEVEL_BASE \
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GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
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#define NUM_BASE_LEVEL_ENTRIES \
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GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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static unsigned long long tcr_ps_bits;
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static unsigned long long calc_physical_addr_size_bits(
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unsigned long long max_addr)
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{
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/* Physical address can't exceed 48 bits */
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assert((max_addr & ADDR_MASK_48_TO_63) == 0U);
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/* 48 bits address */
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if ((max_addr & ADDR_MASK_44_TO_47) != 0U)
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return TCR_PS_BITS_256TB;
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/* 44 bits address */
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if ((max_addr & ADDR_MASK_42_TO_43) != 0U)
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return TCR_PS_BITS_16TB;
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/* 42 bits address */
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if ((max_addr & ADDR_MASK_40_TO_41) != 0U)
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return TCR_PS_BITS_4TB;
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/* 40 bits address */
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if ((max_addr & ADDR_MASK_36_TO_39) != 0U)
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return TCR_PS_BITS_1TB;
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/* 36 bits address */
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if ((max_addr & ADDR_MASK_32_TO_35) != 0U)
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return TCR_PS_BITS_64GB;
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return TCR_PS_BITS_4GB;
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}
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#if ENABLE_ASSERTIONS
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/*
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* Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is
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* supported in ARMv8.2 onwards.
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*/
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static const unsigned int pa_range_bits_arr[] = {
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PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
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PARANGE_0101, PARANGE_0110
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};
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static unsigned long long get_max_supported_pa(void)
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{
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u_register_t pa_range = read_id_aa64mmfr0_el1() &
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ID_AA64MMFR0_EL1_PARANGE_MASK;
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/* All other values are reserved */
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assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
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return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
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}
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/*
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* Return minimum virtual address space size supported by the architecture
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*/
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static uintptr_t xlat_get_min_virt_addr_space_size(void)
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{
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uintptr_t ret;
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if (is_armv8_4_ttst_present())
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ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
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else
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ret = MIN_VIRT_ADDR_SPACE_SIZE;
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return ret;
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}
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#endif /* ENABLE_ASSERTIONS */
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unsigned int xlat_arch_current_el(void)
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{
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unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
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assert(el > 0U);
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return el;
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}
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uint64_t xlat_arch_get_xn_desc(unsigned int el)
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{
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if (el == 3U) {
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return UPPER_ATTRS(XN);
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} else {
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assert(el == 1U);
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return UPPER_ATTRS(PXN);
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}
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}
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void init_xlat_tables(void)
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{
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unsigned long long max_pa;
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uintptr_t max_va;
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assert(PLAT_VIRT_ADDR_SPACE_SIZE >=
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(xlat_get_min_virt_addr_space_size() - 1U));
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assert(PLAT_VIRT_ADDR_SPACE_SIZE <= MAX_VIRT_ADDR_SPACE_SIZE);
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assert(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE));
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print_mmap();
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init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
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assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
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assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
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tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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}
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/*******************************************************************************
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* Macro generating the code for the function enabling the MMU in the given
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* exception level, assuming that the pagetables have already been created.
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*
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* _el: Exception level at which the function will run
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* _tcr_extra: Extra bits to set in the TCR register. This mask will
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* be OR'ed with the default TCR value.
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* exception level
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******************************************************************************/
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#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
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void enable_mmu_el##_el(unsigned int flags) \
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{ \
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uint64_t mair, tcr, ttbr; \
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uint32_t sctlr; \
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\
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assert(IS_IN_EL(_el)); \
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assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0U); \
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\
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/* Set attributes in the right indices of the MAIR */ \
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
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ATTR_IWBWA_OWBWA_NTR_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
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ATTR_NON_CACHEABLE_INDEX); \
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write_mair_el##_el(mair); \
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\
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/* Invalidate TLBs at the current exception level */ \
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_tlbi_fct(); \
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\
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/* Set TCR bits as well. */ \
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/* Set T0SZ to (64 - width of virtual address space) */ \
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int t0sz = 64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);\
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\
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if ((flags & XLAT_TABLE_NC) != 0U) { \
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/* Inner & outer non-cacheable non-shareable. */\
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tcr = TCR_SH_NON_SHAREABLE | \
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TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
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((uint64_t)t0sz << TCR_T0SZ_SHIFT); \
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} else { \
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/* Inner & outer WBWA & shareable. */ \
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tcr = TCR_SH_INNER_SHAREABLE | \
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TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
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((uint64_t)t0sz << TCR_T0SZ_SHIFT); \
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} \
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tcr |= _tcr_extra; \
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) base_xlation_table; \
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write_ttbr0_el##_el(ttbr); \
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\
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/* Ensure all translation table writes have drained */ \
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/* into memory, the TLB invalidation is complete, */ \
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/* and translation register writes are committed */ \
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/* before enabling the MMU */ \
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dsbish(); \
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isb(); \
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\
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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\
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if ((flags & DISABLE_DCACHE) != 0U) \
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sctlr &= ~SCTLR_C_BIT; \
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else \
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sctlr |= SCTLR_C_BIT; \
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\
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write_sctlr_el##_el(sctlr); \
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\
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/* Ensure the MMU enable takes effect immediately */ \
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isb(); \
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} \
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\
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void enable_mmu_direct_el##_el(unsigned int flags) \
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{ \
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enable_mmu_el##_el(flags); \
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}
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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DEFINE_ENABLE_MMU_EL(1,
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/*
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* TCR_EL1.EPD1: Disable translation table walk for addresses
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* that are translated using TTBR1_EL1.
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*/
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TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT),
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tlbivmalle1)
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DEFINE_ENABLE_MMU_EL(3,
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TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
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tlbialle3)
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