GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
+39
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
static uint32_t arisc_core_off[] = {
|
||||
0x18600000, /* l.movhi r3, <corenr> */
|
||||
0x18000000, /* l.movhi r0, 0x0 */
|
||||
0x19a00170, /* l.movhi r13, 0x170 */
|
||||
0x84ad0030, /* l.lwz r5, 0x30(r13) */
|
||||
0xe0a51803, /* l.and r5, r5, r3 */
|
||||
0xe4050000, /* l.sfeq r5, r0 */
|
||||
0x13fffffd, /* l.bf -12 */
|
||||
|
||||
0xb8c30050, /* l.srli r6, r3, 16 */
|
||||
0xbc060001, /* l.sfeqi r6, 1 */
|
||||
0x10000005, /* l.bf +20 */
|
||||
0x19a001f0, /* l.movhi r13, 0x1f0 */
|
||||
0x84ad1500, /* l.lwz r5, 0x1500(r13) */
|
||||
0xe0a53004, /* l.or r5, r5, r6 */
|
||||
0xd44d2d00, /* l.sw 0x1500(r13), r5 */
|
||||
|
||||
0x84ad1c30, /* l.lwz r5, 0x1c30(r13) */
|
||||
0xacc6ffff, /* l.xori r6, r6, -1 */
|
||||
0xe0a53003, /* l.and r5, r5, r6 */
|
||||
0xd46d2c30, /* l.sw 0x1c30(r13), r5 */
|
||||
|
||||
0xe0c3000f, /* l.ff1 r6, r3 */
|
||||
0x9cc6ffef, /* l.addi r6, r6, -17 */
|
||||
0xb8c60002, /* l.slli r6, r6, 2 */
|
||||
0xe0c66800, /* l.add r6, r6, r13 */
|
||||
0xa8a000ff, /* l.ori r5, r0, 0xff */
|
||||
0xd4462d40, /* l.sw 0x1540(r6), r5 */
|
||||
|
||||
0xd46d0400, /* l.sw 0x1c00(r13), r0 */
|
||||
0x03ffffff, /* l.j -1 */
|
||||
0x15000000, /* l.nop */
|
||||
};
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SUNXI_CCU_H
|
||||
#define SUNXI_CCU_H
|
||||
|
||||
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x02f0)
|
||||
|
||||
#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x01d0)
|
||||
|
||||
#endif /* SUNXI_CCU_H */
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SUNXI_CPUCFG_H
|
||||
#define SUNXI_CPUCFG_H
|
||||
|
||||
#include <sunxi_mmap.h>
|
||||
|
||||
/* c = cluster, n = core */
|
||||
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 16)
|
||||
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0004 + (c) * 16)
|
||||
#define SUNXI_CPUCFG_CACHE_CFG_REG0 (SUNXI_CPUCFG_BASE + 0x0008)
|
||||
#define SUNXI_CPUCFG_CACHE_CFG_REG1 (SUNXI_CPUCFG_BASE + 0x000c)
|
||||
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x0020)
|
||||
#define SUNXI_CPUCFG_GLB_CTRL_REG (SUNXI_CPUCFG_BASE + 0x0028)
|
||||
#define SUNXI_CPUCFG_CPU_STS_REG(c) (SUNXI_CPUCFG_BASE + 0x0030 + (c) * 4)
|
||||
#define SUNXI_CPUCFG_L2_STS_REG (SUNXI_CPUCFG_BASE + 0x003c)
|
||||
#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0080 + (c) * 4)
|
||||
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8)
|
||||
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8)
|
||||
|
||||
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \
|
||||
(c) * 16 + (n) * 4)
|
||||
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_PRCM_BASE + 0x0100 + (c) * 4)
|
||||
#define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000)
|
||||
#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4)
|
||||
#define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
|
||||
#define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0)
|
||||
#define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4)
|
||||
#define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8)
|
||||
#define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac)
|
||||
|
||||
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
|
||||
#define SUNXI_AA64nAA32_OFFSET 24
|
||||
|
||||
#endif /* SUNXI_CPUCFG_H */
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SUNXI_MMAP_H
|
||||
#define SUNXI_MMAP_H
|
||||
|
||||
/* Memory regions */
|
||||
#define SUNXI_ROM_BASE 0x00000000
|
||||
#define SUNXI_ROM_SIZE 0x00010000
|
||||
#define SUNXI_SRAM_BASE 0x00010000
|
||||
#define SUNXI_SRAM_SIZE 0x00044000
|
||||
#define SUNXI_SRAM_A1_BASE 0x00010000
|
||||
#define SUNXI_SRAM_A1_SIZE 0x00008000
|
||||
#define SUNXI_SRAM_A2_BASE 0x00040000
|
||||
#define SUNXI_SRAM_A2_BL31_OFFSET 0x00004000
|
||||
#define SUNXI_SRAM_A2_SIZE 0x00014000
|
||||
#define SUNXI_SRAM_C_BASE 0x00018000
|
||||
#define SUNXI_SRAM_C_SIZE 0x0001c000
|
||||
#define SUNXI_DEV_BASE 0x01000000
|
||||
#define SUNXI_DEV_SIZE 0x01000000
|
||||
#define SUNXI_DRAM_BASE 0x40000000
|
||||
#define SUNXI_DRAM_VIRT_BASE 0x02000000
|
||||
|
||||
/* Memory-mapped devices */
|
||||
#define SUNXI_CPU_MBIST_BASE 0x01502000
|
||||
#define SUNXI_CPUCFG_BASE 0x01700000
|
||||
#define SUNXI_SYSCON_BASE 0x01c00000
|
||||
#define SUNXI_DMA_BASE 0x01c02000
|
||||
#define SUNXI_KEYMEM_BASE 0x01c0b000
|
||||
#define SUNXI_SMHC0_BASE 0x01c0f000
|
||||
#define SUNXI_SMHC1_BASE 0x01c10000
|
||||
#define SUNXI_SMHC2_BASE 0x01c11000
|
||||
#define SUNXI_SID_BASE 0x01c14000
|
||||
#define SUNXI_MSGBOX_BASE 0x01c17000
|
||||
#define SUNXI_SPINLOCK_BASE 0x01c18000
|
||||
#define SUNXI_CCU_BASE 0x01c20000
|
||||
#define SUNXI_PIO_BASE 0x01c20800
|
||||
#define SUNXI_TIMER_BASE 0x01c20c00
|
||||
#define SUNXI_WDOG_BASE 0x01c20ca0
|
||||
#define SUNXI_SPC_BASE 0x01c23400
|
||||
#define SUNXI_THS_BASE 0x01c25000
|
||||
#define SUNXI_UART0_BASE 0x01c28000
|
||||
#define SUNXI_UART1_BASE 0x01c28400
|
||||
#define SUNXI_UART2_BASE 0x01c28800
|
||||
#define SUNXI_UART3_BASE 0x01c28c00
|
||||
#define SUNXI_I2C0_BASE 0x01c2ac00
|
||||
#define SUNXI_I2C1_BASE 0x01c2b000
|
||||
#define SUNXI_I2C2_BASE 0x01c2b400
|
||||
#define SUNXI_DRAMCOM_BASE 0x01c62000
|
||||
#define SUNXI_DRAMCTL_BASE 0x01c63000
|
||||
#define SUNXI_DRAMPHY_BASE 0x01c65000
|
||||
#define SUNXI_SPI0_BASE 0x01c68000
|
||||
#define SUNXI_SPI1_BASE 0x01c69000
|
||||
#define SUNXI_SCU_BASE 0x01c80000
|
||||
#define SUNXI_GICD_BASE 0x01c81000
|
||||
#define SUNXI_GICC_BASE 0x01c82000
|
||||
#define SUNXI_RTC_BASE 0x01f00000
|
||||
#define SUNXI_R_TIMER_BASE 0x01f00800
|
||||
#define SUNXI_R_INTC_BASE 0x01f00c00
|
||||
#define SUNXI_R_WDOG_BASE 0x01f01000
|
||||
#define SUNXI_R_PRCM_BASE 0x01f01400
|
||||
#define SUNXI_R_TWD_BASE 0x01f01800
|
||||
#define SUNXI_R_CPUCFG_BASE 0x01f01c00
|
||||
#define SUNXI_R_CIR_BASE 0x01f02000
|
||||
#define SUNXI_R_I2C_BASE 0x01f02400
|
||||
#define SUNXI_R_UART_BASE 0x01f02800
|
||||
#define SUNXI_R_PIO_BASE 0x01f02c00
|
||||
#define SUNXI_R_RSB_BASE 0x01f03400
|
||||
#define SUNXI_R_PWM_BASE 0x01f03800
|
||||
|
||||
#endif /* SUNXI_MMAP_H */
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SUNXI_SPC_H
|
||||
#define SUNXI_SPC_H
|
||||
|
||||
#define SUNXI_SPC_NUM_PORTS 6
|
||||
|
||||
#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x0c * (p))
|
||||
#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x0c * (p))
|
||||
#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x000c + 0x0c * (p))
|
||||
|
||||
#endif /* SUNXI_SPC_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
#
|
||||
# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# The differences between the platform are covered by the include files.
|
||||
include plat/allwinner/common/allwinner-common.mk
|
||||
|
||||
BL31_SOURCES += drivers/allwinner/axp/axp803.c \
|
||||
drivers/allwinner/sunxi_rsb.c
|
||||
|
||||
FDT_ASSUME_MASK := "(ASSUME_LATEST | ASSUME_NO_ROLLBACK | ASSUME_LIBFDT_ORDER)"
|
||||
$(eval $(call add_define,FDT_ASSUME_MASK))
|
||||
|
||||
# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
|
||||
SEPARATE_NOBITS_REGION := 1
|
||||
+27
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <sunxi_private.h>
|
||||
|
||||
const struct psci_cpu_idle_state sunxi_idle_states[] = {
|
||||
{
|
||||
.name = "cpu-sleep",
|
||||
.power_state = 0x00010003,
|
||||
.local_timer_stop = true,
|
||||
.entry_latency_us = 800,
|
||||
.exit_latency_us = 1500,
|
||||
.min_residency_us = 25000
|
||||
},
|
||||
{
|
||||
.name = "cluster-sleep",
|
||||
.power_state = 0x01010013,
|
||||
.local_timer_stop = true,
|
||||
.entry_latency_us = 850,
|
||||
.exit_latency_us = 1500,
|
||||
.min_residency_us = 50000
|
||||
},
|
||||
{}
|
||||
};
|
||||
+259
@@ -0,0 +1,259 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/allwinner/axp.h>
|
||||
#include <drivers/allwinner/sunxi_rsb.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <core_off_arisc.h>
|
||||
#include <sunxi_def.h>
|
||||
#include <sunxi_mmap.h>
|
||||
#include <sunxi_private.h>
|
||||
|
||||
static enum pmic_type {
|
||||
UNKNOWN,
|
||||
GENERIC_H5,
|
||||
GENERIC_A64,
|
||||
REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
|
||||
AXP803_RSB, /* PMIC connected via RSB on most A64 boards */
|
||||
} pmic;
|
||||
|
||||
#define AXP803_HW_ADDR 0x3a3
|
||||
#define AXP803_RT_ADDR 0x2d
|
||||
|
||||
/*
|
||||
* On boards without a proper PMIC we struggle to turn off the system properly.
|
||||
* Try to turn off as much off the system as we can, to reduce power
|
||||
* consumption. This should be entered with only one core running and SMP
|
||||
* disabled.
|
||||
* This function only cares about peripherals.
|
||||
*/
|
||||
static void sunxi_turn_off_soc(uint16_t socid)
|
||||
{
|
||||
int i;
|
||||
|
||||
/** Turn off most peripherals, most importantly DRAM users. **/
|
||||
/* Keep DRAM controller running for now. */
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14));
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14));
|
||||
/* Contains msgbox (bit 21) and spinlock (bit 22) */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0);
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x64, 0);
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0);
|
||||
/* Keep PIO controller running for now. */
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5)));
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0);
|
||||
/* Contains UART0 (bit 16) */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0);
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0);
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x70, 0);
|
||||
|
||||
/** Turn off DRAM controller. **/
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14));
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14));
|
||||
|
||||
/** Migrate CPU and bus clocks away from the PLLs. **/
|
||||
/* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000);
|
||||
/* APB2: use OSC24M */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000);
|
||||
/* AHB2: use AHB1 clock */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0);
|
||||
/* CPU: use OSC24M */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000);
|
||||
|
||||
/** Turn off PLLs. **/
|
||||
for (i = 0; i < 6; i++)
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31));
|
||||
switch (socid) {
|
||||
case SUNXI_SOC_H5:
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31));
|
||||
break;
|
||||
case SUNXI_SOC_A64:
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31));
|
||||
mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int rsb_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = rsb_init_controller();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Switch to the recommended 3 MHz bus clock. */
|
||||
ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
|
||||
ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Associate the 8-bit runtime address with the 12-bit bus address. */
|
||||
ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
|
||||
AXP803_RT_ADDR);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return axp_check_id();
|
||||
}
|
||||
|
||||
int axp_read(uint8_t reg)
|
||||
{
|
||||
return rsb_read(AXP803_RT_ADDR, reg);
|
||||
}
|
||||
|
||||
int axp_write(uint8_t reg, uint8_t val)
|
||||
{
|
||||
return rsb_write(AXP803_RT_ADDR, reg, val);
|
||||
}
|
||||
|
||||
int sunxi_pmic_setup(uint16_t socid, const void *fdt)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (socid) {
|
||||
case SUNXI_SOC_H5:
|
||||
NOTICE("PMIC: Assuming H5 reference regulator design\n");
|
||||
|
||||
pmic = REF_DESIGN_H5;
|
||||
|
||||
break;
|
||||
case SUNXI_SOC_A64:
|
||||
pmic = GENERIC_A64;
|
||||
|
||||
INFO("PMIC: Probing AXP803 on RSB\n");
|
||||
|
||||
ret = sunxi_init_platform_r_twi(socid, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rsb_init();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmic = AXP803_RSB;
|
||||
axp_setup_regulators(fdt);
|
||||
|
||||
/* Switch the PMIC back to I2C mode. */
|
||||
ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
break;
|
||||
default:
|
||||
return -ENODEV;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sunxi_power_down(void)
|
||||
{
|
||||
switch (pmic) {
|
||||
case GENERIC_H5:
|
||||
/* Turn off as many peripherals and clocks as we can. */
|
||||
sunxi_turn_off_soc(SUNXI_SOC_H5);
|
||||
/* Turn off the pin controller now. */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
|
||||
break;
|
||||
case GENERIC_A64:
|
||||
/* Turn off as many peripherals and clocks as we can. */
|
||||
sunxi_turn_off_soc(SUNXI_SOC_A64);
|
||||
/* Turn off the pin controller now. */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
|
||||
break;
|
||||
case REF_DESIGN_H5:
|
||||
sunxi_turn_off_soc(SUNXI_SOC_H5);
|
||||
|
||||
/*
|
||||
* Switch PL pins to power off the board:
|
||||
* - PL5 (VCC_IO) -> high
|
||||
* - PL8 (PWR-STB = CPU power supply) -> low
|
||||
* - PL9 (PWR-DRAM) ->low
|
||||
* - PL10 (power LED) -> low
|
||||
* Note: Clearing PL8 will reset the board, so keep it up.
|
||||
*/
|
||||
sunxi_set_gpio_out('L', 5, 1);
|
||||
sunxi_set_gpio_out('L', 9, 0);
|
||||
sunxi_set_gpio_out('L', 10, 0);
|
||||
|
||||
/* Turn off pin controller now. */
|
||||
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
|
||||
|
||||
break;
|
||||
case AXP803_RSB:
|
||||
/* (Re-)init RSB in case the rich OS has disabled it. */
|
||||
sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
|
||||
rsb_init();
|
||||
axp_power_off();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* This lock synchronises access to the arisc management processor. */
|
||||
static DEFINE_BAKERY_LOCK(arisc_lock);
|
||||
|
||||
/*
|
||||
* If we are supposed to turn ourself off, tell the arisc SCP to do that
|
||||
* work for us. Without any SCPI provider running there, we place some
|
||||
* OpenRISC code into SRAM, put the address of that into the reset vector
|
||||
* and release the arisc reset line. The SCP will wait for the core to enter
|
||||
* WFI, then execute that code and pull the line up again.
|
||||
* The code expects the core mask to be patched into the first instruction.
|
||||
*/
|
||||
void sunxi_cpu_power_off_self(void)
|
||||
{
|
||||
u_register_t mpidr = read_mpidr();
|
||||
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
|
||||
uint32_t *code = arisc_core_off;
|
||||
|
||||
do {
|
||||
bakery_lock_get(&arisc_lock);
|
||||
/* Wait until the arisc is in reset state. */
|
||||
if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
|
||||
break;
|
||||
|
||||
bakery_lock_release(&arisc_lock);
|
||||
} while (1);
|
||||
|
||||
/* Patch up the code to feed in an input parameter. */
|
||||
code[0] = (code[0] & ~0xffff) | BIT_32(core);
|
||||
clean_dcache_range((uintptr_t)code, sizeof(arisc_core_off));
|
||||
|
||||
/*
|
||||
* The OpenRISC unconditional branch has opcode 0, the branch offset
|
||||
* is in the lower 26 bits, containing the distance to the target,
|
||||
* in instruction granularity (32 bits).
|
||||
*/
|
||||
mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
|
||||
|
||||
/* De-assert the arisc reset line to let it run. */
|
||||
mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
|
||||
|
||||
/*
|
||||
* We release the lock here, although the arisc is still busy.
|
||||
* But as long as it runs, the reset line is high, so other users
|
||||
* won't leave the loop above.
|
||||
* Once it has finished, the code is supposed to clear the reset line,
|
||||
* to signal this to other users.
|
||||
*/
|
||||
bakery_lock_release(&arisc_lock);
|
||||
}
|
||||
Reference in New Issue
Block a user