GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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static uint32_t arisc_core_off[] = {
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0x18600000, /* l.movhi r3, <corenr> */
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0x18000000, /* l.movhi r0, 0x0 */
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0x19a00170, /* l.movhi r13, 0x170 */
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0x84ad0030, /* l.lwz r5, 0x30(r13) */
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0xe0a51803, /* l.and r5, r5, r3 */
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0xe4050000, /* l.sfeq r5, r0 */
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0x13fffffd, /* l.bf -12 */
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0xb8c30050, /* l.srli r6, r3, 16 */
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0xbc060001, /* l.sfeqi r6, 1 */
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0x10000005, /* l.bf +20 */
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0x19a001f0, /* l.movhi r13, 0x1f0 */
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0x84ad1500, /* l.lwz r5, 0x1500(r13) */
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0xe0a53004, /* l.or r5, r5, r6 */
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0xd44d2d00, /* l.sw 0x1500(r13), r5 */
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0x84ad1c30, /* l.lwz r5, 0x1c30(r13) */
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0xacc6ffff, /* l.xori r6, r6, -1 */
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0xe0a53003, /* l.and r5, r5, r6 */
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0xd46d2c30, /* l.sw 0x1c30(r13), r5 */
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0xe0c3000f, /* l.ff1 r6, r3 */
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0x9cc6ffef, /* l.addi r6, r6, -17 */
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0xb8c60002, /* l.slli r6, r6, 2 */
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0xe0c66800, /* l.add r6, r6, r13 */
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0xa8a000ff, /* l.ori r5, r0, 0xff */
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0xd4462d40, /* l.sw 0x1540(r6), r5 */
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0xd46d0400, /* l.sw 0x1c00(r13), r0 */
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0x03ffffff, /* l.j -1 */
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0x15000000, /* l.nop */
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};
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SUNXI_CCU_H
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#define SUNXI_CCU_H
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#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x02f0)
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#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x01d0)
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#endif /* SUNXI_CCU_H */
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SUNXI_CPUCFG_H
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#define SUNXI_CPUCFG_H
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#include <sunxi_mmap.h>
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/* c = cluster, n = core */
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#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 16)
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#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0004 + (c) * 16)
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#define SUNXI_CPUCFG_CACHE_CFG_REG0 (SUNXI_CPUCFG_BASE + 0x0008)
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#define SUNXI_CPUCFG_CACHE_CFG_REG1 (SUNXI_CPUCFG_BASE + 0x000c)
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#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x0020)
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#define SUNXI_CPUCFG_GLB_CTRL_REG (SUNXI_CPUCFG_BASE + 0x0028)
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#define SUNXI_CPUCFG_CPU_STS_REG(c) (SUNXI_CPUCFG_BASE + 0x0030 + (c) * 4)
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#define SUNXI_CPUCFG_L2_STS_REG (SUNXI_CPUCFG_BASE + 0x003c)
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#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0080 + (c) * 4)
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#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8)
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#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8)
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#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \
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(c) * 16 + (n) * 4)
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#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_PRCM_BASE + 0x0100 + (c) * 4)
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#define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000)
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#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4)
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#define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
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#define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0)
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#define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4)
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#define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8)
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#define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac)
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#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
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#define SUNXI_AA64nAA32_OFFSET 24
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#endif /* SUNXI_CPUCFG_H */
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SUNXI_MMAP_H
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#define SUNXI_MMAP_H
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/* Memory regions */
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#define SUNXI_ROM_BASE 0x00000000
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#define SUNXI_ROM_SIZE 0x00010000
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#define SUNXI_SRAM_BASE 0x00010000
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#define SUNXI_SRAM_SIZE 0x00044000
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#define SUNXI_SRAM_A1_BASE 0x00010000
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#define SUNXI_SRAM_A1_SIZE 0x00008000
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#define SUNXI_SRAM_A2_BASE 0x00040000
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#define SUNXI_SRAM_A2_BL31_OFFSET 0x00004000
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#define SUNXI_SRAM_A2_SIZE 0x00014000
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#define SUNXI_SRAM_C_BASE 0x00018000
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#define SUNXI_SRAM_C_SIZE 0x0001c000
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#define SUNXI_DEV_BASE 0x01000000
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#define SUNXI_DEV_SIZE 0x01000000
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#define SUNXI_DRAM_BASE 0x40000000
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#define SUNXI_DRAM_VIRT_BASE 0x02000000
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/* Memory-mapped devices */
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#define SUNXI_CPU_MBIST_BASE 0x01502000
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#define SUNXI_CPUCFG_BASE 0x01700000
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#define SUNXI_SYSCON_BASE 0x01c00000
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#define SUNXI_DMA_BASE 0x01c02000
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#define SUNXI_KEYMEM_BASE 0x01c0b000
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#define SUNXI_SMHC0_BASE 0x01c0f000
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#define SUNXI_SMHC1_BASE 0x01c10000
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#define SUNXI_SMHC2_BASE 0x01c11000
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#define SUNXI_SID_BASE 0x01c14000
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#define SUNXI_MSGBOX_BASE 0x01c17000
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#define SUNXI_SPINLOCK_BASE 0x01c18000
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#define SUNXI_CCU_BASE 0x01c20000
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#define SUNXI_PIO_BASE 0x01c20800
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#define SUNXI_TIMER_BASE 0x01c20c00
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#define SUNXI_WDOG_BASE 0x01c20ca0
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#define SUNXI_SPC_BASE 0x01c23400
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#define SUNXI_THS_BASE 0x01c25000
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#define SUNXI_UART0_BASE 0x01c28000
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#define SUNXI_UART1_BASE 0x01c28400
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#define SUNXI_UART2_BASE 0x01c28800
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#define SUNXI_UART3_BASE 0x01c28c00
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#define SUNXI_I2C0_BASE 0x01c2ac00
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#define SUNXI_I2C1_BASE 0x01c2b000
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#define SUNXI_I2C2_BASE 0x01c2b400
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#define SUNXI_DRAMCOM_BASE 0x01c62000
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#define SUNXI_DRAMCTL_BASE 0x01c63000
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#define SUNXI_DRAMPHY_BASE 0x01c65000
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#define SUNXI_SPI0_BASE 0x01c68000
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#define SUNXI_SPI1_BASE 0x01c69000
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#define SUNXI_SCU_BASE 0x01c80000
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#define SUNXI_GICD_BASE 0x01c81000
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#define SUNXI_GICC_BASE 0x01c82000
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#define SUNXI_RTC_BASE 0x01f00000
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#define SUNXI_R_TIMER_BASE 0x01f00800
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#define SUNXI_R_INTC_BASE 0x01f00c00
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#define SUNXI_R_WDOG_BASE 0x01f01000
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#define SUNXI_R_PRCM_BASE 0x01f01400
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#define SUNXI_R_TWD_BASE 0x01f01800
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#define SUNXI_R_CPUCFG_BASE 0x01f01c00
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#define SUNXI_R_CIR_BASE 0x01f02000
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#define SUNXI_R_I2C_BASE 0x01f02400
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#define SUNXI_R_UART_BASE 0x01f02800
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#define SUNXI_R_PIO_BASE 0x01f02c00
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#define SUNXI_R_RSB_BASE 0x01f03400
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#define SUNXI_R_PWM_BASE 0x01f03800
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#endif /* SUNXI_MMAP_H */
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SUNXI_SPC_H
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#define SUNXI_SPC_H
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#define SUNXI_SPC_NUM_PORTS 6
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#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x0c * (p))
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#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x0c * (p))
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#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x000c + 0x0c * (p))
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#endif /* SUNXI_SPC_H */
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