GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
+27
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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nt_fw-config {
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load-address = <0x0 0xFEF00000>;
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max-size = <0x0100000>;
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id = <NT_FW_CONFIG_ID>;
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};
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};
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};
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+22
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* compatible string */
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compatible = "arm,rd-n1edge";
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/*
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* Place holder for system-id node with default values. The
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* value of platform-id and config-id will be set to the
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* correct values during the BL2 stage of boot.
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*/
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system-id {
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platform-id = <0x0>;
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config-id = <0x0>;
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multi-chip-mode = <0x0>;
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};
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};
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+27
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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tb_fw-config {
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compatible = "arm,tb_fw";
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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};
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+54
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/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_sdei.h>
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#include <sgi_soc_platform_def.h>
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#define PLAT_ARM_CLUSTER_COUNT U(2)
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
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#define CSS_SGI_MAX_PE_PER_CPU U(1)
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
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#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/* Virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
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/* Maximum number of address bits used per chip */
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#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
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CSS_SGI_CHIP_COUNT)
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#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
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CSS_SGI_CHIP_COUNT)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x300C0000)
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#endif /* PLATFORM_DEF_H */
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@@ -0,0 +1,75 @@
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#
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# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
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# GIC-600 configuration
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GICV3_IMPL_GIC600_MULTICHIP := 1
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include plat/arm/css/sgi/sgi-common.mk
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RDN1EDGE_BASE = plat/arm/board/rdn1edge
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PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
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PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
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BL1_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN1EDGE_BASE}/rdn1edge_err.c
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BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \
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${RDN1EDGE_BASE}/rdn1edge_security.c \
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${RDN1EDGE_BASE}/rdn1edge_err.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN1EDGE_BASE}/rdn1edge_plat.c \
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${RDN1EDGE_BASE}/rdn1edge_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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BL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
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BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
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endif
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# Enable dynamic addition of MMAP regions in BL31
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BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
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${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
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$(eval $(call CREATE_SEQ,SEQ,2))
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ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
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$(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
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set to ${CSS_SGI_CHIP_COUNT}.")
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endif
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ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
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$(error "CSS_SGI_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
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currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
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endif
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override CTX_INCLUDE_AARCH32_REGS := 0
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@@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*
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* rdn1edge error handler
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*/
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void __dead2 plat_arm_error_handler(int err)
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{
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while (true) {
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wfi();
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}
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}
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+97
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/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/gic600_multichip.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <sgi_soc_platform_def.h>
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#include <sgi_plat.h>
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#if defined(IMAGE_BL31)
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static const mmap_region_t rdn1edge_dynamic_mmap[] = {
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ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
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CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
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SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1)
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};
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static struct gic600_multichip_data rdn1e1_multichip_data __init = {
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.rt_owner_base = PLAT_ARM_GICD_BASE,
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.rt_owner = 0,
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.chip_count = CSS_SGI_CHIP_COUNT,
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.chip_addrs = {
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PLAT_ARM_GICD_BASE >> 16,
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(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
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},
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.spi_ids = {
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{PLAT_ARM_GICD_BASE, 32, 255},
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{0, 0, 0}
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}
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};
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static uintptr_t rdn1e1_multichip_gicr_frames[] = {
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PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
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PLAT_ARM_GICR_BASE +
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CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
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UL(0) /* Zero Termination */
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};
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#endif /* IMAGE_BL31 */
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unsigned int plat_arm_sgi_get_platform_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
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& SID_SYSTEM_ID_PART_NUM_MASK;
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}
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unsigned int plat_arm_sgi_get_config_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
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}
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unsigned int plat_arm_sgi_get_multi_chip_mode(void)
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{
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return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
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SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
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}
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/*
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* IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31
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* because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
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* for other stages.
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*/
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#if defined(IMAGE_BL31)
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void bl31_platform_setup(void)
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{
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int i, ret;
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if (plat_arm_sgi_get_multi_chip_mode() == 0 && CSS_SGI_CHIP_COUNT > 1) {
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ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
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CSS_SGI_CHIP_COUNT);
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panic();
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} else if (plat_arm_sgi_get_multi_chip_mode() == 1 &&
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CSS_SGI_CHIP_COUNT > 1) {
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INFO("Enabling support for multi-chip in RD-N1-Edge\n");
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for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {
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ret = mmap_add_dynamic_region(
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rdn1edge_dynamic_mmap[i].base_pa,
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rdn1edge_dynamic_mmap[i].base_va,
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rdn1edge_dynamic_mmap[i].size,
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rdn1edge_dynamic_mmap[i].attr
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);
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if (ret != 0) {
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ERROR("Failed to add dynamic mmap entry\n");
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panic();
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}
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}
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plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames);
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gic600_multichip_init(&rdn1e1_multichip_data);
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}
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sgi_bl31_common_platform_setup();
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}
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#endif /* IMAGE_BL31 */
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+36
@@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/debug.h>
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#include <sgi_dmc620_tzc_regions.h>
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uintptr_t rdn1edge_dmc_base[] = {
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RDN1EDGE_DMC620_BASE0,
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RDN1EDGE_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
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.dmc_base = rdn1edge_dmc_base,
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.dmc_count = ARRAY_SIZE(rdn1edge_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
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CSS_SGI_DMC620_TZC_REGIONS_DEF
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};
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static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
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.plat_drv_data = &rdn1edge_plat_driver_data,
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.plat_acc_addr_data = rdn1edge_acc_addr_data,
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.acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data)
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};
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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arm_tzc_dmc620_setup(&rdn1edge_plat_config_data);
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}
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+54
@@ -0,0 +1,54 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/css/common/css_pm.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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static const unsigned char rdn1edge_pd_tree_desc[] = {
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(PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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#if (CSS_SGI_CHIP_COUNT > 1)
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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#endif
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return rdn1edge_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
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#if (CSS_SGI_CHIP_COUNT > 1)
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
|
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
|
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x4)),
|
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x5)),
|
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(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x6)),
|
||||
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x7)),
|
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#endif
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||||
};
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||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
Reference in New Issue
Block a user