GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
+27
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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nt_fw-config {
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load-address = <0x0 0xFEF00000>;
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max-size = <0x0100000>;
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id = <NT_FW_CONFIG_ID>;
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};
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};
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};
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+43
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/*
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* Copyright (c) 2020 - 2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* compatible string */
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compatible = "arm,rd-n2";
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/*
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* Place holder for system-id node with default values. The
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* value of platform-id and config-id will be set to the
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* correct values during the BL2 stage of boot.
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*/
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system-id {
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platform-id = <0x0>;
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config-id = <0x0>;
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multi-chip-mode = <0x0>;
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/*
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* First cell pair: Count of isolated CPUs in the list.
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* Rest of the cells: MPID list of the isolated CPUs.
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*/
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isolated-cpu-list = <0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0
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0x0 0x0>;
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};
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};
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+28
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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tb_fw-config {
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compatible = "arm,tb_fw";
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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};
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+103
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/*
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* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_soc_platform_def_v2.h>
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#if (CSS_SGI_PLATFORM_VARIANT == 1)
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#define PLAT_ARM_CLUSTER_COUNT U(8)
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#elif (CSS_SGI_PLATFORM_VARIANT == 2)
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#define PLAT_ARM_CLUSTER_COUNT U(4)
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#else
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#define PLAT_ARM_CLUSTER_COUNT U(16)
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#endif
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
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#define CSS_SGI_MAX_PE_PER_CPU U(1)
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#define PLAT_CSS_MHU_BASE UL(0x2A920000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/* TZC Related Constants */
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#define PLAT_ARM_TZC_BASE UL(0x10720000)
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
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#define TZC400_OFFSET UL(0x1000000)
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#if (CSS_SGI_PLATFORM_VARIANT == 1)
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#define TZC400_COUNT U(2)
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#elif (CSS_SGI_PLATFORM_VARIANT == 2)
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#define TZC400_COUNT U(4)
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#else
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#define TZC400_COUNT U(8)
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#endif
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#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
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(n * TZC400_OFFSET))
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#define TZC_NSAID_ALL_AP U(0)
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#define TZC_NSAID_PCI U(1)
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#define TZC_NSAID_HDLCD0 U(2)
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#define TZC_NSAID_DMA U(5)
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#define TZC_NSAID_DMA2 U(8)
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#define TZC_NSAID_CLCD U(7)
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#define TZC_NSAID_AP U(9)
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#define TZC_NSAID_VIRTIO U(15)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#if (CSS_SGI_PLATFORM_VARIANT == 2)
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#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */
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#else
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#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */
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#endif
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#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
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CSS_SGI_CHIP_COUNT)
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#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
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CSS_SGI_CHIP_COUNT)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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/* Virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
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#if (CSS_SGI_PLATFORM_VARIANT == 1)
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#define PLAT_ARM_GICR_BASE UL(0x30100000)
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#else
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#define PLAT_ARM_GICR_BASE UL(0x301C0000)
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#endif
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/* Interrupt priority level for shutdown/reboot */
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#define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY
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#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
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#endif /* PLATFORM_DEF_H */
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@@ -0,0 +1,90 @@
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# Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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RD_N2_VARIANTS := 0 1 2
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ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
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$(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
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$(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1 or 2, currently set \
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to ${CSS_SGI_PLATFORM_VARIANT}.")
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endif
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$(eval $(call CREATE_SEQ,SEQ,4))
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ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
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$(error "Chip count for RD-N2-MC should be either $(SEQ) \
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currently it is set to ${CSS_SGI_CHIP_COUNT}.")
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endif
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# RD-N2 platform uses GIC-700 which is based on GICv4.1
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GIC_ENABLE_V4_EXTN := 1
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GIC_EXT_INTID := 1
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#Enable GIC Multichip Extension only for Multichip Platforms
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ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
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GICV3_IMPL_GIC600_MULTICHIP := 1
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endif
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override CSS_SYSTEM_GRACEFUL_RESET := 1
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override EL3_EXCEPTION_HANDLING := 1
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include plat/arm/css/sgi/sgi-common.mk
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RDN2_BASE = plat/arm/board/rdn2
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PLAT_INCLUDES += -I${RDN2_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
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lib/cpus/aarch64/neoverse_v2.S
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PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c
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BL1_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN2_BASE}/rdn2_err.c
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BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
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${RDN2_BASE}/rdn2_security.c \
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${RDN2_BASE}/rdn2_err.c \
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lib/utils/mem_region.c \
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drivers/arm/tzc/tzc400.c \
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plat/arm/common/arm_tzc400.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN2_BASE}/rdn2_plat.c \
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${RDN2_BASE}/rdn2_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
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BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
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endif
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ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
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BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
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# Enable dynamic addition of MMAP regions in BL31
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BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
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endif
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
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${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
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override CTX_INCLUDE_AARCH32_REGS := 0
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override ENABLE_AMU := 1
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@@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*
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* rdn2 error handler
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*/
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void __dead2 plat_arm_error_handler(int err)
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{
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while (1) {
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wfi();
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}
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}
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@@ -0,0 +1,138 @@
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/*
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* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
|
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/gic600_multichip.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <sgi_soc_platform_def_v2.h>
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#include <sgi_plat.h>
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#if defined(IMAGE_BL31)
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#if (CSS_SGI_PLATFORM_VARIANT == 2)
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static const mmap_region_t rdn2mc_dynamic_mmap[] = {
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#if CSS_SGI_CHIP_COUNT > 1
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ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
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CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
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#endif
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#if CSS_SGI_CHIP_COUNT > 2
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ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
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CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
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#endif
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#if CSS_SGI_CHIP_COUNT > 3
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ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
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CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
|
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#endif
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};
|
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#endif
|
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#if (CSS_SGI_PLATFORM_VARIANT == 2)
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static struct gic600_multichip_data rdn2mc_multichip_data __init = {
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.rt_owner_base = PLAT_ARM_GICD_BASE,
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.rt_owner = 0,
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.chip_count = CSS_SGI_CHIP_COUNT,
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.chip_addrs = {
|
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PLAT_ARM_GICD_BASE >> 16,
|
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#if CSS_SGI_CHIP_COUNT > 1
|
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(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
|
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#endif
|
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#if CSS_SGI_CHIP_COUNT > 2
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(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
|
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#endif
|
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#if CSS_SGI_CHIP_COUNT > 3
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(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
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#endif
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},
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.spi_ids = {
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{PLAT_ARM_GICD_BASE, 32, 511},
|
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#if CSS_SGI_CHIP_COUNT > 1
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{PLAT_ARM_GICD_BASE, 512, 991},
|
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#endif
|
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#if CSS_SGI_CHIP_COUNT > 2
|
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{PLAT_ARM_GICD_BASE, 4096, 4575},
|
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#endif
|
||||
#if CSS_SGI_CHIP_COUNT > 3
|
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{PLAT_ARM_GICD_BASE, 4576, 5055},
|
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#endif
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 2)
|
||||
static uintptr_t rdn2mc_multichip_gicr_frames[] = {
|
||||
/* Chip 0's GICR Base */
|
||||
PLAT_ARM_GICR_BASE,
|
||||
#if CSS_SGI_CHIP_COUNT > 1
|
||||
/* Chip 1's GICR BASE */
|
||||
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
|
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#endif
|
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#if CSS_SGI_CHIP_COUNT > 2
|
||||
/* Chip 2's GICR BASE */
|
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PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
|
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#endif
|
||||
#if CSS_SGI_CHIP_COUNT > 3
|
||||
/* Chip 3's GICR BASE */
|
||||
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
|
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#endif
|
||||
UL(0) /* Zero Termination */
|
||||
};
|
||||
#endif
|
||||
#endif /* IMAGE_BL31 */
|
||||
|
||||
unsigned int plat_arm_sgi_get_platform_id(void)
|
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{
|
||||
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
|
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& SID_SYSTEM_ID_PART_NUM_MASK;
|
||||
}
|
||||
|
||||
unsigned int plat_arm_sgi_get_config_id(void)
|
||||
{
|
||||
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
|
||||
}
|
||||
|
||||
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
|
||||
{
|
||||
return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
|
||||
SID_MULTI_CHIP_MODE_MASK) >>
|
||||
SID_MULTI_CHIP_MODE_SHIFT;
|
||||
}
|
||||
|
||||
#if defined(IMAGE_BL31)
|
||||
void bl31_platform_setup(void)
|
||||
{
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 2)
|
||||
int ret;
|
||||
unsigned int i;
|
||||
|
||||
if (plat_arm_sgi_get_multi_chip_mode() == 0) {
|
||||
ERROR("Chip Count is set to %u but multi-chip mode is not "
|
||||
"enabled\n", CSS_SGI_CHIP_COUNT);
|
||||
panic();
|
||||
} else {
|
||||
INFO("Enabling multi-chip support for RD-N2 variant\n");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) {
|
||||
ret = mmap_add_dynamic_region(
|
||||
rdn2mc_dynamic_mmap[i].base_pa,
|
||||
rdn2mc_dynamic_mmap[i].base_va,
|
||||
rdn2mc_dynamic_mmap[i].size,
|
||||
rdn2mc_dynamic_mmap[i].attr);
|
||||
if (ret != 0) {
|
||||
ERROR("Failed to add dynamic mmap entry for"
|
||||
" i: %d " "(ret=%d)\n", i, ret);
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
||||
plat_arm_override_gicr_frames(
|
||||
rdn2mc_multichip_gicr_frames);
|
||||
gic600_multichip_init(&rdn2mc_multichip_data);
|
||||
}
|
||||
#endif
|
||||
|
||||
sgi_bl31_common_platform_setup();
|
||||
}
|
||||
#endif /* IMAGE_BL31 */
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
static const arm_tzc_regions_info_t tzc_regions[] = {
|
||||
ARM_TZC_REGIONS_DEF,
|
||||
{}
|
||||
};
|
||||
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
|
||||
static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
|
||||
{
|
||||
/* TZC memory regions for second chip */
|
||||
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
|
||||
{}
|
||||
},
|
||||
#if CSS_SGI_CHIP_COUNT > 2
|
||||
{
|
||||
/* TZC memory regions for third chip */
|
||||
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
|
||||
{}
|
||||
},
|
||||
#endif
|
||||
#if CSS_SGI_CHIP_COUNT > 3
|
||||
{
|
||||
/* TZC memory regions for fourth chip */
|
||||
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
|
||||
{}
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */
|
||||
|
||||
/* Initialize the secure environment */
|
||||
void plat_arm_security_setup(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
INFO("Configuring TrustZone Controller for Chip 0\n");
|
||||
|
||||
for (i = 0; i < TZC400_COUNT; i++) {
|
||||
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
|
||||
}
|
||||
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
|
||||
unsigned int j;
|
||||
|
||||
for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
|
||||
INFO("Configuring TrustZone Controller for Chip %u\n", i);
|
||||
|
||||
for (j = 0; j < TZC400_COUNT; j++) {
|
||||
arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
|
||||
+ TZC400_BASE(j), tzc_regions_mc[i-1]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/arm/css/common/css_pm.h>
|
||||
|
||||
/******************************************************************************
|
||||
* The power domain tree descriptor.
|
||||
******************************************************************************/
|
||||
const unsigned char rd_n2_pd_tree_desc[] = {
|
||||
(PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
#if (CSS_SGI_PLATFORM_VARIANT != 2 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
#endif
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
#endif
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
CSS_SGI_MAX_CPUS_PER_CLUSTER,
|
||||
#endif
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return rd_n2_pd_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* The array mapping platform core position (implemented by plat_my_core_pos())
|
||||
* to the SCMI power domain ID implemented by SCP.
|
||||
******************************************************************************/
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 2)
|
||||
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
|
||||
#if (CSS_SGI_CHIP_COUNT > 1)
|
||||
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
|
||||
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
|
||||
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
|
||||
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
|
||||
#endif
|
||||
#if (CSS_SGI_CHIP_COUNT > 2)
|
||||
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
|
||||
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
|
||||
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
|
||||
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
|
||||
#endif
|
||||
#if (CSS_SGI_CHIP_COUNT > 3)
|
||||
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
|
||||
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
|
||||
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
|
||||
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
|
||||
#endif
|
||||
};
|
||||
#else
|
||||
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
|
||||
#if (CSS_SGI_PLATFORM_VARIANT == 0)
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
|
||||
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
Reference in New Issue
Block a user