GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak bl1_early_platform_setup
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#pragma weak bl1_plat_arch_setup
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#pragma weak bl1_plat_sec_mem_layout
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#pragma weak arm_bl1_early_platform_setup
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#pragma weak bl1_plat_prepare_exit
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#pragma weak bl1_plat_get_next_image_id
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#pragma weak plat_arm_bl1_fwu_needed
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#pragma weak arm_bl1_plat_arch_setup
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#pragma weak arm_bl1_platform_setup
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#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
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bl1_tzram_layout.total_base, \
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bl1_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | EL3_PAS)
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/*
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* If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
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* otherwise one region is defined containing both
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*/
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#if SEPARATE_CODE_AND_RODATA
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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MT_CODE | EL3_PAS), \
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MAP_REGION_FLAT( \
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BL1_RO_DATA_BASE, \
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BL1_RO_DATA_END \
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- BL_RO_DATA_BASE, \
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MT_RO_DATA | EL3_PAS)
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#else
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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MT_CODE | EL3_PAS)
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#endif
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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/* Boolean variable to hold condition whether firmware update needed or not */
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static bool is_fwu_needed;
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struct meminfo *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* BL1 specific platform actions shared between ARM standard platforms.
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******************************************************************************/
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void arm_bl1_early_platform_setup(void)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Enable watchdog */
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plat_arm_secure_wdt_start();
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#endif
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/* Initialize the console to provide early debug support */
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arm_console_boot_init();
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
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bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
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}
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void bl1_early_platform_setup(void)
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{
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arm_bl1_early_platform_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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plat_arm_interconnect_init();
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/*
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* Enable Interconnect coherency for the primary CPU's cluster.
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*/
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plat_arm_interconnect_enter_coherency();
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}
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/******************************************************************************
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* Perform the very early platform specific architecture setup shared between
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* ARM standard platforms. This only does basic initialization. Later
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* architectural setup (bl1_arch_setup()) does not do anything platform
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* specific.
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*****************************************************************************/
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void arm_bl1_plat_arch_setup(void)
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{
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#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
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/*
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* Ensure ARM platforms don't use coherent memory in BL1 unless
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* cryptocell integration is enabled.
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*/
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assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
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#endif
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const mmap_region_t bl_regions[] = {
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MAP_BL1_TOTAL,
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MAP_BL1_RO,
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#if USE_ROMLIB
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ARM_MAP_ROMLIB_CODE,
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ARM_MAP_ROMLIB_DATA,
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#endif
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#if ARM_CRYPTOCELL_INTEG
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ARM_MAP_BL_COHERENT_RAM,
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#endif
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{0}
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};
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setup_page_tables(bl_regions, plat_arm_get_mmap());
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#ifdef __aarch64__
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enable_mmu_el3(0);
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#else
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enable_mmu_svc_mon(0);
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#endif /* __aarch64__ */
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arm_setup_romlib();
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}
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void bl1_plat_arch_setup(void)
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{
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arm_bl1_plat_arch_setup();
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}
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/*
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* Perform the platform specific architecture setup shared between
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* ARM standard platforms.
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*/
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void arm_bl1_platform_setup(void)
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{
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const struct dyn_cfg_dtb_info_t *fw_config_info;
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image_desc_t *desc;
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uint32_t fw_config_max_size;
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int err = -1;
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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/* Check if we need FWU before further processing */
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is_fwu_needed = plat_arm_bl1_fwu_needed();
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if (is_fwu_needed) {
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ERROR("Skip platform setup as FWU detected\n");
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return;
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}
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/* Set global DTB info for fixed fw_config information */
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fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
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set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
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/* Fill the device tree information struct with the info from the config dtb */
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err = fconf_load_config(FW_CONFIG_ID);
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if (err < 0) {
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ERROR("Loading of FW_CONFIG failed %d\n", err);
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plat_error_handler(err);
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}
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/*
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* FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
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* is successful then load TB_FW_CONFIG device tree.
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*/
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fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
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if (fw_config_info != NULL) {
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err = fconf_populate_dtb_registry(fw_config_info->config_addr);
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if (err < 0) {
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ERROR("Parsing of FW_CONFIG failed %d\n", err);
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plat_error_handler(err);
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}
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/* load TB_FW_CONFIG */
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err = fconf_load_config(TB_FW_CONFIG_ID);
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if (err < 0) {
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ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
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plat_error_handler(err);
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}
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} else {
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ERROR("Invalid FW_CONFIG address\n");
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plat_error_handler(err);
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}
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/* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
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desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
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assert(desc != NULL);
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desc->ep_info.args.arg0 = fw_config_info->config_addr;
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#if CRYPTO_SUPPORT
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/* Share the Mbed TLS heap info with other images */
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arm_bl1_set_mbedtls_heap();
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#endif /* CRYPTO_SUPPORT */
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/*
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* Allow access to the System counter timer module and program
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* counter frequency for non secure images during FWU
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*/
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#ifdef ARM_SYS_TIMCTL_BASE
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arm_configure_sys_timer();
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#endif
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#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
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write_cntfrq_el0(plat_get_syscnt_freq2());
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#endif
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}
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void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Disable watchdog before leaving BL1 */
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plat_arm_secure_wdt_stop();
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#endif
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#ifdef EL3_PAYLOAD_BASE
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/*
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* Program the EL3 payload's entry point address into the CPUs mailbox
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* in order to release secondary CPUs from their holding pen and make
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* them jump there.
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*/
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plat_arm_program_trusted_mailbox(ep_info->pc);
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dsbsy();
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sev();
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#endif
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}
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/*
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* On Arm platforms, the FWU process is triggered when the FIP image has
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* been tampered with.
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*/
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bool plat_arm_bl1_fwu_needed(void)
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{
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return !arm_io_is_toc_valid();
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}
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/*******************************************************************************
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* The following function checks if Firmware update is needed,
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* by checking if TOC in FIP image is valid or not.
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******************************************************************************/
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unsigned int bl1_plat_get_next_image_id(void)
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{
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return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
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}
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