GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/partition/partition.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#if ENABLE_RME
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#include <lib/gpt_rme/gpt_rme.h>
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#endif /* ENABLE_RME */
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#ifdef SPD_opteed
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#include <lib/optee_utils.h>
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#endif
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#include <lib/utils.h>
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#if ENABLE_RME
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#include <plat/arm/common/arm_pas_def.h>
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#endif /* ENABLE_RME */
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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/* Base address of fw_config received from BL1 */
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static uintptr_t config_base;
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/*
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* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
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* for `meminfo_t` data structure and fw_configs passed from BL1.
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*/
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CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak bl2_early_platform_setup2
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#pragma weak bl2_platform_setup
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#pragma weak bl2_plat_arch_setup
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#pragma weak bl2_plat_sec_mem_layout
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#if ENABLE_RME
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#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
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bl2_tzram_layout.total_base, \
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bl2_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | MT_ROOT)
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#else
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#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
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bl2_tzram_layout.total_base, \
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bl2_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif /* ENABLE_RME */
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#pragma weak arm_bl2_plat_handle_post_image_load
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/*******************************************************************************
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* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
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* in x0. This memory layout is sitting at the base of the free trusted SRAM.
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* Copy it to a safe location before its reclaimed by later BL2 functionality.
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******************************************************************************/
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void arm_bl2_early_platform_setup(uintptr_t fw_config,
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struct meminfo *mem_layout)
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{
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/* Initialize the console to provide early debug support */
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arm_console_boot_init();
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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config_base = fw_config;
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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/* Load partition table */
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#if ARM_GPT_SUPPORT
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partition_init(GPT_IMAGE_ID);
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#endif /* ARM_GPT_SUPPORT */
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}
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void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
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{
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arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
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generic_delay_timer_init();
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}
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/*
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* Perform BL2 preload setup. Currently we initialise the dynamic
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* configuration here.
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*/
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void bl2_plat_preload_setup(void)
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{
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arm_bl2_dyn_cfg_init();
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#if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
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/* Always use the FIP from bank 0 */
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arm_set_fip_addr(0U);
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#endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */
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}
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/*
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* Perform ARM standard platform setup.
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*/
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void arm_bl2_platform_setup(void)
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{
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#if !ENABLE_RME
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/* Initialize the secure environment */
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plat_arm_security_setup();
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#endif
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#if defined(PLAT_ARM_MEM_PROT_ADDR)
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arm_nor_psci_do_static_mem_protect();
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#endif
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}
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void bl2_platform_setup(void)
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{
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arm_bl2_platform_setup();
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}
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#if ENABLE_RME
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static void arm_bl2_plat_gpt_setup(void)
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{
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/*
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* The GPT library might modify the gpt regions structure to optimize
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* the layout, so the array cannot be constant.
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*/
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pas_region_t pas_regions[] = {
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ARM_PAS_KERNEL,
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ARM_PAS_SECURE,
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ARM_PAS_REALM,
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ARM_PAS_EL3_DRAM,
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ARM_PAS_GPTS
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};
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/* Initialize entire protected space to GPT_GPI_ANY. */
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if (gpt_init_l0_tables(GPCCR_PPS_4GB, ARM_L0_GPT_ADDR_BASE,
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ARM_L0_GPT_SIZE) < 0) {
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ERROR("gpt_init_l0_tables() failed!\n");
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panic();
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}
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/* Carve out defined PAS ranges. */
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if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
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ARM_L1_GPT_ADDR_BASE,
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ARM_L1_GPT_SIZE,
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pas_regions,
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(unsigned int)(sizeof(pas_regions) /
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sizeof(pas_region_t))) < 0) {
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ERROR("gpt_init_pas_l1_tables() failed!\n");
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panic();
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}
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INFO("Enabling Granule Protection Checks\n");
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if (gpt_enable() < 0) {
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ERROR("gpt_enable() failed!\n");
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panic();
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}
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}
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#endif /* ENABLE_RME */
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here.
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* When RME is enabled the secure environment is initialised before
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* initialising and enabling Granule Protection.
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* This function initialises the MMU in a quick and dirty way.
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******************************************************************************/
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void arm_bl2_plat_arch_setup(void)
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{
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#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
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/*
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* Ensure ARM platforms don't use coherent memory in BL2 unless
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* cryptocell integration is enabled.
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*/
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assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
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#endif
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const mmap_region_t bl_regions[] = {
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MAP_BL2_TOTAL,
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ARM_MAP_BL_RO,
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#if USE_ROMLIB
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ARM_MAP_ROMLIB_CODE,
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ARM_MAP_ROMLIB_DATA,
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#endif
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#if ARM_CRYPTOCELL_INTEG
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ARM_MAP_BL_COHERENT_RAM,
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#endif
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ARM_MAP_BL_CONFIG_REGION,
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#if ENABLE_RME
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ARM_MAP_L0_GPT_REGION,
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#endif
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{0}
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};
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#if ENABLE_RME
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/* Initialise the secure environment */
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plat_arm_security_setup();
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#endif
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setup_page_tables(bl_regions, plat_arm_get_mmap());
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#ifdef __aarch64__
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#if ENABLE_RME
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/* BL2 runs in EL3 when RME enabled. */
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assert(get_armv9_2_feat_rme_support() != 0U);
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enable_mmu_el3(0);
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/* Initialise and enable granule protection after MMU. */
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arm_bl2_plat_gpt_setup();
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#else
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enable_mmu_el1(0);
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#endif
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#else
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enable_mmu_svc_mon(0);
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#endif
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arm_setup_romlib();
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}
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void bl2_plat_arch_setup(void)
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{
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const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
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arm_bl2_plat_arch_setup();
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/* Fill the properties struct with the info from the config dtb */
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fconf_populate("FW_CONFIG", config_base);
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/* TB_FW_CONFIG was also loaded by BL1 */
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tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
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assert(tb_fw_config_info != NULL);
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fconf_populate("TB_FW", tb_fw_config_info->config_addr);
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}
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int arm_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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#ifdef SPD_opteed
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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#endif
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assert(bl_mem_params != NULL);
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switch (image_id) {
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#ifdef __aarch64__
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case BL32_IMAGE_ID:
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#ifdef SPD_opteed
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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#endif
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bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
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break;
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#endif
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
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break;
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#ifdef SCP_BL2_BASE
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case SCP_BL2_IMAGE_ID:
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/* The subsequent handling of SCP_BL2 is platform specific */
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err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
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if (err) {
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WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
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}
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break;
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#endif
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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#if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD
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/* For Secure Partitions we don't need post processing */
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if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
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(image_id < MAX_NUMBER_IDS)) {
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return 0;
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}
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#endif
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return arm_bl2_handle_post_image_load(image_id);
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return arm_bl2_plat_handle_post_image_load(image_id);
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}
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