GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HI6220_H
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#define HI6220_H
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#include <hi6220_regs_acpu.h>
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#include <hi6220_regs_ao.h>
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#include <hi6220_regs_peri.h>
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#include <hi6220_regs_pin.h>
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#include <hi6220_regs_pmctrl.h>
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/*******************************************************************************
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* Implementation defined ACTLR_EL2 bit definitions
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******************************************************************************/
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#define ACTLR_EL2_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL2_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL2_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL2_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL2_CPUACTLR_BIT (1 << 0)
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define CCI400_BASE 0xF6E90000
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#define CCI400_SL_IFACE3_CLUSTER_IX 3
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#define CCI400_SL_IFACE4_CLUSTER_IX 4
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#define DWMMC0_BASE 0xF723D000
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#define DWUSB_BASE 0xF72C0000
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#define EDMAC_BASE 0xf7370000
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#define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694)
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#define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6))
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#define EDMAC_SEC_CTRL_INTR_SEC (1 << 1)
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#define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0)
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#define EDMAC_CHANNEL_NUMS 16
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#define PMUSSI_BASE 0xF8000000
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#define SP804_TIMER0_BASE 0xF8008000
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#define GPIO0_BASE 0xF8011000
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#define GPIO1_BASE 0xF8012000
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#define GPIO2_BASE 0xF8013000
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#define GPIO3_BASE 0xF8014000
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#define GPIO4_BASE 0xF7020000
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#define GPIO5_BASE 0xF7021000
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#define GPIO6_BASE 0xF7022000
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#define GPIO7_BASE 0xF7023000
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#define GPIO8_BASE 0xF7024000
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#define GPIO9_BASE 0xF7025000
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#define GPIO10_BASE 0xF7026000
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#define GPIO11_BASE 0xF7027000
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#define GPIO12_BASE 0xF7028000
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#define GPIO13_BASE 0xF7029000
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#define GPIO14_BASE 0xF702A000
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#define GPIO15_BASE 0xF702B000
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#define GPIO16_BASE 0xF702C000
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#define GPIO17_BASE 0xF702D000
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#define GPIO18_BASE 0xF702E000
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#define GPIO19_BASE 0xF702F000
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#endif /* HI6220_H */
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+300
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HI6220_REGS_ACPU_H
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#define HI6220_REGS_ACPU_H
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#define ACPU_CTRL_BASE 0xF6504000
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#define ACPU_SC_CPU_CTRL (ACPU_CTRL_BASE + 0x000)
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#define ACPU_SC_CPU_STAT (ACPU_CTRL_BASE + 0x008)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2 (1 << 0)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2_SHIFT (0)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI0 (1 << 1)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI0_SHIFT (1)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI1 (1 << 2)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI1_SHIFT (2)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI2 (1 << 3)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI2_SHIFT (3)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI3 (1 << 4)
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#define ACPU_SC_CPU_STAT_SC_STANDBYWFI3_SHIFT (4)
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#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2 (1 << 8)
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#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2_SHIFT (8)
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#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI (1 << 9)
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#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI_SHIFT (9)
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#define ACPU_SC_CPU_STAT_L2FLSHUDONE0 (1 << 16)
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#define ACPU_SC_CPU_STAT_L2FLSHUDONE0_SHIFT (16)
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#define ACPU_SC_CPU_STAT_L2FLSHUDONE1 (1 << 17)
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#define ACPU_SC_CPU_STAT_L2FLSHUDONE1_SHIFT (17)
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#define ACPU_SC_CPU_STAT_CCI400_ACTIVE (1 << 18)
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#define ACPU_SC_CPU_STAT_CCI400_ACTIVE_SHIFT (18)
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#define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD (1 << 20)
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#define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD_SHIFT (20)
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#define ACPU_SC_CLKEN (ACPU_CTRL_BASE + 0x00c)
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#define HPM_L2_1_CLKEN (1 << 9)
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#define G_CPU_1_CLKEN (1 << 8)
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#define HPM_L2_CLKEN (1 << 1)
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#define G_CPU_CLKEN (1 << 0)
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#define ACPU_SC_CLKDIS (ACPU_CTRL_BASE + 0x010)
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#define ACPU_SC_CLK_STAT (ACPU_CTRL_BASE + 0x014)
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#define ACPU_SC_RSTEN (ACPU_CTRL_BASE + 0x018)
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#define SRST_PRESET1_RSTEN (1 << 11)
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#define SRST_PRESET0_RSTEN (1 << 10)
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#define SRST_CLUSTER1_RSTEN (1 << 9)
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#define SRST_CLUSTER0_RSTEN (1 << 8)
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#define SRST_L2_HPM_1_RSTEN (1 << 5)
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#define SRST_AARM_L2_1_RSTEN (1 << 4)
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#define SRST_L2_HPM_0_RSTEN (1 << 3)
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#define SRST_AARM_L2_0_RSTEN (1 << 1)
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#define SRST_CLUSTER1 (SRST_PRESET1_RSTEN | \
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SRST_CLUSTER1_RSTEN | \
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SRST_L2_HPM_1_RSTEN | \
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SRST_AARM_L2_1_RSTEN)
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#define SRST_CLUSTER0 (SRST_PRESET0_RSTEN | \
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SRST_CLUSTER0_RSTEN | \
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SRST_L2_HPM_0_RSTEN | \
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SRST_AARM_L2_0_RSTEN)
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#define ACPU_SC_RSTDIS (ACPU_CTRL_BASE + 0x01c)
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#define ACPU_SC_RST_STAT (ACPU_CTRL_BASE + 0x020)
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#define ACPU_SC_PDBGUP_MBIST (ACPU_CTRL_BASE + 0x02c)
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#define PDBGUP_CLUSTER1_SHIFT 8
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#define ACPU_SC_VD_CTRL (ACPU_CTRL_BASE + 0x054)
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#define ACPU_SC_VD_MASK_PATTERN_CTRL (ACPU_CTRL_BASE + 0x058)
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#define ACPU_SC_VD_MASK_PATTERN_VAL (0xCCB << 12)
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#define ACPU_SC_VD_MASK_PATTERN_MASK ((0x1 << 13) - 1)
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#define ACPU_SC_VD_DLY_FIXED_CTRL (ACPU_CTRL_BASE + 0x05c)
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#define ACPU_SC_VD_DLY_TABLE0_CTRL (ACPU_CTRL_BASE + 0x060)
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#define ACPU_SC_VD_DLY_TABLE1_CTRL (ACPU_CTRL_BASE + 0x064)
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#define ACPU_SC_VD_DLY_TABLE2_CTRL (ACPU_CTRL_BASE + 0x068)
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#define ACPU_SC_VD_HPM_CTRL (ACPU_CTRL_BASE + 0x06c)
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#define ACPU_SC_A53_CLUSTER_MTCMOS_EN (ACPU_CTRL_BASE + 0x088)
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#define PW_MTCMOS_EN_A53_1_EN (1 << 1)
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#define PW_MTCMOS_EN_A53_0_EN (1 << 0)
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#define ACPU_SC_A53_CLUSTER_MTCMOS_STA (ACPU_CTRL_BASE + 0x090)
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#define ACPU_SC_A53_CLUSTER_ISO_EN (ACPU_CTRL_BASE + 0x098)
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#define PW_ISO_A53_1_EN (1 << 1)
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#define PW_ISO_A53_0_EN (1 << 0)
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#define ACPU_SC_A53_CLUSTER_ISO_DIS (ACPU_CTRL_BASE + 0x09c)
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#define ACPU_SC_A53_CLUSTER_ISO_STA (ACPU_CTRL_BASE + 0x0a0)
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#define ACPU_SC_A53_1_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0b4)
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#define ACPU_SC_A53_0_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0bc)
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#define ACPU_SC_A53_x_MTCMOS_TIMER(x) ((x) ? ACPU_SC_A53_1_MTCMOS_TIMER : ACPU_SC_A53_0_MTCMOS_TIMER)
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#define ACPU_SC_SNOOP_PWD (ACPU_CTRL_BASE + 0xe4)
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#define PD_DETECT_START1 (1 << 16)
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#define PD_DETECT_START0 (1 << 0)
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#define ACPU_SC_CPU0_CTRL (ACPU_CTRL_BASE + 0x100)
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#define CPU_CTRL_AARCH64_MODE (1 << 7)
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#define ACPU_SC_CPU0_STAT (ACPU_CTRL_BASE + 0x104)
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#define ACPU_SC_CPU0_CLKEN (ACPU_CTRL_BASE + 0x108)
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#define CPU_CLKEN_HPM (1 << 1)
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#define ACPU_SC_CPU0_CLK_STAT (ACPU_CTRL_BASE + 0x110)
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#define ACPU_SC_CPU0_RSTEN (ACPU_CTRL_BASE + 0x114)
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#define ACPU_SC_CPU0_RSTDIS (ACPU_CTRL_BASE + 0x118)
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#define ACPU_SC_CPU0_MTCMOS_EN (ACPU_CTRL_BASE + 0x120)
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#define CPU_MTCMOS_PW (1 << 0)
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#define ACPU_SC_CPU0_PW_ISOEN (ACPU_CTRL_BASE + 0x130)
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#define CPU_PW_ISO (1 << 0)
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#define ACPU_SC_CPU0_PW_ISODIS (ACPU_CTRL_BASE + 0x134)
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#define ACPU_SC_CPU0_PW_ISO_STAT (ACPU_CTRL_BASE + 0x138)
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#define ACPU_SC_CPU0_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x154)
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#define CPU_MTCMOS_TIMER_STA (1 << 0)
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#define ACPU_SC_CPU0_RVBARADDR (ACPU_CTRL_BASE + 0x158)
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#define ACPU_SC_CPU1_CTRL (ACPU_CTRL_BASE + 0x200)
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#define ACPU_SC_CPU1_STAT (ACPU_CTRL_BASE + 0x204)
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#define ACPU_SC_CPU1_CLKEN (ACPU_CTRL_BASE + 0x208)
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#define ACPU_SC_CPU1_CLK_STAT (ACPU_CTRL_BASE + 0x210)
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#define ACPU_SC_CPU1_RSTEN (ACPU_CTRL_BASE + 0x214)
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#define ACPU_SC_CPU1_RSTDIS (ACPU_CTRL_BASE + 0x218)
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#define ACPU_SC_CPU1_MTCMOS_EN (ACPU_CTRL_BASE + 0x220)
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#define ACPU_SC_CPU1_PW_ISODIS (ACPU_CTRL_BASE + 0x234)
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#define ACPU_SC_CPU1_PW_ISO_STAT (ACPU_CTRL_BASE + 0x238)
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#define ACPU_SC_CPU1_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x254)
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#define ACPU_SC_CPU1_RVBARADDR (ACPU_CTRL_BASE + 0x258)
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#define ACPU_SC_CPU2_CTRL (ACPU_CTRL_BASE + 0x300)
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#define ACPU_SC_CPU2_STAT (ACPU_CTRL_BASE + 0x304)
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#define ACPU_SC_CPU2_CLKEN (ACPU_CTRL_BASE + 0x308)
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#define ACPU_SC_CPU2_CLK_STAT (ACPU_CTRL_BASE + 0x310)
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#define ACPU_SC_CPU2_RSTEN (ACPU_CTRL_BASE + 0x314)
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#define ACPU_SC_CPU2_RSTDIS (ACPU_CTRL_BASE + 0x318)
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#define ACPU_SC_CPU2_MTCMOS_EN (ACPU_CTRL_BASE + 0x320)
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#define ACPU_SC_CPU2_PW_ISODIS (ACPU_CTRL_BASE + 0x334)
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#define ACPU_SC_CPU2_PW_ISO_STAT (ACPU_CTRL_BASE + 0x338)
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#define ACPU_SC_CPU2_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x354)
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#define ACPU_SC_CPU2_RVBARADDR (ACPU_CTRL_BASE + 0x358)
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#define ACPU_SC_CPU3_CTRL (ACPU_CTRL_BASE + 0x400)
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#define ACPU_SC_CPU3_STAT (ACPU_CTRL_BASE + 0x404)
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#define ACPU_SC_CPU3_CLKEN (ACPU_CTRL_BASE + 0x408)
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#define ACPU_SC_CPU3_CLK_STAT (ACPU_CTRL_BASE + 0x410)
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#define ACPU_SC_CPU3_RSTEN (ACPU_CTRL_BASE + 0x414)
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#define ACPU_SC_CPU3_RSTDIS (ACPU_CTRL_BASE + 0x418)
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#define ACPU_SC_CPU3_MTCMOS_EN (ACPU_CTRL_BASE + 0x420)
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#define ACPU_SC_CPU3_PW_ISODIS (ACPU_CTRL_BASE + 0x434)
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#define ACPU_SC_CPU3_PW_ISO_STAT (ACPU_CTRL_BASE + 0x438)
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#define ACPU_SC_CPU3_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x454)
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#define ACPU_SC_CPU3_RVBARADDR (ACPU_CTRL_BASE + 0x458)
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#define ACPU_SC_CPU4_CTRL (ACPU_CTRL_BASE + 0x500)
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#define ACPU_SC_CPU4_STAT (ACPU_CTRL_BASE + 0x504)
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#define ACPU_SC_CPU4_CLKEN (ACPU_CTRL_BASE + 0x508)
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#define ACPU_SC_CPU4_CLK_STAT (ACPU_CTRL_BASE + 0x510)
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#define ACPU_SC_CPU4_RSTEN (ACPU_CTRL_BASE + 0x514)
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#define ACPU_SC_CPU4_RSTDIS (ACPU_CTRL_BASE + 0x518)
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#define ACPU_SC_CPU4_MTCMOS_EN (ACPU_CTRL_BASE + 0x520)
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#define ACPU_SC_CPU4_PW_ISODIS (ACPU_CTRL_BASE + 0x534)
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#define ACPU_SC_CPU4_PW_ISO_STAT (ACPU_CTRL_BASE + 0x538)
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#define ACPU_SC_CPU4_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x554)
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#define ACPU_SC_CPU4_RVBARADDR (ACPU_CTRL_BASE + 0x558)
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#define ACPU_SC_CPU5_CTRL (ACPU_CTRL_BASE + 0x600)
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#define ACPU_SC_CPU5_STAT (ACPU_CTRL_BASE + 0x604)
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#define ACPU_SC_CPU5_CLKEN (ACPU_CTRL_BASE + 0x608)
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#define ACPU_SC_CPU5_CLK_STAT (ACPU_CTRL_BASE + 0x610)
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#define ACPU_SC_CPU5_RSTEN (ACPU_CTRL_BASE + 0x614)
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#define ACPU_SC_CPU5_RSTDIS (ACPU_CTRL_BASE + 0x618)
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#define ACPU_SC_CPU5_MTCMOS_EN (ACPU_CTRL_BASE + 0x620)
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#define ACPU_SC_CPU5_PW_ISODIS (ACPU_CTRL_BASE + 0x634)
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#define ACPU_SC_CPU5_PW_ISO_STAT (ACPU_CTRL_BASE + 0x638)
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#define ACPU_SC_CPU5_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x654)
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#define ACPU_SC_CPU5_RVBARADDR (ACPU_CTRL_BASE + 0x658)
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#define ACPU_SC_CPU6_CTRL (ACPU_CTRL_BASE + 0x700)
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#define ACPU_SC_CPU6_STAT (ACPU_CTRL_BASE + 0x704)
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#define ACPU_SC_CPU6_CLKEN (ACPU_CTRL_BASE + 0x708)
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#define ACPU_SC_CPU6_CLK_STAT (ACPU_CTRL_BASE + 0x710)
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#define ACPU_SC_CPU6_RSTEN (ACPU_CTRL_BASE + 0x714)
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#define ACPU_SC_CPU6_RSTDIS (ACPU_CTRL_BASE + 0x718)
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#define ACPU_SC_CPU6_MTCMOS_EN (ACPU_CTRL_BASE + 0x720)
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#define ACPU_SC_CPU6_PW_ISODIS (ACPU_CTRL_BASE + 0x734)
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#define ACPU_SC_CPU6_PW_ISO_STAT (ACPU_CTRL_BASE + 0x738)
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#define ACPU_SC_CPU6_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x754)
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#define ACPU_SC_CPU6_RVBARADDR (ACPU_CTRL_BASE + 0x758)
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#define ACPU_SC_CPU7_CTRL (ACPU_CTRL_BASE + 0x800)
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#define ACPU_SC_CPU7_STAT (ACPU_CTRL_BASE + 0x804)
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#define ACPU_SC_CPU7_CLKEN (ACPU_CTRL_BASE + 0x808)
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#define ACPU_SC_CPU7_CLK_STAT (ACPU_CTRL_BASE + 0x810)
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#define ACPU_SC_CPU7_RSTEN (ACPU_CTRL_BASE + 0x814)
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#define ACPU_SC_CPU7_RSTDIS (ACPU_CTRL_BASE + 0x818)
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#define ACPU_SC_CPU7_MTCMOS_EN (ACPU_CTRL_BASE + 0x820)
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#define ACPU_SC_CPU7_PW_ISODIS (ACPU_CTRL_BASE + 0x834)
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#define ACPU_SC_CPU7_PW_ISO_STAT (ACPU_CTRL_BASE + 0x838)
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#define ACPU_SC_CPU7_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x854)
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#define ACPU_SC_CPU7_RVBARADDR (ACPU_CTRL_BASE + 0x858)
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#define ACPU_SC_CPUx_CTRL(x) ((x < 8) ? (ACPU_SC_CPU0_CTRL + 0x100 * x) : ACPU_SC_CPU0_CTRL)
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#define ACPU_SC_CPUx_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_STAT + 0x100 * x) : ACPU_SC_CPU0_STAT)
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#define ACPU_SC_CPUx_CLKEN(x) ((x < 8) ? (ACPU_SC_CPU0_CLKEN + 0x100 * x) : ACPU_SC_CPU0_CLKEN)
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#define ACPU_SC_CPUx_CLK_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_CLK_STAT + 0x100 * x) : ACPU_SC_CPU0_CLK_STAT)
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#define ACPU_SC_CPUx_RSTEN(x) ((x < 8) ? (ACPU_SC_CPU0_RSTEN + 0x100 * x) : ACPU_SC_CPU0_RSTEN)
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#define ACPU_SC_CPUx_RSTDIS(x) ((x < 8) ? (ACPU_SC_CPU0_RSTDIS + 0x100 * x) : ACPU_SC_CPU0_RSTDIS)
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#define ACPU_SC_CPUx_MTCMOS_EN(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_EN + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_EN)
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#define ACPU_SC_CPUx_PW_ISODIS(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISODIS + 0x100 * x) : ACPU_SC_CPU0_PW_ISODIS)
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#define ACPU_SC_CPUx_PW_ISO_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISO_STAT + 0x100 * x) : ACPU_SC_CPU0_PW_ISO_STAT)
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#define ACPU_SC_CPUx_MTCMOS_TIMER_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_TIMER_STAT + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_TIMER_STAT)
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#define ACPU_SC_CPUx_RVBARADDR(x) ((x < 8) ? (ACPU_SC_CPU0_RVBARADDR + 0x100 * x) : ACPU_SC_CPU0_RVBARADDR)
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#define ACPU_SC_CPU_STAT_CLKDIV_VD_MASK (3 << 20)
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#define ACPU_SC_VD_CTRL_TUNE_EN_DIF (1 << 0)
|
||||
#define ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT (0)
|
||||
#define ACPU_SC_VD_CTRL_TUNE (1 << 1)
|
||||
#define ACPU_SC_VD_CTRL_TUNE_SHIFT (1)
|
||||
#define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF (1 << 7)
|
||||
#define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT (7)
|
||||
#define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI (1 << 8)
|
||||
#define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT (8)
|
||||
#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR (1 << 9)
|
||||
#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR_SHIFT (9)
|
||||
#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN (1 << 10)
|
||||
#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT (10)
|
||||
#define ACPU_SC_VD_CTRL_TUNE_EN_INT (1 << 11)
|
||||
#define ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT (11)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE0 (1 << 12)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE0_MASK (0xf << 12)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT (12)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE1 (1 << 16)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE1_MASK (0xf << 16)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT (16)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE2 (1 << 20)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE2_MASK (0xf << 20)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT (20)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE3 (1 << 24)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE3_MASK (0xf << 24)
|
||||
#define ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT (24)
|
||||
#define ACPU_SC_VD_CTRL_FORCE_CLK_EN (1 << 28)
|
||||
#define ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT (28)
|
||||
#define ACPU_SC_VD_CTRL_DIV_EN_DIF (1 << 29)
|
||||
#define ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT (29)
|
||||
|
||||
#define ACPU_SC_VD_SHIFT_TABLE_TUNE_VAL \
|
||||
((0x1 << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \
|
||||
(0x3 << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \
|
||||
(0x5 << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \
|
||||
(0x6 << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \
|
||||
(0x7 << ACPU_SC_VD_CTRL_TUNE_SHIFT))
|
||||
|
||||
#define ACPU_SC_VD_SHIFT_TABLE_TUNE_MASK \
|
||||
((0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \
|
||||
(0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \
|
||||
(0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \
|
||||
(0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \
|
||||
(0x3F << ACPU_SC_VD_CTRL_TUNE_SHIFT))
|
||||
|
||||
#define ACPU_SC_VD_HPM_CTRL_OSC_DIV (1 << 0)
|
||||
#define ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT (0)
|
||||
#define ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK (0x000000FF)
|
||||
#define ACPU_SC_VD_HPM_CTRL_DLY_EXP (1 << 8)
|
||||
#define ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT (8)
|
||||
#define ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK (0x001FFF00)
|
||||
|
||||
#define HPM_OSC_DIV_VAL \
|
||||
(0x56 << ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT)
|
||||
#define HPM_OSC_DIV_MASK \
|
||||
(ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK)
|
||||
|
||||
#define HPM_DLY_EXP_VAL \
|
||||
(0xC7A << ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT)
|
||||
#define HPM_DLY_EXP_MASK \
|
||||
(ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK)
|
||||
|
||||
#define ACPU_SC_VD_EN_ASIC_VAL \
|
||||
((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \
|
||||
(0X0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \
|
||||
(0X0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT))
|
||||
|
||||
#define ACPU_SC_VD_EN_SFT_VAL \
|
||||
((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \
|
||||
(0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT))
|
||||
|
||||
#define ACPU_SC_VD_EN_MASK \
|
||||
((0x1 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \
|
||||
(0x1 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \
|
||||
(0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \
|
||||
(0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \
|
||||
(0x1 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \
|
||||
(0x1 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \
|
||||
(0x1 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT))
|
||||
|
||||
#endif /* HI6220_REGS_ACPU_H */
|
||||
+334
@@ -0,0 +1,334 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HI6220_REGS_AO_H
|
||||
#define HI6220_REGS_AO_H
|
||||
|
||||
#define AO_CTRL_BASE 0xF7800000
|
||||
|
||||
#define AO_SC_SYS_CTRL0 (AO_CTRL_BASE + 0x000)
|
||||
#define AO_SC_SYS_CTRL1 (AO_CTRL_BASE + 0x004)
|
||||
#define AO_SC_SYS_CTRL2 (AO_CTRL_BASE + 0x008)
|
||||
#define AO_SC_SYS_STAT0 (AO_CTRL_BASE + 0x010)
|
||||
#define AO_SC_SYS_STAT1 (AO_CTRL_BASE + 0x014)
|
||||
#define AO_SC_MCU_IMCTRL (AO_CTRL_BASE + 0x018)
|
||||
#define AO_SC_MCU_IMSTAT (AO_CTRL_BASE + 0x01C)
|
||||
#define AO_SC_SECONDRY_INT_EN0 (AO_CTRL_BASE + 0x044)
|
||||
#define AO_SC_SECONDRY_INT_STATR0 (AO_CTRL_BASE + 0x048)
|
||||
#define AO_SC_SECONDRY_INT_STATM0 (AO_CTRL_BASE + 0x04C)
|
||||
#define AO_SC_MCU_WKUP_INT_EN6 (AO_CTRL_BASE + 0x054)
|
||||
#define AO_SC_MCU_WKUP_INT_STATR6 (AO_CTRL_BASE + 0x058)
|
||||
#define AO_SC_MCU_WKUP_INT_STATM6 (AO_CTRL_BASE + 0x05C)
|
||||
#define AO_SC_MCU_WKUP_INT_EN5 (AO_CTRL_BASE + 0x064)
|
||||
#define AO_SC_MCU_WKUP_INT_STATR5 (AO_CTRL_BASE + 0x068)
|
||||
#define AO_SC_MCU_WKUP_INT_STATM5 (AO_CTRL_BASE + 0x06C)
|
||||
#define AO_SC_MCU_WKUP_INT_EN4 (AO_CTRL_BASE + 0x094)
|
||||
#define AO_SC_MCU_WKUP_INT_STATR4 (AO_CTRL_BASE + 0x098)
|
||||
#define AO_SC_MCU_WKUP_INT_STATM4 (AO_CTRL_BASE + 0x09C)
|
||||
#define AO_SC_MCU_WKUP_INT_EN0 (AO_CTRL_BASE + 0x0A8)
|
||||
#define AO_SC_MCU_WKUP_INT_STATR0 (AO_CTRL_BASE + 0x0AC)
|
||||
#define AO_SC_MCU_WKUP_INT_STATM0 (AO_CTRL_BASE + 0x0B0)
|
||||
#define AO_SC_MCU_WKUP_INT_EN1 (AO_CTRL_BASE + 0x0B4)
|
||||
#define AO_SC_MCU_WKUP_INT_STATR1 (AO_CTRL_BASE + 0x0B8)
|
||||
#define AO_SC_MCU_WKUP_INT_STATM1 (AO_CTRL_BASE + 0x0BC)
|
||||
#define AO_SC_INT_STATR (AO_CTRL_BASE + 0x0C4)
|
||||
#define AO_SC_INT_STATM (AO_CTRL_BASE + 0x0C8)
|
||||
#define AO_SC_INT_CLEAR (AO_CTRL_BASE + 0x0CC)
|
||||
#define AO_SC_INT_EN_SET (AO_CTRL_BASE + 0x0D0)
|
||||
#define AO_SC_INT_EN_DIS (AO_CTRL_BASE + 0x0D4)
|
||||
#define AO_SC_INT_EN_STAT (AO_CTRL_BASE + 0x0D8)
|
||||
#define AO_SC_INT_STATR1 (AO_CTRL_BASE + 0x0E4)
|
||||
#define AO_SC_INT_STATM1 (AO_CTRL_BASE + 0x0E8)
|
||||
#define AO_SC_INT_CLEAR1 (AO_CTRL_BASE + 0x0EC)
|
||||
#define AO_SC_INT_EN_SET1 (AO_CTRL_BASE + 0x0F0)
|
||||
#define AO_SC_INT_EN_DIS1 (AO_CTRL_BASE + 0x0F4)
|
||||
#define AO_SC_INT_EN_STAT1 (AO_CTRL_BASE + 0x0F8)
|
||||
#define AO_SC_TIMER_EN0 (AO_CTRL_BASE + 0x1D0)
|
||||
#define AO_SC_TIMER_EN1 (AO_CTRL_BASE + 0x1D4)
|
||||
#define AO_SC_TIMER_EN4 (AO_CTRL_BASE + 0x1F0)
|
||||
#define AO_SC_TIMER_EN5 (AO_CTRL_BASE + 0x1F4)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL0 (AO_CTRL_BASE + 0x400)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL1 (AO_CTRL_BASE + 0x404)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL2 (AO_CTRL_BASE + 0x408)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3 (AO_CTRL_BASE + 0x40C)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL4 (AO_CTRL_BASE + 0x410)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL5 (AO_CTRL_BASE + 0x414)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL6 (AO_CTRL_BASE + 0x418)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL7 (AO_CTRL_BASE + 0x41C)
|
||||
#define AO_SC_MCU_SUBSYS_STAT0 (AO_CTRL_BASE + 0x440)
|
||||
#define AO_SC_MCU_SUBSYS_STAT1 (AO_CTRL_BASE + 0x444)
|
||||
#define AO_SC_MCU_SUBSYS_STAT2 (AO_CTRL_BASE + 0x448)
|
||||
#define AO_SC_MCU_SUBSYS_STAT3 (AO_CTRL_BASE + 0x44C)
|
||||
#define AO_SC_MCU_SUBSYS_STAT4 (AO_CTRL_BASE + 0x450)
|
||||
#define AO_SC_MCU_SUBSYS_STAT5 (AO_CTRL_BASE + 0x454)
|
||||
#define AO_SC_MCU_SUBSYS_STAT6 (AO_CTRL_BASE + 0x458)
|
||||
#define AO_SC_MCU_SUBSYS_STAT7 (AO_CTRL_BASE + 0x45C)
|
||||
#define AO_SC_PERIPH_CLKEN4 (AO_CTRL_BASE + 0x630)
|
||||
#define AO_SC_PERIPH_CLKDIS4 (AO_CTRL_BASE + 0x634)
|
||||
#define AO_SC_PERIPH_CLKSTAT4 (AO_CTRL_BASE + 0x638)
|
||||
#define AO_SC_PERIPH_CLKEN5 (AO_CTRL_BASE + 0x63C)
|
||||
#define AO_SC_PERIPH_CLKDIS5 (AO_CTRL_BASE + 0x640)
|
||||
#define AO_SC_PERIPH_CLKSTAT5 (AO_CTRL_BASE + 0x644)
|
||||
#define AO_SC_PERIPH_RSTEN4 (AO_CTRL_BASE + 0x6F0)
|
||||
#define AO_SC_PERIPH_RSTDIS4 (AO_CTRL_BASE + 0x6F4)
|
||||
#define AO_SC_PERIPH_RSTSTAT4 (AO_CTRL_BASE + 0x6F8)
|
||||
#define AO_SC_PERIPH_RSTEN5 (AO_CTRL_BASE + 0x6FC)
|
||||
#define AO_SC_PERIPH_RSTDIS5 (AO_CTRL_BASE + 0x700)
|
||||
#define AO_SC_PERIPH_RSTSTAT5 (AO_CTRL_BASE + 0x704)
|
||||
#define AO_SC_PW_CLKEN0 (AO_CTRL_BASE + 0x800)
|
||||
#define AO_SC_PW_CLKDIS0 (AO_CTRL_BASE + 0x804)
|
||||
#define AO_SC_PW_CLK_STAT0 (AO_CTRL_BASE + 0x808)
|
||||
#define AO_SC_PW_RSTEN0 (AO_CTRL_BASE + 0x810)
|
||||
#define AO_SC_PW_RSTDIS0 (AO_CTRL_BASE + 0x814)
|
||||
#define AO_SC_PW_RST_STAT0 (AO_CTRL_BASE + 0x818)
|
||||
#define AO_SC_PW_ISOEN0 (AO_CTRL_BASE + 0x820)
|
||||
#define AO_SC_PW_ISODIS0 (AO_CTRL_BASE + 0x824)
|
||||
#define AO_SC_PW_ISO_STAT0 (AO_CTRL_BASE + 0x828)
|
||||
#define AO_SC_PW_MTCMOS_EN0 (AO_CTRL_BASE + 0x830)
|
||||
#define AO_SC_PW_MTCMOS_DIS0 (AO_CTRL_BASE + 0x834)
|
||||
#define AO_SC_PW_MTCMOS_STAT0 (AO_CTRL_BASE + 0x838)
|
||||
#define AO_SC_PW_MTCMOS_ACK_STAT0 (AO_CTRL_BASE + 0x83C)
|
||||
#define AO_SC_PW_MTCMOS_TIMEOUT_STAT0 (AO_CTRL_BASE + 0x840)
|
||||
#define AO_SC_PW_STAT0 (AO_CTRL_BASE + 0x850)
|
||||
#define AO_SC_PW_STAT1 (AO_CTRL_BASE + 0x854)
|
||||
#define AO_SC_SYSTEST_STAT (AO_CTRL_BASE + 0x880)
|
||||
#define AO_SC_SYSTEST_SLICER_CNT0 (AO_CTRL_BASE + 0x890)
|
||||
#define AO_SC_SYSTEST_SLICER_CNT1 (AO_CTRL_BASE + 0x894)
|
||||
#define AO_SC_PW_CTRL1 (AO_CTRL_BASE + 0x8C8)
|
||||
#define AO_SC_PW_CTRL (AO_CTRL_BASE + 0x8CC)
|
||||
#define AO_SC_MCPU_VOTEEN (AO_CTRL_BASE + 0x8D0)
|
||||
#define AO_SC_MCPU_VOTEDIS (AO_CTRL_BASE + 0x8D4)
|
||||
#define AO_SC_MCPU_VOTESTAT (AO_CTRL_BASE + 0x8D8)
|
||||
#define AO_SC_MCPU_VOTE_MSK0 (AO_CTRL_BASE + 0x8E0)
|
||||
#define AO_SC_MCPU_VOTE_MSK1 (AO_CTRL_BASE + 0x8E4)
|
||||
#define AO_SC_MCPU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x8E8)
|
||||
#define AO_SC_MCPU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x8EC)
|
||||
#define AO_SC_PERI_VOTEEN (AO_CTRL_BASE + 0x8F0)
|
||||
#define AO_SC_PERI_VOTEDIS (AO_CTRL_BASE + 0x8F4)
|
||||
#define AO_SC_PERI_VOTESTAT (AO_CTRL_BASE + 0x8F8)
|
||||
#define AO_SC_PERI_VOTE_MSK0 (AO_CTRL_BASE + 0x900)
|
||||
#define AO_SC_PERI_VOTE_MSK1 (AO_CTRL_BASE + 0x904)
|
||||
#define AO_SC_PERI_VOTESTAT0_MSK (AO_CTRL_BASE + 0x908)
|
||||
#define AO_SC_PERI_VOTESTAT1_MSK (AO_CTRL_BASE + 0x90C)
|
||||
#define AO_SC_ACPU_VOTEEN (AO_CTRL_BASE + 0x910)
|
||||
#define AO_SC_ACPU_VOTEDIS (AO_CTRL_BASE + 0x914)
|
||||
#define AO_SC_ACPU_VOTESTAT (AO_CTRL_BASE + 0x918)
|
||||
#define AO_SC_ACPU_VOTE_MSK0 (AO_CTRL_BASE + 0x920)
|
||||
#define AO_SC_ACPU_VOTE_MSK1 (AO_CTRL_BASE + 0x924)
|
||||
#define AO_SC_ACPU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x928)
|
||||
#define AO_SC_ACPU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x92C)
|
||||
#define AO_SC_MCU_VOTEEN (AO_CTRL_BASE + 0x930)
|
||||
#define AO_SC_MCU_VOTEDIS (AO_CTRL_BASE + 0x934)
|
||||
#define AO_SC_MCU_VOTESTAT (AO_CTRL_BASE + 0x938)
|
||||
#define AO_SC_MCU_VOTE_MSK0 (AO_CTRL_BASE + 0x940)
|
||||
#define AO_SC_MCU_VOTE_MSK1 (AO_CTRL_BASE + 0x944)
|
||||
#define AO_SC_MCU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x948)
|
||||
#define AO_SC_MCU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x94C)
|
||||
#define AO_SC_MCU_VOTE1EN (AO_CTRL_BASE + 0x960)
|
||||
#define AO_SC_MCU_VOTE1DIS (AO_CTRL_BASE + 0x964)
|
||||
#define AO_SC_MCU_VOTE1STAT (AO_CTRL_BASE + 0x968)
|
||||
#define AO_SC_MCU_VOTE1_MSK0 (AO_CTRL_BASE + 0x970)
|
||||
#define AO_SC_MCU_VOTE1_MSK1 (AO_CTRL_BASE + 0x974)
|
||||
#define AO_SC_MCU_VOTE1STAT0_MSK (AO_CTRL_BASE + 0x978)
|
||||
#define AO_SC_MCU_VOTE1STAT1_MSK (AO_CTRL_BASE + 0x97C)
|
||||
#define AO_SC_MCU_VOTE2EN (AO_CTRL_BASE + 0x980)
|
||||
#define AO_SC_MCU_VOTE2DIS (AO_CTRL_BASE + 0x984)
|
||||
#define AO_SC_MCU_VOTE2STAT (AO_CTRL_BASE + 0x988)
|
||||
#define AO_SC_MCU_VOTE2_MSK0 (AO_CTRL_BASE + 0x990)
|
||||
#define AO_SC_MCU_VOTE2_MSK1 (AO_CTRL_BASE + 0x994)
|
||||
#define AO_SC_MCU_VOTE2STAT0_MSK (AO_CTRL_BASE + 0x998)
|
||||
#define AO_SC_MCU_VOTE2STAT1_MSK (AO_CTRL_BASE + 0x99C)
|
||||
#define AO_SC_VOTE_CTRL (AO_CTRL_BASE + 0x9A0)
|
||||
#define AO_SC_VOTE_STAT (AO_CTRL_BASE + 0x9A4)
|
||||
#define AO_SC_ECONUM (AO_CTRL_BASE + 0xF00)
|
||||
#define AO_SCCHIPID (AO_CTRL_BASE + 0xF10)
|
||||
#define AO_SCSOCID (AO_CTRL_BASE + 0xF1C)
|
||||
#define AO_SC_SOC_FPGA_RTL_DEF (AO_CTRL_BASE + 0xFE0)
|
||||
#define AO_SC_SOC_FPGA_PR_DEF (AO_CTRL_BASE + 0xFE4)
|
||||
#define AO_SC_SOC_FPGA_RES_DEF0 (AO_CTRL_BASE + 0xFE8)
|
||||
#define AO_SC_SOC_FPGA_RES_DEF1 (AO_CTRL_BASE + 0xFEC)
|
||||
#define AO_SC_XTAL_CTRL0 (AO_CTRL_BASE + 0x102)
|
||||
#define AO_SC_XTAL_CTRL1 (AO_CTRL_BASE + 0x102)
|
||||
#define AO_SC_XTAL_CTRL3 (AO_CTRL_BASE + 0x103)
|
||||
#define AO_SC_XTAL_CTRL5 (AO_CTRL_BASE + 0x103)
|
||||
#define AO_SC_XTAL_STAT0 (AO_CTRL_BASE + 0x106)
|
||||
#define AO_SC_XTAL_STAT1 (AO_CTRL_BASE + 0x107)
|
||||
#define AO_SC_EFUSE_CHIPID0 (AO_CTRL_BASE + 0x108)
|
||||
#define AO_SC_EFUSE_CHIPID1 (AO_CTRL_BASE + 0x108)
|
||||
#define AO_SC_EFUSE_SYS_CTRL (AO_CTRL_BASE + 0x108)
|
||||
#define AO_SC_DEBUG_CTRL1 (AO_CTRL_BASE + 0x128)
|
||||
#define AO_SC_DBG_STAT (AO_CTRL_BASE + 0x12B)
|
||||
#define AO_SC_ARM_DBG_KEY0 (AO_CTRL_BASE + 0x12B)
|
||||
#define AO_SC_RESERVED31 (AO_CTRL_BASE + 0x13A)
|
||||
#define AO_SC_RESERVED32 (AO_CTRL_BASE + 0x13A)
|
||||
#define AO_SC_RESERVED33 (AO_CTRL_BASE + 0x13A)
|
||||
#define AO_SC_RESERVED34 (AO_CTRL_BASE + 0x13A)
|
||||
#define AO_SC_RESERVED35 (AO_CTRL_BASE + 0x13B)
|
||||
#define AO_SC_RESERVED36 (AO_CTRL_BASE + 0x13B)
|
||||
#define AO_SC_RESERVED37 (AO_CTRL_BASE + 0x13B)
|
||||
#define AO_SC_RESERVED38 (AO_CTRL_BASE + 0x13B)
|
||||
#define AO_SC_ALWAYSON_SYS_CTRL0 (AO_CTRL_BASE + 0x148)
|
||||
#define AO_SC_ALWAYSON_SYS_CTRL1 (AO_CTRL_BASE + 0x148)
|
||||
#define AO_SC_ALWAYSON_SYS_CTRL2 (AO_CTRL_BASE + 0x148)
|
||||
#define AO_SC_ALWAYSON_SYS_CTRL3 (AO_CTRL_BASE + 0x148)
|
||||
#define AO_SC_ALWAYSON_SYS_CTRL10 (AO_CTRL_BASE + 0x14A)
|
||||
#define AO_SC_ALWAYSON_SYS_CTRL11 (AO_CTRL_BASE + 0x14A)
|
||||
#define AO_SC_ALWAYSON_SYS_STAT0 (AO_CTRL_BASE + 0x14C)
|
||||
#define AO_SC_ALWAYSON_SYS_STAT1 (AO_CTRL_BASE + 0x14C)
|
||||
#define AO_SC_ALWAYSON_SYS_STAT2 (AO_CTRL_BASE + 0x14C)
|
||||
#define AO_SC_ALWAYSON_SYS_STAT3 (AO_CTRL_BASE + 0x14C)
|
||||
#define AO_SC_PWUP_TIME0 (AO_CTRL_BASE + 0x188)
|
||||
#define AO_SC_PWUP_TIME1 (AO_CTRL_BASE + 0x188)
|
||||
#define AO_SC_PWUP_TIME2 (AO_CTRL_BASE + 0x188)
|
||||
#define AO_SC_PWUP_TIME3 (AO_CTRL_BASE + 0x188)
|
||||
#define AO_SC_PWUP_TIME4 (AO_CTRL_BASE + 0x189)
|
||||
#define AO_SC_PWUP_TIME5 (AO_CTRL_BASE + 0x189)
|
||||
#define AO_SC_PWUP_TIME6 (AO_CTRL_BASE + 0x189)
|
||||
#define AO_SC_PWUP_TIME7 (AO_CTRL_BASE + 0x189)
|
||||
#define AO_SC_SECURITY_CTRL1 (AO_CTRL_BASE + 0x1C0)
|
||||
#define AO_SC_SYSTEST_SLICER_CNT0 (AO_CTRL_BASE + 0x890)
|
||||
#define AO_SC_SYSTEST_SLICER_CNT1 (AO_CTRL_BASE + 0x894)
|
||||
|
||||
#define AO_SC_SYS_CTRL0_MODE_NORMAL 0x004
|
||||
#define AO_SC_SYS_CTRL0_MODE_MASK 0x007
|
||||
|
||||
#define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0)
|
||||
#define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1)
|
||||
#define AO_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2)
|
||||
#define AO_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3)
|
||||
#define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4)
|
||||
#define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6)
|
||||
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7)
|
||||
#define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8)
|
||||
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9)
|
||||
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10)
|
||||
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11)
|
||||
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12)
|
||||
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13)
|
||||
#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15)
|
||||
#define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16)
|
||||
#define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17)
|
||||
#define AO_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18)
|
||||
#define AO_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19)
|
||||
#define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20)
|
||||
#define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22)
|
||||
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23)
|
||||
#define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24)
|
||||
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25)
|
||||
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26)
|
||||
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
|
||||
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
|
||||
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
|
||||
#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1U << 31)
|
||||
|
||||
#define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
|
||||
#define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
|
||||
#define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
|
||||
#define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
|
||||
#define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
|
||||
#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1U << 31)
|
||||
|
||||
#define AO_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
|
||||
#define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
|
||||
#define AO_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27)
|
||||
#define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
|
||||
#define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
|
||||
#define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
|
||||
#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1U << 31)
|
||||
|
||||
#define AO_SC_SYS_STAT1_MODE_STATUS (1 << 0)
|
||||
#define AO_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
|
||||
#define AO_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17)
|
||||
#define AO_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19)
|
||||
#define AO_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20)
|
||||
#define AO_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27)
|
||||
#define AO_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28)
|
||||
#define AO_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29)
|
||||
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_ECTR_N (1 << 0)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_SYS_N (1 << 1)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_POR_N (1 << 2)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_DAP_N (1 << 3)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER0_N (1 << 4)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER1_N (1 << 5)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT0_N (1 << 6)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT1_N (1 << 7)
|
||||
#define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_S_N (1 << 8)
|
||||
#define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_NS_N (1 << 9)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_EFUSEC_N (1 << 10)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT0_N (1 << 12)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT1_N (1 << 13)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT2_N (1 << 14)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER0_N (1 << 15)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER1_N (1 << 16)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER2_N (1 << 17)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER3_N (1 << 18)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER4_N (1 << 19)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER5_N (1 << 20)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER6_N (1 << 21)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER7_N (1 << 22)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER8_N (1 << 23)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_UART0_N (1 << 24)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N (1 << 25)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_RTC1_N (1 << 26)
|
||||
#define AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N (1 << 27)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_JTAG_AUTH_N (1 << 28)
|
||||
#define AO_SC_PERIPH_RSTDIS4_RESET_CS_DAPB_ON_N (1 << 29)
|
||||
#define AO_SC_PERIPH_RSTDIS4_MDM_SUBSYS_GLB (1 << 30)
|
||||
|
||||
#define AO_SC_PERIPH_CLKEN4_HCLK_MCU (1 << 0)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_MCU_DAP (1 << 3)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER0 (1 << 4)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER1 (1 << 5)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT0 (1 << 6)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT1 (1 << 7)
|
||||
#define AO_SC_PERIPH_CLKEN4_HCLK_IPC_S (1 << 8)
|
||||
#define AO_SC_PERIPH_CLKEN4_HCLK_IPC_NS (1 << 9)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_EFUSEC (1 << 10)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TZPC (1 << 11)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_WDT0 (1 << 12)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_WDT1 (1 << 13)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_WDT2 (1 << 14)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER0 (1 << 15)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER1 (1 << 16)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER2 (1 << 17)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER3 (1 << 18)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER4 (1 << 19)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER5 (1 << 20)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER6 (1 << 21)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER7 (1 << 22)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER8 (1 << 23)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_UART0 (1 << 24)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_RTC0 (1 << 25)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_RTC1 (1 << 26)
|
||||
#define AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI (1 << 27)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH (1 << 28)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON (1 << 29)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_PDM (1 << 30)
|
||||
#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1U << 31)
|
||||
|
||||
#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU (1 << 0)
|
||||
#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU (1 << 1)
|
||||
#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_CCPU (1 << 2)
|
||||
#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_CCPU (1 << 3)
|
||||
#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU (1 << 16)
|
||||
#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_MCU (1 << 17)
|
||||
#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_MCU (1 << 18)
|
||||
#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_MCU (1 << 19)
|
||||
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10)
|
||||
#define AO_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11)
|
||||
|
||||
#define PCLK_TIMER1 (1 << 16)
|
||||
#define PCLK_TIMER0 (1 << 15)
|
||||
|
||||
#endif /* HI6220_REGS_AO_H */
|
||||
+380
@@ -0,0 +1,380 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HI6220_REGS_PERI_H
|
||||
#define HI6220_REGS_PERI_H
|
||||
|
||||
#define PERI_BASE 0xF7030000
|
||||
|
||||
#define PERI_SC_PERIPH_CTRL1 (PERI_BASE + 0x000)
|
||||
#define PERI_SC_PERIPH_CTRL2 (PERI_BASE + 0x004)
|
||||
#define PERI_SC_PERIPH_CTRL3 (PERI_BASE + 0x008)
|
||||
#define PERI_SC_PERIPH_CTRL4 (PERI_BASE + 0x00c)
|
||||
#define PERI_SC_PERIPH_CTRL5 (PERI_BASE + 0x010)
|
||||
#define PERI_SC_PERIPH_CTRL6 (PERI_BASE + 0x014)
|
||||
#define PERI_SC_PERIPH_CTRL8 (PERI_BASE + 0x018)
|
||||
#define PERI_SC_PERIPH_CTRL9 (PERI_BASE + 0x01c)
|
||||
#define PERI_SC_PERIPH_CTRL10 (PERI_BASE + 0x020)
|
||||
#define PERI_SC_PERIPH_CTRL12 (PERI_BASE + 0x024)
|
||||
#define PERI_SC_PERIPH_CTRL13 (PERI_BASE + 0x028)
|
||||
#define PERI_SC_PERIPH_CTRL14 (PERI_BASE + 0x02c)
|
||||
|
||||
#define PERI_SC_DDR_CTRL0 (PERI_BASE + 0x050)
|
||||
#define PERI_SC_PERIPH_STAT1 (PERI_BASE + 0x094)
|
||||
|
||||
#define PERI_SC_PERIPH_CLKEN0 (PERI_BASE + 0x200)
|
||||
#define PERI_SC_PERIPH_CLKDIS0 (PERI_BASE + 0x204)
|
||||
#define PERI_SC_PERIPH_CLKSTAT0 (PERI_BASE + 0x208)
|
||||
#define PERI_SC_PERIPH_CLKEN1 (PERI_BASE + 0x210)
|
||||
#define PERI_SC_PERIPH_CLKDIS1 (PERI_BASE + 0x214)
|
||||
#define PERI_SC_PERIPH_CLKSTAT1 (PERI_BASE + 0x218)
|
||||
#define PERI_SC_PERIPH_CLKEN2 (PERI_BASE + 0x220)
|
||||
#define PERI_SC_PERIPH_CLKDIS2 (PERI_BASE + 0x224)
|
||||
#define PERI_SC_PERIPH_CLKSTAT2 (PERI_BASE + 0x228)
|
||||
#define PERI_SC_PERIPH_CLKEN3 (PERI_BASE + 0x230)
|
||||
#define PERI_SC_PERIPH_CLKDIS3 (PERI_BASE + 0x234)
|
||||
#define PERI_SC_PERIPH_CLKSTAT3 (PERI_BASE + 0x238)
|
||||
#define PERI_SC_PERIPH_CLKEN8 (PERI_BASE + 0x240)
|
||||
#define PERI_SC_PERIPH_CLKDIS8 (PERI_BASE + 0x244)
|
||||
#define PERI_SC_PERIPH_CLKSTAT8 (PERI_BASE + 0x248)
|
||||
#define PERI_SC_PERIPH_CLKEN9 (PERI_BASE + 0x250)
|
||||
#define PERI_SC_PERIPH_CLKDIS9 (PERI_BASE + 0x254)
|
||||
#define PERI_SC_PERIPH_CLKSTAT9 (PERI_BASE + 0x258)
|
||||
#define PERI_SC_PERIPH_CLKEN10 (PERI_BASE + 0x260)
|
||||
#define PERI_SC_PERIPH_CLKDIS10 (PERI_BASE + 0x264)
|
||||
#define PERI_SC_PERIPH_CLKSTAT10 (PERI_BASE + 0x268)
|
||||
#define PERI_SC_PERIPH_CLKEN12 (PERI_BASE + 0x270)
|
||||
#define PERI_SC_PERIPH_CLKDIS12 (PERI_BASE + 0x274)
|
||||
#define PERI_SC_PERIPH_CLKSTAT12 (PERI_BASE + 0x278)
|
||||
|
||||
#define PERI_SC_PERIPH_RSTEN0 (PERI_BASE + 0x300)
|
||||
#define PERI_SC_PERIPH_RSTDIS0 (PERI_BASE + 0x304)
|
||||
#define PERI_SC_PERIPH_RSTSTAT0 (PERI_BASE + 0x308)
|
||||
#define PERI_SC_PERIPH_RSTEN1 (PERI_BASE + 0x310)
|
||||
#define PERI_SC_PERIPH_RSTDIS1 (PERI_BASE + 0x314)
|
||||
#define PERI_SC_PERIPH_RSTSTAT1 (PERI_BASE + 0x318)
|
||||
#define PERI_SC_PERIPH_RSTEN2 (PERI_BASE + 0x320)
|
||||
#define PERI_SC_PERIPH_RSTDIS2 (PERI_BASE + 0x324)
|
||||
#define PERI_SC_PERIPH_RSTSTAT2 (PERI_BASE + 0x328)
|
||||
#define PERI_SC_PERIPH_RSTEN3 (PERI_BASE + 0x330)
|
||||
#define PERI_SC_PERIPH_RSTDIS3 (PERI_BASE + 0x334)
|
||||
#define PERI_SC_PERIPH_RSTSTAT3 (PERI_BASE + 0x338)
|
||||
#define PERI_SC_PERIPH_RSTEN8 (PERI_BASE + 0x340)
|
||||
#define PERI_SC_PERIPH_RSTDIS8 (PERI_BASE + 0x344)
|
||||
#define PERI_SC_PERIPH_RSTSTAT8 (PERI_BASE + 0x338)
|
||||
|
||||
#define PERI_SC_CLK_SEL0 (PERI_BASE + 0x400)
|
||||
#define PERI_SC_CLKCFG8BIT1 (PERI_BASE + 0x494)
|
||||
#define PERI_SC_CLKCFG8BIT2 (PERI_BASE + 0x498)
|
||||
#define PERI_SC_RESERVED8_ADDR (PERI_BASE + 0xd04)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL1 */
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
|
||||
#define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
|
||||
#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
|
||||
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
|
||||
#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
|
||||
#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL2 */
|
||||
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
|
||||
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
|
||||
#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
|
||||
#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
|
||||
#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8)
|
||||
#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9)
|
||||
#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12)
|
||||
#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27)
|
||||
#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL3 */
|
||||
#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0)
|
||||
#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12)
|
||||
#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22)
|
||||
#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL4 */
|
||||
#define PERI_CTRL4_PICO_FSELV (1 << 0)
|
||||
#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3)
|
||||
#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4)
|
||||
#define PERI_CTRL4_PICO_SIDDQ (1 << 6)
|
||||
#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7)
|
||||
#define PERI_CTRL4_PICO_OGDISABLE (1 << 8)
|
||||
#define PERI_CTRL4_PICO_COMMONONN (1 << 9)
|
||||
#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10)
|
||||
#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11)
|
||||
#define PERI_CTRL4_PICO_VATESTENB (1 << 12)
|
||||
#define PERI_CTRL4_PICO_SUSPENDM (1 << 14)
|
||||
#define PERI_CTRL4_PICO_SLEEPM (1 << 15)
|
||||
#define PERI_CTRL4_BC11_C (1 << 16)
|
||||
#define PERI_CTRL4_BC11_B (1 << 17)
|
||||
#define PERI_CTRL4_BC11_A (1 << 18)
|
||||
#define PERI_CTRL4_BC11_GND (1 << 19)
|
||||
#define PERI_CTRL4_BC11_FLOAT (1 << 20)
|
||||
#define PERI_CTRL4_OTG_PHY_SEL (1 << 21)
|
||||
#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22)
|
||||
#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24)
|
||||
#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25)
|
||||
#define PERI_CTRL4_OTG_IDPULLUP (1 << 26)
|
||||
#define PERI_CTRL4_OTG_DRVBUS (1 << 27)
|
||||
#define PERI_CTRL4_OTG_SESSEND (1 << 28)
|
||||
#define PERI_CTRL4_OTG_BVALID (1 << 29)
|
||||
#define PERI_CTRL4_OTG_AVALID (1 << 30)
|
||||
#define PERI_CTRL4_OTG_VBUSVALID (1U << 31)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL5 */
|
||||
#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
|
||||
#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4)
|
||||
#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5)
|
||||
#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6)
|
||||
#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7)
|
||||
#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8)
|
||||
#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9)
|
||||
#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10)
|
||||
#define PERI_CTRL5_DBG_MUX (1 << 11)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL6 */
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11)
|
||||
#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL8 */
|
||||
#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0)
|
||||
#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2)
|
||||
#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4)
|
||||
#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6)
|
||||
#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8)
|
||||
#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11)
|
||||
#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12)
|
||||
#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16)
|
||||
#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20)
|
||||
#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28)
|
||||
|
||||
/* PERI_SC_PERIPH_CTRL9 */
|
||||
#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0)
|
||||
#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1)
|
||||
#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4)
|
||||
#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN0
|
||||
* PERI_SC_PERIPH_CLKDIS0
|
||||
* PERI_SC_PERIPH_CLKSTAT0
|
||||
*/
|
||||
#define PERI_CLK0_MMC0 (1 << 0)
|
||||
#define PERI_CLK0_MMC1 (1 << 1)
|
||||
#define PERI_CLK0_MMC2 (1 << 2)
|
||||
#define PERI_CLK0_NANDC (1 << 3)
|
||||
#define PERI_CLK0_USBOTG (1 << 4)
|
||||
#define PERI_CLK0_PICOPHY (1 << 5)
|
||||
#define PERI_CLK0_PLL (1 << 6)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN1
|
||||
* PERI_SC_PERIPH_CLKDIS1
|
||||
* PERI_SC_PERIPH_CLKSTAT1
|
||||
*/
|
||||
#define PERI_CLK1_HIFI (1 << 0)
|
||||
#define PERI_CLK1_DIGACODEC (1 << 5)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN2
|
||||
* PERI_SC_PERIPH_CLKDIS2
|
||||
* PERI_SC_PERIPH_CLKSTAT2
|
||||
*/
|
||||
#define PERI_CLK2_IPF (1 << 0)
|
||||
#define PERI_CLK2_SOCP (1 << 1)
|
||||
#define PERI_CLK2_DMAC (1 << 2)
|
||||
#define PERI_CLK2_SECENG (1 << 3)
|
||||
#define PERI_CLK2_HPM0 (1 << 5)
|
||||
#define PERI_CLK2_HPM1 (1 << 6)
|
||||
#define PERI_CLK2_HPM2 (1 << 7)
|
||||
#define PERI_CLK2_HPM3 (1 << 8)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN3
|
||||
* PERI_SC_PERIPH_CLKDIS3
|
||||
* PERI_SC_PERIPH_CLKSTAT3
|
||||
*/
|
||||
#define PERI_CLK3_CSSYS (1 << 0)
|
||||
#define PERI_CLK3_I2C0 (1 << 1)
|
||||
#define PERI_CLK3_I2C1 (1 << 2)
|
||||
#define PERI_CLK3_I2C2 (1 << 3)
|
||||
#define PERI_CLK3_I2C3 (1 << 4)
|
||||
#define PERI_CLK3_UART1 (1 << 5)
|
||||
#define PERI_CLK3_UART2 (1 << 6)
|
||||
#define PERI_CLK3_UART3 (1 << 7)
|
||||
#define PERI_CLK3_UART4 (1 << 8)
|
||||
#define PERI_CLK3_SSP (1 << 9)
|
||||
#define PERI_CLK3_PWM (1 << 10)
|
||||
#define PERI_CLK3_BLPWM (1 << 11)
|
||||
#define PERI_CLK3_TSENSOR (1 << 12)
|
||||
#define PERI_CLK3_GPS (1 << 15)
|
||||
#define PERI_CLK3_TCXO_PAD0 (1 << 16)
|
||||
#define PERI_CLK3_TCXO_PAD1 (1 << 17)
|
||||
#define PERI_CLK3_DAPB (1 << 18)
|
||||
#define PERI_CLK3_HKADC (1 << 19)
|
||||
#define PERI_CLK3_CODEC_SSI (1 << 20)
|
||||
#define PERI_CLK3_TZPC_DEP (1 << 21)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN8
|
||||
* PERI_SC_PERIPH_CLKDIS8
|
||||
* PERI_SC_PERIPH_CLKSTAT8
|
||||
*/
|
||||
#define PERI_CLK8_RS0 (1 << 0)
|
||||
#define PERI_CLK8_RS2 (1 << 1)
|
||||
#define PERI_CLK8_RS3 (1 << 2)
|
||||
#define PERI_CLK8_MS0 (1 << 3)
|
||||
#define PERI_CLK8_MS2 (1 << 5)
|
||||
#define PERI_CLK8_XG2RAM0 (1 << 6)
|
||||
#define PERI_CLK8_X2SRAM (1 << 7)
|
||||
#define PERI_CLK8_SRAM (1 << 8)
|
||||
#define PERI_CLK8_ROM (1 << 9)
|
||||
#define PERI_CLK8_HARQ (1 << 10)
|
||||
#define PERI_CLK8_MMU (1 << 11)
|
||||
#define PERI_CLK8_DDRC (1 << 12)
|
||||
#define PERI_CLK8_DDRPHY (1 << 13)
|
||||
#define PERI_CLK8_DDRPHY_REF (1 << 14)
|
||||
#define PERI_CLK8_X2X_SYSNOC (1 << 15)
|
||||
#define PERI_CLK8_X2X_CCPU (1 << 16)
|
||||
#define PERI_CLK8_DDRT (1 << 17)
|
||||
#define PERI_CLK8_DDRPACK_RS (1 << 18)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN9
|
||||
* PERI_SC_PERIPH_CLKDIS9
|
||||
* PERI_SC_PERIPH_CLKSTAT9
|
||||
*/
|
||||
#define PERI_CLK9_CARM_DAP (1 << 0)
|
||||
#define PERI_CLK9_CARM_ATB (1 << 1)
|
||||
#define PERI_CLK9_CARM_LBUS (1 << 2)
|
||||
#define PERI_CLK9_CARM_KERNEL (1 << 3)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN10
|
||||
* PERI_SC_PERIPH_CLKDIS10
|
||||
* PERI_SC_PERIPH_CLKSTAT10
|
||||
*/
|
||||
#define PERI_CLK10_IPF_CCPU (1 << 0)
|
||||
#define PERI_CLK10_SOCP_CCPU (1 << 1)
|
||||
#define PERI_CLK10_SECENG_CCPU (1 << 2)
|
||||
#define PERI_CLK10_HARQ_CCPU (1 << 3)
|
||||
#define PERI_CLK10_IPF_MCU (1 << 16)
|
||||
#define PERI_CLK10_SOCP_MCU (1 << 17)
|
||||
#define PERI_CLK10_SECENG_MCU (1 << 18)
|
||||
#define PERI_CLK10_HARQ_MCU (1 << 19)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_CLKEN12
|
||||
* PERI_SC_PERIPH_CLKDIS12
|
||||
* PERI_SC_PERIPH_CLKSTAT12
|
||||
*/
|
||||
#define PERI_CLK12_HIFI_SRC (1 << 0)
|
||||
#define PERI_CLK12_MMC0_SRC (1 << 1)
|
||||
#define PERI_CLK12_MMC1_SRC (1 << 2)
|
||||
#define PERI_CLK12_MMC2_SRC (1 << 3)
|
||||
#define PERI_CLK12_SYSPLL_DIV (1 << 4)
|
||||
#define PERI_CLK12_TPIU_SRC (1 << 5)
|
||||
#define PERI_CLK12_MMC0_HF (1 << 6)
|
||||
#define PERI_CLK12_MMC1_HF (1 << 7)
|
||||
#define PERI_CLK12_PLL_TEST_SRC (1 << 8)
|
||||
#define PERI_CLK12_CODEC_SOC (1 << 9)
|
||||
#define PERI_CLK12_MEDIA (1 << 10)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_RSTEN0
|
||||
* PERI_SC_PERIPH_RSTDIS0
|
||||
* PERI_SC_PERIPH_RSTSTAT0
|
||||
*/
|
||||
#define PERI_RST0_MMC0 (1 << 0)
|
||||
#define PERI_RST0_MMC1 (1 << 1)
|
||||
#define PERI_RST0_MMC2 (1 << 2)
|
||||
#define PERI_RST0_NANDC (1 << 3)
|
||||
#define PERI_RST0_USBOTG_BUS (1 << 4)
|
||||
#define PERI_RST0_POR_PICOPHY (1 << 5)
|
||||
#define PERI_RST0_USBOTG (1 << 6)
|
||||
#define PERI_RST0_USBOTG_32K (1 << 7)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_RSTEN1
|
||||
* PERI_SC_PERIPH_RSTDIS1
|
||||
* PERI_SC_PERIPH_RSTSTAT1
|
||||
*/
|
||||
#define PERI_RST1_HIFI (1 << 0)
|
||||
#define PERI_RST1_DIGACODEC (1 << 5)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_RSTEN2
|
||||
* PERI_SC_PERIPH_RSTDIS2
|
||||
* PERI_SC_PERIPH_RSTSTAT2
|
||||
*/
|
||||
#define PERI_RST2_IPF (1 << 0)
|
||||
#define PERI_RST2_SOCP (1 << 1)
|
||||
#define PERI_RST2_DMAC (1 << 2)
|
||||
#define PERI_RST2_SECENG (1 << 3)
|
||||
#define PERI_RST2_ABB (1 << 4)
|
||||
#define PERI_RST2_HPM0 (1 << 5)
|
||||
#define PERI_RST2_HPM1 (1 << 6)
|
||||
#define PERI_RST2_HPM2 (1 << 7)
|
||||
#define PERI_RST2_HPM3 (1 << 8)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_RSTEN3
|
||||
* PERI_SC_PERIPH_RSTDIS3
|
||||
* PERI_SC_PERIPH_RSTSTAT3
|
||||
*/
|
||||
#define PERI_RST3_CSSYS (1 << 0)
|
||||
#define PERI_RST3_I2C0 (1 << 1)
|
||||
#define PERI_RST3_I2C1 (1 << 2)
|
||||
#define PERI_RST3_I2C2 (1 << 3)
|
||||
#define PERI_RST3_I2C3 (1 << 4)
|
||||
#define PERI_RST3_UART1 (1 << 5)
|
||||
#define PERI_RST3_UART2 (1 << 6)
|
||||
#define PERI_RST3_UART3 (1 << 7)
|
||||
#define PERI_RST3_UART4 (1 << 8)
|
||||
#define PERI_RST3_SSP (1 << 9)
|
||||
#define PERI_RST3_PWM (1 << 10)
|
||||
#define PERI_RST3_BLPWM (1 << 11)
|
||||
#define PERI_RST3_TSENSOR (1 << 12)
|
||||
#define PERI_RST3_DAPB (1 << 18)
|
||||
#define PERI_RST3_HKADC (1 << 19)
|
||||
#define PERI_RST3_CODEC (1 << 20)
|
||||
|
||||
/*
|
||||
* PERI_SC_PERIPH_RSTEN8
|
||||
* PERI_SC_PERIPH_RSTDIS8
|
||||
* PERI_SC_PERIPH_RSTSTAT8
|
||||
*/
|
||||
#define PERI_RST8_RS0 (1 << 0)
|
||||
#define PERI_RST8_RS2 (1 << 1)
|
||||
#define PERI_RST8_RS3 (1 << 2)
|
||||
#define PERI_RST8_MS0 (1 << 3)
|
||||
#define PERI_RST8_MS2 (1 << 5)
|
||||
#define PERI_RST8_XG2RAM0 (1 << 6)
|
||||
#define PERI_RST8_X2SRAM_TZMA (1 << 7)
|
||||
#define PERI_RST8_SRAM (1 << 8)
|
||||
#define PERI_RST8_HARQ (1 << 10)
|
||||
#define PERI_RST8_DDRC (1 << 12)
|
||||
#define PERI_RST8_DDRC_APB (1 << 13)
|
||||
#define PERI_RST8_DDRPACK_APB (1 << 14)
|
||||
#define PERI_RST8_DDRT (1 << 17)
|
||||
|
||||
#endif /* HI6220_REGS_PERI_H */
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HI6220_REGS_PIN_H
|
||||
#define HI6220_REGS_PIN_H
|
||||
|
||||
#define IOMG_BASE 0xF7010000
|
||||
|
||||
#define IOMG_SD_CLK (IOMG_BASE + 0x0C)
|
||||
#define IOMG_SD_CMD (IOMG_BASE + 0x10)
|
||||
#define IOMG_SD_DATA0 (IOMG_BASE + 0x14)
|
||||
#define IOMG_SD_DATA1 (IOMG_BASE + 0x18)
|
||||
#define IOMG_SD_DATA2 (IOMG_BASE + 0x1C)
|
||||
#define IOMG_SD_DATA3 (IOMG_BASE + 0x20)
|
||||
#define IOMG_GPIO24 (IOMG_BASE + 0x140)
|
||||
|
||||
#define IOMG_MUX_FUNC0 0
|
||||
#define IOMG_MUX_FUNC1 1
|
||||
#define IOMG_MUX_FUNC2 2
|
||||
|
||||
#define IOCG1_BASE 0xF7010800
|
||||
#define IOCG2_BASE 0xF8001800
|
||||
|
||||
#define IOCG_SD_CLK (IOCG1_BASE + 0x0C)
|
||||
#define IOCG_SD_CMD (IOCG1_BASE + 0x10)
|
||||
#define IOCG_SD_DATA0 (IOCG1_BASE + 0x14)
|
||||
#define IOCG_SD_DATA1 (IOCG1_BASE + 0x18)
|
||||
#define IOCG_SD_DATA2 (IOCG1_BASE + 0x1C)
|
||||
#define IOCG_SD_DATA3 (IOCG1_BASE + 0x20)
|
||||
#define IOCG_GPIO24 (IOCG1_BASE + 0x150)
|
||||
#define IOCG_GPIO8 (IOCG2_BASE + 0x30)
|
||||
|
||||
#define IOCG_DRIVE_8MA (2 << 4)
|
||||
#define IOCG_DRIVE_10MA (3 << 4)
|
||||
#define IOCG_INPUT_16MA 0x64
|
||||
#define IOCG_INPUT_12MA 0x54
|
||||
#define IOCG_PULLDOWN (1 << 1)
|
||||
#define IOCG_PULLUP (1 << 0)
|
||||
|
||||
#endif /* HI6220_REGS_PIN_H */
|
||||
+101
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HI6220_REGS_PMCTRL_H
|
||||
#define HI6220_REGS_PMCTRL_H
|
||||
|
||||
#define PMCTRL_BASE 0xF7032000
|
||||
|
||||
#define PMCTRL_ACPUPLLCTRL (PMCTRL_BASE + 0x000)
|
||||
#define PMCTRL_ACPUPLLFREQ (PMCTRL_BASE + 0x004)
|
||||
#define PMCTRL_DDRPLL1CTRL (PMCTRL_BASE + 0x010)
|
||||
#define PMCTRL_DDRPLL0CTRL (PMCTRL_BASE + 0x030)
|
||||
#define PMCTRL_MEDPLLCTRL (PMCTRL_BASE + 0x038)
|
||||
#define PMCTRL_ACPUPLLSEL (PMCTRL_BASE + 0x100)
|
||||
#define PMCTRL_ACPUCLKDIV (PMCTRL_BASE + 0x104)
|
||||
#define PMCTRL_ACPUSYSPLLCFG (PMCTRL_BASE + 0x110)
|
||||
#define PMCTRL_ACPUCLKOFFCFG (PMCTRL_BASE + 0x114)
|
||||
#define PMCTRL_ACPUPLLFRAC (PMCTRL_BASE + 0x134)
|
||||
#define PMCTRL_ACPUPMUVOLUPTIME (PMCTRL_BASE + 0x360)
|
||||
#define PMCTRL_ACPUPMUVOLDNTIME (PMCTRL_BASE + 0x364)
|
||||
#define PMCTRL_ACPUVOLPMUADDR (PMCTRL_BASE + 0x368)
|
||||
#define PMCTRL_ACPUVOLUPSTEP (PMCTRL_BASE + 0x36c)
|
||||
#define PMCTRL_ACPUVOLDNSTEP (PMCTRL_BASE + 0x370)
|
||||
#define PMCTRL_ACPUDFTVOL (PMCTRL_BASE + 0x374)
|
||||
#define PMCTRL_ACPUDESTVOL (PMCTRL_BASE + 0x378)
|
||||
#define PMCTRL_ACPUVOLTTIMEOUT (PMCTRL_BASE + 0x37c)
|
||||
|
||||
#define PMCTRL_ACPUPLLCTRL_EN_CFG (1 << 0)
|
||||
|
||||
#define PMCTRL_ACPUCLKDIV_CPUEXT_CFG_MASK (3 << 0)
|
||||
#define PMCTRL_ACPUCLKDIV_DDR_CFG_MASK (3 << 8)
|
||||
#define PMCTRL_ACPUCLKDIV_CPUEXT_STAT_MASK (3 << 16)
|
||||
#define PMCTRL_ACPUCLKDIV_DDR_STAT_MASK (3 << 24)
|
||||
|
||||
#define PMCTRL_ACPUPLLSEL_ACPUPLL_CFG (1 << 0)
|
||||
#define PMCTRL_ACPUPLLSEL_ACPUPLL_STAT (1 << 1)
|
||||
#define PMCTRL_ACPUPLLSEL_SYSPLL_STAT (1 << 2)
|
||||
|
||||
#define PMCTRL_ACPUSYSPLL_CLKDIV_CFG_MASK 0x7
|
||||
#define PMCTRL_ACPUSYSPLL_CLKEN_CFG (1 << 4)
|
||||
#define PMCTRL_ACPUSYSPLL_CLKDIV_SW (3 << 12)
|
||||
|
||||
#define PMCTRL_ACPUSYSPLLCFG_SYSPLL_CLKEN (1 << 4)
|
||||
#define PMCTRL_ACPUSYSPLLCFG_CLKDIV_MASK (3 << 12)
|
||||
|
||||
#define PMCTRL_ACPUDESTVOL_DEST_VOL_MASK 0x7f
|
||||
#define PMCTRL_ACPUDESTVOL_CURR_VOL_MASK (0x7f << 8)
|
||||
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START (0)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_END (0)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_START (2)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_END (2)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_START (4)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_END (27)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START (28)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_END (28)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_START (29)
|
||||
#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_END (29)
|
||||
|
||||
#define SOC_PMCTRL_ACPUPLLFRAC_ADDR(base) ((base) + (0x134))
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START (12)
|
||||
|
||||
#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START (0)
|
||||
#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_END (0)
|
||||
#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START (1)
|
||||
#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_END (1)
|
||||
#define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_START (2)
|
||||
#define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_END (2)
|
||||
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START (0)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_END (1)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START (8)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_END (9)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START (16)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_END (17)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START (24)
|
||||
#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_END (25)
|
||||
|
||||
#define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START (0)
|
||||
#define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END (6)
|
||||
#define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START (8)
|
||||
#define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_END (14)
|
||||
|
||||
#define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START (0)
|
||||
#define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_END (0)
|
||||
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_START (0)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_END (2)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START (4)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_END (4)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_START (8)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_END (9)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_START (16)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_END (19)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_START (20)
|
||||
#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_END (20)
|
||||
|
||||
#endif /* HI6220_REGS_PMCTRL_H */
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HI6553_H
|
||||
#define HI6553_H
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <hi6220.h>
|
||||
|
||||
#define HI6553_DISABLE6_XO_CLK (PMUSSI_BASE + (0x036 << 2))
|
||||
|
||||
#define DISABLE6_XO_CLK_BB (1 << 0)
|
||||
#define DISABLE6_XO_CLK_CONN (1 << 1)
|
||||
#define DISABLE6_XO_CLK_NFC (1 << 2)
|
||||
#define DISABLE6_XO_CLK_RF1 (1 << 3)
|
||||
#define DISABLE6_XO_CLK_RF2 (1 << 4)
|
||||
|
||||
#define HI6553_VERSION_REG (PMUSSI_BASE + (0x000 << 2))
|
||||
#define HI6553_IRQ2_MASK (PMUSSI_BASE + (0x008 << 2))
|
||||
#define HI6553_ENABLE2_LDO1_8 (PMUSSI_BASE + (0x029 << 2))
|
||||
#define HI6553_DISABLE2_LDO1_8 (PMUSSI_BASE + (0x02a << 2))
|
||||
#define HI6553_ONOFF_STATUS2_LDO1_8 (PMUSSI_BASE + (0x02b << 2))
|
||||
#define HI6553_ENABLE3_LDO9_16 (PMUSSI_BASE + (0x02c << 2))
|
||||
#define HI6553_DISABLE3_LDO9_16 (PMUSSI_BASE + (0x02d << 2))
|
||||
#define HI6553_ONOFF_STATUS3_LDO9_16 (PMUSSI_BASE + (0x02e << 2))
|
||||
#define HI6553_ENABLE4_LDO17_22 (PMUSSI_BASE + (0x02f << 2))
|
||||
#define HI6553_DISABLE4_LDO17_22 (PMUSSI_BASE + (0x030 << 2))
|
||||
#define HI6553_ONOFF_STATUS4_LDO17_22 (PMUSSI_BASE + (0x031 << 2))
|
||||
#define HI6553_PERI_EN_MARK (PMUSSI_BASE + (0x040 << 2))
|
||||
#define HI6553_BUCK2_REG1 (PMUSSI_BASE + (0x04a << 2))
|
||||
#define HI6553_BUCK2_REG5 (PMUSSI_BASE + (0x04e << 2))
|
||||
#define HI6553_BUCK2_REG6 (PMUSSI_BASE + (0x04f << 2))
|
||||
#define HI6553_BUCK3_REG3 (PMUSSI_BASE + (0x054 << 2))
|
||||
#define HI6553_BUCK3_REG5 (PMUSSI_BASE + (0x056 << 2))
|
||||
#define HI6553_BUCK3_REG6 (PMUSSI_BASE + (0x057 << 2))
|
||||
#define HI6553_BUCK4_REG2 (PMUSSI_BASE + (0x05b << 2))
|
||||
#define HI6553_BUCK4_REG5 (PMUSSI_BASE + (0x05e << 2))
|
||||
#define HI6553_BUCK4_REG6 (PMUSSI_BASE + (0x05f << 2))
|
||||
#define HI6553_CLK_TOP0 (PMUSSI_BASE + (0x063 << 2))
|
||||
#define HI6553_CLK_TOP3 (PMUSSI_BASE + (0x066 << 2))
|
||||
#define HI6553_CLK_TOP4 (PMUSSI_BASE + (0x067 << 2))
|
||||
#define HI6553_VSET_BUCK2_ADJ (PMUSSI_BASE + (0x06d << 2))
|
||||
#define HI6553_VSET_BUCK3_ADJ (PMUSSI_BASE + (0x06e << 2))
|
||||
#define HI6553_LDO7_REG_ADJ (PMUSSI_BASE + (0x078 << 2))
|
||||
#define HI6553_LDO10_REG_ADJ (PMUSSI_BASE + (0x07b << 2))
|
||||
#define HI6553_LDO15_REG_ADJ (PMUSSI_BASE + (0x080 << 2))
|
||||
#define HI6553_LDO19_REG_ADJ (PMUSSI_BASE + (0x084 << 2))
|
||||
#define HI6553_LDO20_REG_ADJ (PMUSSI_BASE + (0x085 << 2))
|
||||
#define HI6553_LDO21_REG_ADJ (PMUSSI_BASE + (0x086 << 2))
|
||||
#define HI6553_LDO22_REG_ADJ (PMUSSI_BASE + (0x087 << 2))
|
||||
#define HI6553_DR_LED_CTRL (PMUSSI_BASE + (0x098 << 2))
|
||||
#define HI6553_DR_OUT_CTRL (PMUSSI_BASE + (0x099 << 2))
|
||||
#define HI6553_DR3_ISET (PMUSSI_BASE + (0x09a << 2))
|
||||
#define HI6553_DR3_START_DEL (PMUSSI_BASE + (0x09b << 2))
|
||||
#define HI6553_DR4_ISET (PMUSSI_BASE + (0x09c << 2))
|
||||
#define HI6553_DR4_START_DEL (PMUSSI_BASE + (0x09d << 2))
|
||||
#define HI6553_DR345_TIM_CONF0 (PMUSSI_BASE + (0x0a0 << 2))
|
||||
#define HI6553_NP_REG_ADJ1 (PMUSSI_BASE + (0x0be << 2))
|
||||
#define HI6553_NP_REG_CHG (PMUSSI_BASE + (0x0c0 << 2))
|
||||
#define HI6553_BUCK01_CTRL2 (PMUSSI_BASE + (0x0d9 << 2))
|
||||
#define HI6553_BUCK0_CTRL1 (PMUSSI_BASE + (0x0dd << 2))
|
||||
#define HI6553_BUCK0_CTRL5 (PMUSSI_BASE + (0x0e1 << 2))
|
||||
#define HI6553_BUCK0_CTRL7 (PMUSSI_BASE + (0x0e3 << 2))
|
||||
#define HI6553_BUCK1_CTRL1 (PMUSSI_BASE + (0x0e8 << 2))
|
||||
#define HI6553_BUCK1_CTRL5 (PMUSSI_BASE + (0x0ec << 2))
|
||||
#define HI6553_BUCK1_CTRL7 (PMUSSI_BASE + (0x0ef << 2))
|
||||
#define HI6553_CLK19M2_600_586_EN (PMUSSI_BASE + (0x0fe << 2))
|
||||
|
||||
#define LED_START_DELAY_TIME 0x00
|
||||
#define LED_ELEC_VALUE 0x07
|
||||
#define LED_LIGHT_TIME 0xf0
|
||||
#define LED_GREEN_ENABLE (1 << 1)
|
||||
#define LED_OUT_CTRL 0x00
|
||||
|
||||
#define PMU_HI6552_V300 0x30
|
||||
#define PMU_HI6552_V310 0x31
|
||||
|
||||
#endif /* HI6553_H */
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HIKEY_DEF_H
|
||||
#define HIKEY_DEF_H
|
||||
|
||||
/* Always assume DDR is 1GB size. */
|
||||
#define DDR_BASE 0x0
|
||||
#define DDR_SIZE 0x40000000
|
||||
|
||||
#define DEVICE_BASE 0xF4000000
|
||||
#define DEVICE_SIZE 0x05800000
|
||||
|
||||
/* Memory location options for TSP */
|
||||
#define HIKEY_SRAM_ID 0
|
||||
#define HIKEY_DRAM_ID 1
|
||||
|
||||
/*
|
||||
* DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
|
||||
* regions
|
||||
* - Secure DDR (default is the top 16MB) used by OP-TEE
|
||||
* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
|
||||
* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
|
||||
* - Non-secure DDR (8MB) reserved for OP-TEE's future use
|
||||
*/
|
||||
#define DDR_SEC_SIZE 0x01000000
|
||||
#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE) /* 0x3F000000 */
|
||||
|
||||
#define DDR_SDP_SIZE 0x00400000
|
||||
#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
|
||||
DDR_SDP_SIZE)
|
||||
|
||||
#define SRAM_BASE 0xFFF80000
|
||||
#define SRAM_SIZE 0x00012000
|
||||
|
||||
/*
|
||||
* PL011 related constants
|
||||
*/
|
||||
#define PL011_UART0_BASE 0xF8015000
|
||||
#define PL011_UART2_BASE 0xF7112000
|
||||
#define PL011_UART3_BASE 0xF7113000
|
||||
#define PL011_BAUDRATE 115200
|
||||
#define PL011_UART_CLK_IN_HZ 19200000
|
||||
|
||||
#define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000)
|
||||
#define HIKEY_USB_DESC_SIZE 0x00100000
|
||||
#define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000)
|
||||
#define HIKEY_USB_DATA_SIZE 0x10000000
|
||||
#define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE)
|
||||
#define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE
|
||||
#define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \
|
||||
HIKEY_FB_BUFFER_SIZE)
|
||||
#define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE
|
||||
|
||||
#define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000)
|
||||
#define HIKEY_USB_DESC_IN_SIZE 0x00040000
|
||||
#define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \
|
||||
HIKEY_USB_DESC_IN_SIZE)
|
||||
#define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000
|
||||
#define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \
|
||||
HIKEY_USB_DESC_EP0_OUT_SIZE)
|
||||
#define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000
|
||||
|
||||
#define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000)
|
||||
#define HIKEY_MMC_DESC_SIZE 0x00100000
|
||||
|
||||
/*
|
||||
* HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot
|
||||
* and eMMC driver. Since it could avoid to memory copy.
|
||||
* So this SRAM region is used twice. First, it's used in BL1 as temporary
|
||||
* buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region
|
||||
* needs to be clear before used in BL2.
|
||||
*/
|
||||
#define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000)
|
||||
#define HIKEY_MMC_DATA_SIZE 0x20000000
|
||||
#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
|
||||
#define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
|
||||
#define HIKEY_BL1_MMC_DESC_SIZE 0x00001000
|
||||
#define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \
|
||||
HIKEY_BL1_MMC_DESC_SIZE)
|
||||
#define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000
|
||||
|
||||
#define EMMC_BASE 0
|
||||
#define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0)
|
||||
#define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10)
|
||||
#define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0)
|
||||
#define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30)
|
||||
|
||||
/*
|
||||
* GIC400 interrupt handling related constants
|
||||
*/
|
||||
#define IRQ_SEC_PHY_TIMER 29
|
||||
#define IRQ_SEC_SGI_0 8
|
||||
#define IRQ_SEC_SGI_1 9
|
||||
#define IRQ_SEC_SGI_2 10
|
||||
#define IRQ_SEC_SGI_3 11
|
||||
#define IRQ_SEC_SGI_4 12
|
||||
#define IRQ_SEC_SGI_5 13
|
||||
#define IRQ_SEC_SGI_6 14
|
||||
#define IRQ_SEC_SGI_7 15
|
||||
#define IRQ_SEC_SGI_8 16
|
||||
|
||||
#endif /* HIKEY_DEF_H */
|
||||
+122
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HIKEY_LAYOUT_H
|
||||
#define HIKEY_LAYOUT_H
|
||||
|
||||
/*
|
||||
* Platform memory map related constants
|
||||
*/
|
||||
#define XG2RAM0_BASE 0xF9800000
|
||||
#define XG2RAM0_SIZE 0x00400000
|
||||
|
||||
/*
|
||||
* BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
|
||||
*/
|
||||
#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
|
||||
#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
|
||||
#define BL1_XG2RAM0_OFFSET 0x1000
|
||||
|
||||
/*
|
||||
* BL1 specific defines.
|
||||
*
|
||||
* Both loader and BL1_RO region stay in SRAM since they are used to simulate
|
||||
* ROM.
|
||||
* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
|
||||
*
|
||||
* ++++++++++ 0xF980_0000
|
||||
* + loader +
|
||||
* ++++++++++ 0xF980_1000
|
||||
* + BL1_RO +
|
||||
* ++++++++++ 0xF981_8000
|
||||
* + BL1_RW +
|
||||
* ++++++++++ 0xF989_8000
|
||||
*/
|
||||
#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
|
||||
#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x18000)
|
||||
#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */
|
||||
#define BL1_RW_SIZE (0x00080000)
|
||||
#define BL1_RW_LIMIT (0xF9898000)
|
||||
|
||||
/*
|
||||
* Non-Secure BL1U specific defines.
|
||||
*/
|
||||
#define NS_BL1U_BASE (0xf9828000)
|
||||
#define NS_BL1U_SIZE (0x00010000)
|
||||
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
|
||||
|
||||
/*
|
||||
* BL2 specific defines.
|
||||
*
|
||||
* Both loader and BL2 region stay in SRAM.
|
||||
* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
|
||||
*
|
||||
* ++++++++++ 0xF980_0000
|
||||
* + loader +
|
||||
* ++++++++++ 0xF980_1000
|
||||
* + BL2 +
|
||||
* ++++++++++ 0xF983_0000
|
||||
*/
|
||||
#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
|
||||
#define BL2_LIMIT (0xF9830000) /* 0xf983_0000 */
|
||||
|
||||
/*
|
||||
* SCP_BL2 specific defines.
|
||||
* In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
|
||||
* at 0x0100_0000. Then BL2 will parse the sections and loaded them into
|
||||
* predefined separated buffers.
|
||||
*/
|
||||
#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
|
||||
#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
|
||||
#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
|
||||
|
||||
/*
|
||||
* BL31 specific defines.
|
||||
*/
|
||||
#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
|
||||
#define BL31_LIMIT (0xF9898000)
|
||||
|
||||
/*
|
||||
* BL3-2 specific defines.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The TSP currently executes from TZC secured area of DRAM or SRAM.
|
||||
*/
|
||||
#define BL32_SRAM_BASE BL31_LIMIT
|
||||
#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
|
||||
|
||||
#define BL32_DRAM_BASE DDR_SEC_BASE
|
||||
#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
|
||||
|
||||
#ifdef SPD_opteed
|
||||
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
|
||||
#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
|
||||
#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
|
||||
#endif
|
||||
|
||||
#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
|
||||
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
|
||||
#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
|
||||
#define BL32_BASE BL32_DRAM_BASE
|
||||
#define BL32_LIMIT BL32_DRAM_LIMIT
|
||||
#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
|
||||
#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
|
||||
#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
|
||||
#define BL32_BASE BL32_SRAM_BASE
|
||||
#define BL32_LIMIT BL32_SRAM_LIMIT
|
||||
#else
|
||||
#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
|
||||
#endif
|
||||
|
||||
/* BL32 is mandatory in AArch32 */
|
||||
#ifdef __aarch64__
|
||||
#ifdef SPD_none
|
||||
#undef BL32_BASE
|
||||
#endif /* SPD_none */
|
||||
#endif
|
||||
|
||||
#endif /* HIKEY_LAYOUT_H */
|
||||
+46
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HISI_IPC_H
|
||||
#define HISI_IPC_H
|
||||
|
||||
#define HISI_IPC_CORE_ACPU 0x0
|
||||
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU0_PD 10
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU1_PD 11
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU2_PD 12
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU3_PD 13
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU_PD 16
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU4_PD 26
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU5_PD 27
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU6_PD 28
|
||||
#define HISI_IPC_MCU_INT_SRC_ACPU7_PD 29
|
||||
|
||||
#define HISI_IPC_SEM_CPUIDLE 27
|
||||
#define HISI_IPC_INT_SRC_NUM 32
|
||||
|
||||
#define HISI_IPC_PM_ON 0
|
||||
#define HISI_IPC_PM_OFF 1
|
||||
|
||||
#define HISI_IPC_OK (0)
|
||||
#define HISI_IPC_ERROR (-1)
|
||||
|
||||
#define HISI_IPC_BASE_ADDR (0xF7510000)
|
||||
#define HISI_IPC_CPU_RAW_INT_ADDR (0xF7510420)
|
||||
#define HISI_IPC_ACPU_CTRL(i) (0xF7510800 + (i << 3))
|
||||
|
||||
void hisi_ipc_spin_lock(unsigned int signal);
|
||||
void hisi_ipc_spin_unlock(unsigned int signal);
|
||||
void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster);
|
||||
void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster);
|
||||
void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster);
|
||||
void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster);
|
||||
void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster);
|
||||
void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster);
|
||||
void hisi_ipc_psci_system_off(void);
|
||||
int hisi_ipc_init(void);
|
||||
|
||||
#endif /* HISI_IPC_H */
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HISI_MCU_H
|
||||
#define HISI_MCU_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern void hisi_mcu_enable_sram(void);
|
||||
extern void hisi_mcu_start_run(void);
|
||||
extern int hisi_mcu_load_image(uintptr_t image_base, uint32_t image_size);
|
||||
|
||||
#endif /* HISI_MCU_H */
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HISI_PWRC_H
|
||||
#define HISI_PWRC_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
void hisi_pwrc_set_cluster_wfi(unsigned int id);
|
||||
void hisi_pwrc_set_core_bx_addr(unsigned int core,
|
||||
unsigned int cluster,
|
||||
uintptr_t entry_point);
|
||||
void hisi_pwrc_enable_debug(unsigned int core,
|
||||
unsigned int cluster);
|
||||
int hisi_pwrc_setup(void);
|
||||
|
||||
#endif /*__ASSEMBLER__*/
|
||||
|
||||
#endif /* HISI_PWRC_H */
|
||||
+21
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HISI_SIP_SVC_H
|
||||
#define HISI_SIP_SVC_H
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
|
||||
#define HISI_SIP_SVC_CALL_COUNT 0x8200ff00
|
||||
#define HISI_SIP_SVC_UID 0x8200ff01
|
||||
/* 0x8200ff02 is reserved */
|
||||
#define HISI_SIP_SVC_VERSION 0x8200ff03
|
||||
|
||||
/* HISI SiP Service Calls version numbers */
|
||||
#define HISI_SIP_SVC_VERSION_MAJOR 0x0
|
||||
#define HISI_SIP_SVC_VERSION_MINOR 0x1
|
||||
|
||||
#endif /* HISI_SIP_SVC_H */
|
||||
+327
@@ -0,0 +1,327 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HISI_SRAM_MAP_H
|
||||
#define HISI_SRAM_MAP_H
|
||||
|
||||
/*
|
||||
* SRAM Memory Region Layout
|
||||
*
|
||||
* +-----------------------+
|
||||
* | Low Power Mode | 7KB
|
||||
* +-----------------------+
|
||||
* | Secure OS | 64KB
|
||||
* +-----------------------+
|
||||
* | Software Flag | 1KB
|
||||
* +-----------------------+
|
||||
*
|
||||
*/
|
||||
|
||||
#define SOC_SRAM_OFF_BASE_ADDR (0xFFF80000)
|
||||
|
||||
/* PM Section: 7KB */
|
||||
#define SRAM_PM_ADDR (SOC_SRAM_OFF_BASE_ADDR)
|
||||
#define SRAM_PM_SIZE (0x00001C00)
|
||||
|
||||
/* TEE OS Section: 64KB */
|
||||
#define SRAM_TEEOS_ADDR (SRAM_PM_ADDR + SRAM_PM_SIZE)
|
||||
#define SRAM_TEEOS_SIZE (0x00010000)
|
||||
|
||||
/* General Use Section: 1KB */
|
||||
#define SRAM_GENERAL_ADDR (SRAM_TEEOS_ADDR + SRAM_TEEOS_SIZE)
|
||||
#define SRAM_GENERAL_SIZE (0x00000400)
|
||||
|
||||
/*
|
||||
* General Usage Section Layout:
|
||||
*
|
||||
* +-----------------------+
|
||||
* | AP boot flag | 64B
|
||||
* +-----------------------+
|
||||
* | DICC flag | 32B
|
||||
* +-----------------------+
|
||||
* | Soft flag | 256B
|
||||
* +-----------------------+
|
||||
* | Thermal flag | 128B
|
||||
* +-----------------------+
|
||||
* | CSHELL | 4B
|
||||
* +-----------------------+
|
||||
* | Uart Switching | 4B
|
||||
* +-----------------------+
|
||||
* | ICC | 1024B
|
||||
* +-----------------------+
|
||||
* | Memory Management | 1024B
|
||||
* +-----------------------+
|
||||
* | IFC | 32B
|
||||
* +-----------------------+
|
||||
* | HIFI | 32B
|
||||
* +-----------------------+
|
||||
* | DDR capacity | 4B
|
||||
* +-----------------------+
|
||||
* | Reserved |
|
||||
* +-----------------------+
|
||||
*
|
||||
*/
|
||||
|
||||
/* App Core Boot Flags */
|
||||
#define MEMORY_AXI_ACPU_START_ADDR (SRAM_GENERAL_ADDR)
|
||||
#define MEMORY_AXI_ACPU_START_SIZE (64)
|
||||
|
||||
#define MEMORY_AXI_SRESET_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0000)
|
||||
#define MEMORY_AXI_SECOND_CPU_BOOT_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0004)
|
||||
#define MEMORY_AXI_READY_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0008)
|
||||
#define MEMORY_AXI_FASTBOOT_ENTRY_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x000C)
|
||||
#define MEMORY_AXI_PD_CHARGE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0010)
|
||||
#define MEMORY_AXI_DBG_ALARM_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0014)
|
||||
#define MEMORY_AXI_CHIP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0018)
|
||||
#define MEMORY_AXI_BOARD_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x001C)
|
||||
#define MEMORY_AXI_BOARD_ID_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0020)
|
||||
#define MEMORY_AXI_CHARGETYPE_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0024)
|
||||
#define MEMORY_AXI_COLD_START_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0028)
|
||||
#define MEMORY_AXI_ANDROID_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x002C)
|
||||
#define MEMORY_AXI_ACPU_WDTRST_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0030)
|
||||
#define MEMORY_AXI_ABNRST_BITMAP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0034)
|
||||
#define MEMORY_AXI_32K_CLK_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0038)
|
||||
#define AXI_MODEM_PANIC_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x003C)
|
||||
#define AXI_MODEM_PANIC_FLAG (0x68697369)
|
||||
#define MEMORY_AXI_ACPU_END_ADDR (AXI_MODEM_PANIC_FLAG_ADDR + 4)
|
||||
|
||||
/* DICC Flags */
|
||||
#define MEMORY_AXI_DICC_ADDR (MEMORY_AXI_ACPU_START_ADDR + MEMORY_AXI_ACPU_START_SIZE)
|
||||
#define MEMORY_AXI_DICC_SIZE (32)
|
||||
|
||||
#define MEMORY_AXI_SOFT_FLAG_ADDR (MEMORY_AXI_DICC_ADDR + MEMORY_AXI_DICC_SIZE)
|
||||
#define MEMORY_AXI_SOFT_FLAG_SIZE (256)
|
||||
|
||||
/* Thermal Flags */
|
||||
#define MEMORY_AXI_TEMP_PROTECT_ADDR (MEMORY_AXI_SOFT_FLAG_ADDR + MEMORY_AXI_SOFT_FLAG_SIZE)
|
||||
#define MEMORY_AXI_TEMP_PROTECT_SIZE (128)
|
||||
|
||||
/* CSHELL */
|
||||
#define MEMORY_AXI_USB_CSHELL_ADDR (MEMORY_AXI_TEMP_PROTECT_ADDR + MEMORY_AXI_TEMP_PROTECT_SIZE)
|
||||
#define MEMORY_AXI_USB_CSHELL_SIZE (4)
|
||||
|
||||
/* Uart and A/C Shell Switch Flags */
|
||||
#define MEMORY_AXI_UART_INOUT_ADDR (MEMORY_AXI_USB_CSHELL_ADDR + MEMORY_AXI_USB_CSHELL_SIZE)
|
||||
#define MEMORY_AXI_UART_INOUT_SIZE (4)
|
||||
|
||||
/* IFC Flags */
|
||||
#define MEMORY_AXI_IFC_ADDR (MEMORY_AXI_UART_INOUT_ADDR + MEMORY_AXI_UART_INOUT_SIZE)
|
||||
#define MEMORY_AXI_IFC_SIZE (32)
|
||||
|
||||
/* HIFI Data */
|
||||
#define MEMORY_AXI_HIFI_ADDR (MEMORY_AXI_IFC_ADDR + MEMORY_AXI_IFC_SIZE)
|
||||
#define MEMORY_AXI_HIFI_SIZE (32)
|
||||
|
||||
/* CONFIG Flags */
|
||||
#define MEMORY_AXI_CONFIG_ADDR (MEMORY_AXI_HIFI_ADDR + MEMORY_AXI_HIFI_SIZE)
|
||||
#define MEMORY_AXI_CONFIG_SIZE (32)
|
||||
|
||||
/* DDR Capacity Flags */
|
||||
#define MEMORY_AXI_DDR_CAPACITY_ADDR (MEMORY_AXI_CONFIG_ADDR + MEMORY_AXI_CONFIG_SIZE)
|
||||
#define MEMORY_AXI_DDR_CAPACITY_SIZE (4)
|
||||
|
||||
/* USB Shell Flags */
|
||||
#define MEMORY_AXI_USB_SHELL_FLAG_ADDR (MEMORY_AXI_DDR_CAPACITY_ADDR + MEMORY_AXI_DDR_CAPACITY_SIZE)
|
||||
#define MEMORY_AXI_USB_SHELL_FLAG_SIZE (4)
|
||||
|
||||
/* MCU WDT Switch Flag */
|
||||
#define MEMORY_AXI_MCU_WDT_FLAG_ADDR (MEMORY_AXI_USB_SHELL_FLAG_ADDR + MEMORY_AXI_USB_SHELL_FLAG_SIZE)
|
||||
#define MEMORY_AXI_MCU_WDT_FLAG_SIZE (4)
|
||||
|
||||
/* TLDSP Mailbox MNTN */
|
||||
#define SRAM_DSP_MNTN_INFO_ADDR (MEMORY_AXI_MCU_WDT_FLAG_ADDR + MEMORY_AXI_MCU_WDT_FLAG_SIZE)
|
||||
#define SRAM_DSP_MNTN_SIZE (32)
|
||||
|
||||
/* TLDSP ARM Mailbox Protect Flag */
|
||||
#define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR (SRAM_DSP_MNTN_INFO_ADDR + SRAM_DSP_MNTN_SIZE)
|
||||
#define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE (4)
|
||||
|
||||
/* RTT Sleep Flag */
|
||||
#define SRAM_RTT_SLEEP_FLAG_ADDR (SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR + SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE)
|
||||
#define SRAM_RTT_SLEEP_FLAG_SIZE (32)
|
||||
|
||||
/* LDSP Awake Flag */
|
||||
#define MEMORY_AXI_LDSP_AWAKE_ADDR (SRAM_RTT_SLEEP_FLAG_ADDR + SRAM_RTT_SLEEP_FLAG_SIZE)
|
||||
#define MEMORY_AXI_LDSP_AWAKE_SIZE (4)
|
||||
|
||||
#define NVUPDATE_SUCCESS 0x5555AAAA
|
||||
#define NVUPDATE_FAILURE 0xAAAA5555
|
||||
|
||||
/*
|
||||
* Low Power Mode Region
|
||||
*/
|
||||
#define PWRCTRL_ACPU_ASM_SPACE_ADDR (SRAM_PM_ADDR)
|
||||
#define PWRCTRL_ACPU_ASM_SPACE_SIZE (SRAM_PM_SIZE)
|
||||
|
||||
#define PWRCTRL_ACPU_ASM_MEM_BASE (PWRCTRL_ACPU_ASM_SPACE_ADDR)
|
||||
#define PWRCTRL_ACPU_ASM_MEM_SIZE (PWRCTRL_ACPU_ASM_SPACE_SIZE)
|
||||
#define PWRCTRL_ACPU_ASM_CODE_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0x200)
|
||||
#define PWRCTRL_ACPU_ASM_DATA_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0xE00)
|
||||
#define PWRCTRL_ACPU_ASM_DATA_SIZE (0xE00)
|
||||
|
||||
#define PWRCTRL_ACPU_ASM_D_C0_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE)
|
||||
#define PWRCTRL_ACPU_ASM_D_C0_MMU_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0)
|
||||
#define PWRCTRL_ACPU_ASM_D_ARM_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0x20)
|
||||
|
||||
#define PWRCTRL_ACPU_ASM_D_COMM_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE + 0x700)
|
||||
|
||||
#define PWRCTRL_ACPU_REBOOT (PWRCTRL_ACPU_ASM_D_COMM_ADDR)
|
||||
#define PWRCTRL_ACPU_REBOOT_SIZE (0x200)
|
||||
#define PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR (PWRCTRL_ACPU_REBOOT + PWRCTRL_ACPU_REBOOT_SIZE)
|
||||
#define PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE (4)
|
||||
#define PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR (PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR + PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE)
|
||||
#define PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE (4)
|
||||
#define EXCH_A_CORE_POWRCTRL_CONV_ADDR (PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR + PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE)
|
||||
#define EXCH_A_CORE_POWRCTRL_CONV_SIZE (4)
|
||||
|
||||
/*
|
||||
* Below region memory mapping is:
|
||||
* 4 + 12 + 16 + 28 + 28 + 16 + 28 + 12 + 24 + 20 + 64 +
|
||||
* 4 + 4 + 4 + 4 + 12 + 4 + 4 + 4 + 4 + 16 + 4 + 0x2BC +
|
||||
* 24 + 20 + 12 + 16
|
||||
*/
|
||||
|
||||
#define MEMORY_AXI_CPU_IDLE_ADDR (EXCH_A_CORE_POWRCTRL_CONV_ADDR + EXCH_A_CORE_POWRCTRL_CONV_SIZE)
|
||||
#define MEMORY_AXI_CPU_IDLE_SIZE (4)
|
||||
|
||||
#define MEMORY_AXI_CUR_FREQ_ADDR (MEMORY_AXI_CPU_IDLE_ADDR + MEMORY_AXI_CPU_IDLE_SIZE)
|
||||
#define MEMORY_AXI_CUR_FREQ_SIZE (12)
|
||||
|
||||
#define MEMORY_AXI_ACPU_FREQ_VOL_ADDR (MEMORY_AXI_CUR_FREQ_ADDR + MEMORY_AXI_CUR_FREQ_SIZE)
|
||||
#define MEMORY_AXI_ACPU_FREQ_VOL_SIZE (16 + 28 + 28)
|
||||
|
||||
#define MEMORY_AXI_DDR_FREQ_VOL_ADDR (MEMORY_AXI_ACPU_FREQ_VOL_ADDR + MEMORY_AXI_ACPU_FREQ_VOL_SIZE)
|
||||
#define MEMORY_AXI_DDR_FREQ_VOL_SIZE (16 + 28)
|
||||
|
||||
#define MEMORY_AXI_ACPU_FIQ_TEST_ADDR (MEMORY_AXI_DDR_FREQ_VOL_ADDR + MEMORY_AXI_DDR_FREQ_VOL_SIZE)
|
||||
#define MEMORY_AXI_ACPU_FIQ_TEST_SIZE (12)
|
||||
|
||||
#define MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_TEST_ADDR + MEMORY_AXI_ACPU_FIQ_TEST_SIZE)
|
||||
#define MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE (24)
|
||||
|
||||
#define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE)
|
||||
#define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE (20)
|
||||
|
||||
#define MEMORY_FREQDUMP_ADDR (MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE)
|
||||
#define MEMORY_FREQDUMP_SIZE (64)
|
||||
|
||||
#define MEMORY_AXI_CCPU_LOG_ADDR (MEMORY_FREQDUMP_ADDR + MEMORY_FREQDUMP_SIZE)
|
||||
#define MEMORY_AXI_CCPU_LOG_SIZE (4)
|
||||
|
||||
#define MEMORY_AXI_MCU_LOG_ADDR (MEMORY_AXI_CCPU_LOG_ADDR + MEMORY_AXI_CCPU_LOG_SIZE)
|
||||
#define MEMORY_AXI_MCU_LOG_SIZE (4)
|
||||
|
||||
#define MEMORY_AXI_SEC_CORE_BOOT_ADDR (MEMORY_AXI_MCU_LOG_ADDR + MEMORY_AXI_MCU_LOG_SIZE)
|
||||
#define MEMORY_AXI_SEC_CORE_BOOT_SIZE (4)
|
||||
|
||||
#define MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR (MEMORY_AXI_SEC_CORE_BOOT_ADDR + MEMORY_AXI_SEC_CORE_BOOT_SIZE)
|
||||
#define MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE (0x4)
|
||||
|
||||
#define POLICY_AREA_RESERVED (MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR + MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE)
|
||||
#define POLICY_AREA_RESERVED_SIZE (12)
|
||||
|
||||
#define DDR_POLICY_VALID_MAGIC (POLICY_AREA_RESERVED + POLICY_AREA_RESERVED_SIZE)
|
||||
#define DDR_POLICY_VALID_MAGIC_SIZE (4)
|
||||
|
||||
#define DDR_POLICY_MAX_NUM (DDR_POLICY_VALID_MAGIC + DDR_POLICY_VALID_MAGIC_SIZE)
|
||||
#define DDR_POLICY_MAX_NUM_SIZE (4)
|
||||
|
||||
#define DDR_POLICY_SUPPORT_NUM (DDR_POLICY_MAX_NUM + DDR_POLICY_MAX_NUM_SIZE)
|
||||
#define DDR_POLICY_SUPPORT_NUM_SIZE (4)
|
||||
|
||||
#define DDR_POLICY_CUR_POLICY (DDR_POLICY_SUPPORT_NUM + DDR_POLICY_SUPPORT_NUM_SIZE)
|
||||
#define DDR_POLICY_CUR_POLICY_SIZE (4)
|
||||
|
||||
#define ACPU_POLICY_VALID_MAGIC (DDR_POLICY_CUR_POLICY + DDR_POLICY_CUR_POLICY_SIZE)
|
||||
#define ACPU_POLICY_VALID_MAGIC_SIZE (4)
|
||||
|
||||
#define ACPU_POLICY_MAX_NUM (ACPU_POLICY_VALID_MAGIC + ACPU_POLICY_VALID_MAGIC_SIZE)
|
||||
#define ACPU_POLICY_MAX_NUM_SIZE (4)
|
||||
|
||||
#define ACPU_POLICY_SUPPORT_NUM (ACPU_POLICY_MAX_NUM + ACPU_POLICY_MAX_NUM_SIZE)
|
||||
#define ACPU_POLICY_SUPPORT_NUM_SIZE (4)
|
||||
|
||||
#define ACPU_POLICY_CUR_POLICY (ACPU_POLICY_SUPPORT_NUM + ACPU_POLICY_SUPPORT_NUM_SIZE)
|
||||
#define ACPU_POLICY_CUR_POLICY_SIZE (4)
|
||||
|
||||
#define LPDDR_OPTION_ADDR (ACPU_POLICY_CUR_POLICY + ACPU_POLICY_CUR_POLICY_SIZE)
|
||||
#define LPDDR_OPTION_SIZE (4)
|
||||
|
||||
#define MEMORY_AXI_DDR_DDL_ADDR (LPDDR_OPTION_ADDR + LPDDR_OPTION_SIZE)
|
||||
#define MEMORY_AXI_DDR_DDL_SIZE (0x2BC)
|
||||
|
||||
#define DDR_TEST_DFS_ADDR (MEMORY_AXI_DDR_DDL_ADDR + MEMORY_AXI_DDR_DDL_SIZE)
|
||||
#define DDR_TEST_DFS_ADDR_SIZE (4)
|
||||
|
||||
#define DDR_TEST_DFS_TIMES_ADDR (DDR_TEST_DFS_ADDR + DDR_TEST_DFS_ADDR_SIZE)
|
||||
#define DDR_TEST_DFS_TIMES_ADDR_SIZE (4)
|
||||
|
||||
#define DDR_TEST_QOS_ADDR (DDR_TEST_DFS_TIMES_ADDR + DDR_TEST_DFS_TIMES_ADDR_SIZE)
|
||||
#define DDR_TEST_QOS_ADDR_SIZE (4)
|
||||
|
||||
#define DDR_TEST_FUN_ADDR (DDR_TEST_QOS_ADDR + DDR_TEST_QOS_ADDR_SIZE)
|
||||
#define DDR_TEST_FUN_ADDR_SIZE (4)
|
||||
|
||||
#define BOARD_TYPE_ADDR (DDR_TEST_FUN_ADDR + DDR_TEST_FUN_ADDR_SIZE)
|
||||
#define BOARD_ADDR_SIZE (4)
|
||||
#define DDR_DFS_FREQ_ADDR (BOARD_TYPE_ADDR + BOARD_ADDR_SIZE)
|
||||
#define DDR_DFS_FREQ_SIZE (4)
|
||||
|
||||
#define DDR_PASR_ADDR (DDR_DFS_FREQ_ADDR + DDR_DFS_FREQ_SIZE)
|
||||
#define DDR_PASR_SIZE (20)
|
||||
|
||||
#define ACPU_DFS_FREQ_ADDR (DDR_PASR_ADDR + DDR_PASR_SIZE)
|
||||
#define ACPU_DFS_FREQ_ADDR_SIZE (12)
|
||||
|
||||
#define ACPU_CHIP_MAX_FREQ (ACPU_DFS_FREQ_ADDR + ACPU_DFS_FREQ_ADDR_SIZE)
|
||||
#define ACPU_CHIP_MAX_FREQ_SIZE (4)
|
||||
|
||||
#define MEMORY_MEDPLL_STATE_ADDR (ACPU_CHIP_MAX_FREQ + ACPU_CHIP_MAX_FREQ_SIZE)
|
||||
#define MEMORY_MEDPLL_STATE_SIZE (8)
|
||||
|
||||
#define MEMORY_CCPU_LOAD_FLAG_ADDR (MEMORY_MEDPLL_STATE_ADDR + MEMORY_MEDPLL_STATE_SIZE)
|
||||
#define MEMORY_CCPU_LOAD_FLAG_SIZE (4)
|
||||
|
||||
|
||||
#define ACPU_CORE_BITS_ADDR (MEMORY_CCPU_LOAD_FLAG_ADDR + MEMORY_CCPU_LOAD_FLAG_SIZE)
|
||||
#define ACPU_CORE_BITS_SIZE (4)
|
||||
|
||||
#define ACPU_CLUSTER_IDLE_ADDR (ACPU_CORE_BITS_ADDR + ACPU_CORE_BITS_SIZE)
|
||||
#define ACPU_CLUSTER_IDLE_SIZE (4)
|
||||
|
||||
#define ACPU_A53_FLAGS_ADDR (ACPU_CLUSTER_IDLE_ADDR + ACPU_CLUSTER_IDLE_SIZE)
|
||||
#define ACPU_A53_FLAGS_SIZE (4)
|
||||
|
||||
#define ACPU_POWER_STATE_QOS_ADDR (ACPU_A53_FLAGS_ADDR+ACPU_A53_FLAGS_SIZE)
|
||||
#define ACPU_POWER_STATE_QOS_SIZE (4)
|
||||
|
||||
#define ACPU_UNLOCK_CORE_FLAGS_ADDR (ACPU_POWER_STATE_QOS_ADDR+ACPU_POWER_STATE_QOS_SIZE)
|
||||
#define ACPU_UNLOCK_CORE_FLAGS_SIZE (8)
|
||||
|
||||
#define ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR (ACPU_UNLOCK_CORE_FLAGS_ADDR + ACPU_UNLOCK_CORE_FLAGS_SIZE)
|
||||
#define ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE (4)
|
||||
|
||||
#define ACPU_CORE_POWERDOWN_FLAGS_ADDR (ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR + ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE)
|
||||
#define ACPU_CORE_POWERDOWN_FLAGS_SIZE (4)
|
||||
|
||||
#define ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR (ACPU_CORE_POWERDOWN_FLAGS_ADDR + ACPU_CORE_POWERDOWN_FLAGS_SIZE)
|
||||
#define ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE (4)
|
||||
|
||||
#define ACPU_ARM64_FLAGA (ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR + ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE)
|
||||
#define ACPU_ARM64_FLAGA_SIZE (4)
|
||||
|
||||
#define ACPU_ARM64_FLAGB (ACPU_ARM64_FLAGA + ACPU_ARM64_FLAGA_SIZE)
|
||||
#define ACPU_ARM64_FLAGB_SIZE (4)
|
||||
|
||||
#define MCU_EXCEPTION_FLAGS_ADDR (ACPU_ARM64_FLAGB + ACPU_ARM64_FLAGB_SIZE)
|
||||
#define MCU_EXCEPTION_FLAGS_SIZE (4)
|
||||
|
||||
#define ACPU_MASTER_CORE_STATE_ADDR (MCU_EXCEPTION_FLAGS_ADDR + MCU_EXCEPTION_FLAGS_SIZE)
|
||||
#define ACPU_MASTER_CORE_STATE_SIZE (4)
|
||||
|
||||
#define PWRCTRL_AXI_RESERVED_ADDR (ACPU_MASTER_CORE_STATE_ADDR + ACPU_MASTER_CORE_STATE_SIZE)
|
||||
|
||||
#endif /* HISI_SRAM_MAP_H */
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_MACROS_S
|
||||
#define PLAT_MACROS_S
|
||||
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <hi6220.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
.section .rodata.gic_reg_name, "aS"
|
||||
gicc_regs:
|
||||
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
|
||||
gicd_pend_reg:
|
||||
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
|
||||
newline:
|
||||
.asciz "\n"
|
||||
spacer:
|
||||
.asciz ":\t\t0x"
|
||||
|
||||
.section .rodata.cci_reg_name, "aS"
|
||||
cci_iface_regs:
|
||||
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below macro prints out relevant GIC
|
||||
* registers whenever an unhandled exception is
|
||||
* taken in BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
mov_imm x16, PLAT_ARM_GICD_BASE
|
||||
mov_imm x17, PLAT_ARM_GICC_BASE
|
||||
|
||||
/* Load the gicc reg list to x6 */
|
||||
adr x6, gicc_regs
|
||||
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
|
||||
ldr w8, [x17, #GICC_HPPIR]
|
||||
ldr w9, [x17, #GICC_AHPPIR]
|
||||
ldr w10, [x17, #GICC_CTLR]
|
||||
/* Store to the crash buf and print to cosole */
|
||||
bl str_in_crash_buf_print
|
||||
|
||||
/* Print the GICD_ISPENDR regs */
|
||||
add x7, x16, #GICD_ISPENDR
|
||||
adr x4, gicd_pend_reg
|
||||
bl asm_print_str
|
||||
2:
|
||||
sub x4, x7, x16
|
||||
cmp x4, #0x280
|
||||
b.eq 1f
|
||||
bl asm_print_hex
|
||||
adr x4, spacer
|
||||
bl asm_print_str
|
||||
ldr x4, [x7], #8
|
||||
bl asm_print_hex
|
||||
adr x4, newline
|
||||
bl asm_print_str
|
||||
b 2b
|
||||
1:
|
||||
adr x6, cci_iface_regs
|
||||
/* Store in x7 the base address of the first interface */
|
||||
mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
|
||||
CCI400_SL_IFACE3_CLUSTER_IX))
|
||||
ldr w8, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store in x7 the base address of the second interface */
|
||||
mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
|
||||
CCI400_SL_IFACE4_CLUSTER_IX))
|
||||
ldr w9, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
.endm
|
||||
|
||||
#endif /* PLAT_MACROS_S */
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
#include <hikey_def.h>
|
||||
#include <hikey_layout.h> /* BL memory region sizes, etc */
|
||||
|
||||
/* Special value used to verify platform parameters from BL2 to BL3-1 */
|
||||
#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
|
||||
|
||||
/*
|
||||
* Generic platform constants
|
||||
*/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
|
||||
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
|
||||
|
||||
#define PLATFORM_CACHE_LINE_SIZE 64
|
||||
#define PLATFORM_CLUSTER_COUNT U(2)
|
||||
#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
|
||||
PLATFORM_CORE_COUNT_PER_CLUSTER)
|
||||
#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER_COUNT + U(1))
|
||||
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
|
||||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
/* eMMC RPMB and eMMC User Data */
|
||||
#define MAX_IO_BLOCK_DEVICES U(2)
|
||||
|
||||
/* GIC related constants (no GICR in GIC-400) */
|
||||
#define PLAT_ARM_GICD_BASE 0xF6801000
|
||||
#define PLAT_ARM_GICC_BASE 0xF6802000
|
||||
#define PLAT_ARM_GICH_BASE 0xF6804000
|
||||
#define PLAT_ARM_GICV_BASE 0xF6806000
|
||||
|
||||
/*
|
||||
* Platform specific page table and MMU setup constants
|
||||
*/
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
|
||||
#define MAX_XLAT_TABLES 3
|
||||
#endif
|
||||
|
||||
#ifdef IMAGE_BL31
|
||||
#define MAX_XLAT_TABLES 4
|
||||
#endif
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
#define MAX_XLAT_TABLES 4
|
||||
#endif
|
||||
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
/*
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
Reference in New Issue
Block a user