GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <services/el3_spmc_ffa_memory.h>
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#include <hi3660.h>
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#include <hisi_ipc.h>
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#include "hikey960_def.h"
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#include "hikey960_private.h"
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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static console_t console;
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/* fastboot serial number consumed by Kinibi SPD/LP for gpd.tee.deviceID. */
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uint64_t fastboot_serno;
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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static const interrupt_prop_t g0_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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const gicv2_driver_data_t hikey960_gic_data = {
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.gicd_base = GICD_REG_BASE,
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.gicc_base = GICC_REG_BASE,
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.interrupt_props = g0_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
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};
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static const int cci_map[] = {
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CCI400_SL_IFACE3_CLUSTER_IX,
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CCI400_SL_IFACE4_CLUSTER_IX
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};
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc)
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return next_image_info;
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return NULL;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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unsigned int id, uart_base;
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void *from_bl2;
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plat_params_from_bl2_t *plat_params_from_bl2 = (plat_params_from_bl2_t *) arg1;
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from_bl2 = (void *) arg0;
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generic_delay_timer_init();
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hikey960_read_boardid(&id);
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if (id == 5300)
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uart_base = PL011_UART5_BASE;
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else
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uart_base = PL011_UART6_BASE;
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/* Initialize the console to provide early debug support */
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console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
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PL011_BAUDRATE, &console);
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/* Initialize CCI driver */
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cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map));
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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/* Fastboot serial number passed from BL2 as a platform parameter */
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fastboot_serno = plat_params_from_bl2->fastboot_serno;
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INFO("BL31: fastboot_serno %lx\n", fastboot_serno);
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/*
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* Check params passed from BL2 should not be NULL,
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*/
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 and BL32 (if present), entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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while (bl_params) {
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if (bl_params->image_id == BL32_IMAGE_ID)
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bl32_ep_info = *bl_params->ep_info;
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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if (bl33_ep_info.pc == 0)
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panic();
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}
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void bl31_plat_arch_setup(void)
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{
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#if SPMC_AT_EL3
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mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE);
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#endif
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hikey960_init_mmu_el3(BL31_BASE,
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BL31_LIMIT - BL31_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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}
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static void hikey960_edma_init(void)
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{
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int i;
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uint32_t non_secure;
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non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
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mmio_write_32(EDMAC_SEC_CTRL, non_secure);
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/* Channel 0 is reserved for LPM3, keep secure */
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for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) {
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mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
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}
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}
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static void hikey960_iomcu_dma_init(void)
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{
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int i;
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uint32_t non_secure;
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non_secure = IOMCU_DMAC_SEC_CTRL_INTR_SEC | IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC;
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mmio_write_32(IOMCU_DMAC_SEC_CTRL, non_secure);
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/* channels 0-3 are reserved */
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for (i = 4; i < IOMCU_DMAC_CHANNEL_NUMS; i++) {
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mmio_write_32(IOMCU_DMAC_AXI_CONF(i), IOMCU_DMAC_AXI_CONF_ARPROT_NS |
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IOMCU_DMAC_AXI_CONF_AWPROT_NS);
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}
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}
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#if SPMC_AT_EL3
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/*
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* On the hikey960 platform when using the EL3 SPMC implementation allocate the
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* datastore for tracking shared memory descriptors in the RAM2 DRAM section
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* to ensure sufficient storage can be allocated.
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* Provide an implementation of the accessor method to allow the datastore
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* details to be retrieved by the SPMC.
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* The SPMC will take care of initializing the memory region.
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*/
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#define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024)
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__section("ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE];
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int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
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{
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*datastore = plat_spmc_shmem_datastore;
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*size = SPMC_SHARED_MEMORY_OBJ_SIZE;
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return 0;
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}
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/*
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* Add dummy implementations of memory management related platform hooks.
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* These can be used to implement platform specific functionality to support
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* a memory sharing/lending operation.
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*
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* Note: The hooks must be located as part of the initial share request and
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* final reclaim to prevent order dependencies with operations that may take
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* place in the normal world without visibility of the SPMC.
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*/
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int plat_spmc_shmem_begin(struct ffa_mtd *desc)
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{
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return 0;
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}
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int plat_spmc_shmem_reclaim(struct ffa_mtd *desc)
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{
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return 0;
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}
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#endif
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void bl31_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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gicv2_driver_init(&hikey960_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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hikey960_edma_init();
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hikey960_iomcu_dma_init();
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hikey960_gpio_init();
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hisi_ipc_init();
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}
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#ifdef SPD_none
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static uint64_t hikey_debug_fiq_handler(uint32_t id,
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uint32_t flags,
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void *handle,
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void *cookie)
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{
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int intr, intr_raw;
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/* Acknowledge interrupt */
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intr_raw = plat_ic_acknowledge_interrupt();
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intr = plat_ic_get_interrupt_id(intr_raw);
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ERROR("Invalid interrupt: intr=%d\n", intr);
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console_flush();
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panic();
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return 0;
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}
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#endif
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void bl31_plat_runtime_setup(void)
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{
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#ifdef SPD_none
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uint32_t flags;
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int32_t rc;
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flags = 0;
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set_interrupt_rm_flag(flags, NON_SECURE);
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rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
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hikey_debug_fiq_handler,
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flags);
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if (rc != 0)
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panic();
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#endif
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}
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