GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HI3660_H
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#define HI3660_H
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#include <hi3660_crg.h>
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#include <hi3660_hkadc.h>
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#include <hi3660_mem_map.h>
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#define ASP_CFG_REG_BASE 0xE804E000
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#define ASP_CFG_MMBUF_CTRL_REG (ASP_CFG_REG_BASE + 0x148)
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#define LP_RAM_BASE 0xFFF50000
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#define SCTRL_REG_BASE 0xFFF0A000
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#define SCTRL_CONTROL_REG (SCTRL_REG_BASE + 0x000)
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#define SCTRL_CONTROL_SYS_MODE(x) (((x) & 0xf) << 3)
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#define SCTRL_CONTROL_SYS_MODE_NORMAL ((1 << 2) << 3)
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#define SCTRL_CONTROL_SYS_MODE_SLOW ((1 << 1) << 3)
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#define SCTRL_CONTROL_SYS_MODE_MASK (0xf << 3)
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#define SCTRL_CONTROL_MODE_CTRL_NORMAL (1 << 2)
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#define SCTRL_CONTROL_MODE_CTRL_SLOW (1 << 1)
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#define SCTRL_CONTROL_MODE_CTRL_MASK 0x7
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#define SCTRL_SCSYSSTAT_REG (SCTRL_REG_BASE + 0x004)
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#define SCTRL_DEEPSLEEPED_REG (SCTRL_REG_BASE + 0x008)
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#define SCTRL_EFUSE_USB_MASK (1 << 30)
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#define SCTRL_EFUSE_USB_PLL (1 << 30)
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#define SCTRL_EFUSE_USB_ABB (0 << 30)
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#define SCTRL_EFUSE_UFS_MASK (3 << 6)
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#define SCTRL_EFUSE_UFS_PLL (1 << 6)
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#define SCTRL_EFUSE_UFS_ABB (0 << 6)
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#define SCTRL_SCISOEN_REG (SCTRL_REG_BASE + 0x040)
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#define SCTRL_SCISODIS_REG (SCTRL_REG_BASE + 0x044)
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#define SCISO_MMBUFISO (1 << 3)
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#define SCTRL_SCPWREN_REG (SCTRL_REG_BASE + 0x060)
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#define SCPWREN_MMBUFPWREN (1 << 3)
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#define SCTRL_PLL_CTRL0_REG (SCTRL_REG_BASE + 0x100)
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#define SCTRL_PLL0_POSTDIV2(x) (((x) & 0x7) << 23)
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#define SCTRL_PLL0_POSTDIV1(x) (((x) & 0x7) << 20)
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#define SCTRL_PLL0_FBDIV(x) (((x) & 0xfff) << 8)
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#define SCTRL_PLL0_REFDIV(x) (((x) & 0x3f) << 2)
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#define SCTRL_PLL0_EN (1 << 0)
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#define SCTRL_PLL_CTRL1_REG (SCTRL_REG_BASE + 0x104)
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#define SCTRL_PLL0_CLK_NO_GATE (1 << 26)
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#define SCTRL_PLL0_CFG_VLD (1 << 25)
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#define SCTRL_PLL0_FRACDIV(x) ((x) & 0xFFFFFF)
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#define SCTRL_PLL_STAT_REG (SCTRL_REG_BASE + 0x10C)
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#define SCTRL_PLL0_STAT (1 << 0)
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#define SCTRL_SCPEREN0_REG (SCTRL_REG_BASE + 0x160)
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#define SCTRL_SCPERDIS0_REG (SCTRL_REG_BASE + 0x164)
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#define SCTRL_SCPERSTAT0_REG (SCTRL_REG_BASE + 0x168)
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#define SCTRL_SCPEREN1_REG (SCTRL_REG_BASE + 0x170)
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#define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174)
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#define SCTRL_SCPEREN1_REG (SCTRL_REG_BASE + 0x170)
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#define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174)
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#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS (1u << 31)
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#define SCPEREN_GT_PCLK_MMBUFCFG (1 << 25)
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#define SCPEREN_GT_PCLK_MMBUF (1 << 23)
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#define SCPEREN_GT_ACLK_MMBUF (1 << 22)
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#define SCPEREN_GT_CLK_NOC_AOBUS2MMBUF (1 << 6)
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#define SCTRL_SCPEREN2_REG (SCTRL_REG_BASE + 0x190)
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#define SCTRL_SCPERDIS2_REG (SCTRL_REG_BASE + 0x194)
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#define SCTRL_SCPERSTAT2_REG (SCTRL_REG_BASE + 0x198)
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#define SCTRL_SCPERRSTEN0_REG (SCTRL_REG_BASE + 0x200)
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#define SCTRL_SCPERRSTDIS0_REG (SCTRL_REG_BASE + 0x204)
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#define SCTRL_SCPERRSTSTAT0_REG (SCTRL_REG_BASE + 0x208)
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#define SCTRL_SCPERRSTEN1_REG (SCTRL_REG_BASE + 0x20C)
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#define SCTRL_SCPERRSTDIS1_REG (SCTRL_REG_BASE + 0x210)
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#define SCTRL_SCPERRSTSTAT1_REG (SCTRL_REG_BASE + 0x214)
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#define IP_RST_MMBUFCFG (1 << 12)
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#define IP_RST_MMBUF (1 << 11)
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#define SCTRL_SCPERRSTEN2_REG (SCTRL_REG_BASE + 0x218)
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#define SCTRL_SCPERRSTDIS2_REG (SCTRL_REG_BASE + 0x21C)
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#define SCTRL_SCPERRSTSTAT2_REG (SCTRL_REG_BASE + 0x220)
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#define SCTRL_SCCLKDIV2_REG (SCTRL_REG_BASE + 0x258)
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#define SEL_CLK_MMBUF_MASK (0x3 << 8)
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#define SEL_CLK_MMBUF_PLL0 (0x3 << 8)
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#define SCCLKDIV2_GT_PCLK_MMBUF (1 << 7)
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#define SCTRL_SCCLKDIV4_REG (SCTRL_REG_BASE + 0x260)
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#define GT_MMBUF_SYS (1 << 13)
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#define GT_MMBUF_FLL (1 << 12)
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#define GT_PLL_CLK_MMBUF (1 << 11)
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#define SCTRL_SCCLKDIV6_REG (SCTRL_REG_BASE + 0x268)
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#define SCTRL_SCPERCTRL7_REG (SCTRL_REG_BASE + 0x31C)
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#define SCTRL_SCPERSTAT6_REG (SCTRL_REG_BASE + 0x378)
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#define SCTRL_SCINNERSTAT_REG (SCTRL_REG_BASE + 0x3A0)
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#define EMMC_UFS_SEL (1 << 15)
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#define SCTRL_BAK_DATA0_REG (SCTRL_REG_BASE + 0x40C)
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#define SCTRL_BAK_DATA4_REG (SCTRL_REG_BASE + 0x41C)
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#define SCTRL_LPMCU_CLKEN_REG (SCTRL_REG_BASE + 0x480)
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#define SCTRL_LPMCU_CLKDIS_REG (SCTRL_REG_BASE + 0x484)
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#define SCTRL_LPMCU_RSTEN_REG (SCTRL_REG_BASE + 0x500)
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#define SCTRL_LPMCU_RSTDIS_REG (SCTRL_REG_BASE + 0x504)
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#define DDRC_SOFT_BIT (1 << 6)
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#define DDRC_CLK_BIT (1 << 5)
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#define SCTRL_SCPEREN0_SEC_REG (SCTRL_REG_BASE + 0x900)
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#define SCTRL_SCPERDIS0_SEC_REG (SCTRL_REG_BASE + 0x904)
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#define MMBUF_SEC_CTRL_MASK (0xfff << 20)
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#define MMBUF_SEC_CTRL(x) (((x) & 0xfff) << 20)
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#define SCTRL_PERRSTEN1_SEC_REG (SCTRL_REG_BASE + 0xA50)
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#define SCTRL_PERRSTDIS1_SEC_REG (SCTRL_REG_BASE + 0xA54)
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#define SCTRL_PERRSTSTAT1_SEC_REG (SCTRL_REG_BASE + 0xA58)
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#define RST_ASP_SUBSYS_BIT (1 << 0)
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#define SCTRL_PERRSTEN2_SEC_REG (SCTRL_REG_BASE + 0xB50)
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#define SCTRL_PERRSTDIS2_SEC_REG (SCTRL_REG_BASE + 0xB54)
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#define SCTRL_PERRSTSTAT2_SEC_REG (SCTRL_REG_BASE + 0xB58)
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#define SCTRL_HISEECLKDIV_REG (SCTRL_REG_BASE + 0xC28)
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#define SC_SEL_HISEE_PLL_MASK (1 << 4)
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#define SC_SEL_HISEE_PLL0 (1 << 4)
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#define SC_SEL_HISEE_PLL2 (0 << 4)
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#define SC_DIV_HISEE_PLL_MASK (7 << 16)
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#define SC_DIV_HISEE_PLL(x) ((x) & 0x7)
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#define SCTRL_SCSOCID0_REG (SCTRL_REG_BASE + 0xE00)
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#define PMC_REG_BASE 0xFFF31000
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#define PMC_PPLL1_CTRL0_REG (PMC_REG_BASE + 0x038)
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#define PMC_PPLL1_CTRL1_REG (PMC_REG_BASE + 0x03C)
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#define PMC_PPLL2_CTRL0_REG (PMC_REG_BASE + 0x040)
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#define PMC_PPLL2_CTRL1_REG (PMC_REG_BASE + 0x044)
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#define PMC_PPLL3_CTRL0_REG (PMC_REG_BASE + 0x048)
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#define PMC_PPLL3_CTRL1_REG (PMC_REG_BASE + 0x04C)
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#define PPLLx_LOCK (1 << 26)
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#define PPLLx_WITHOUT_CLK_GATE (1 << 26)
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#define PPLLx_CFG_VLD (1 << 25)
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#define PPLLx_INT_MOD (1 << 24)
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#define PPLLx_POSTDIV2_MASK (0x7 << 23)
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#define PPLLx_POSTDIV2(x) (((x) & 0x7) << 23)
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#define PPLLx_POSTDIV1_MASK (0x7 << 20)
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#define PPLLx_POSTDIV1(x) (((x) & 0x7) << 20)
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#define PPLLx_FRACDIV_MASK (0x00FFFFFF)
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#define PPLLx_FRACDIV(x) ((x) & 0x00FFFFFF)
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#define PPLLx_FBDIV_MASK (0xfff << 8)
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#define PPLLx_FBDIV(x) (((x) & 0xfff) << 8)
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#define PPLLx_REFDIV_MASK (0x3f << 2)
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#define PPLLx_REFDIV(x) (((x) & 0x3f) << 2)
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#define PPLLx_BP (1 << 1)
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#define PPLLx_EN (1 << 0)
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#define PMC_DDRLP_CTRL_REG (PMC_REG_BASE + 0x30C)
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#define DDRC_CSYSREQ_CFG(x) ((x) & 0xF)
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#define PMC_NOC_POWER_IDLEREQ_REG (PMC_REG_BASE + 0x380)
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#define PMC_NOC_POWER_IDLEREQ_IVP (1 << 14)
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#define PMC_NOC_POWER_IDLEREQ_DSS (1 << 13)
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#define PMC_NOC_POWER_IDLEREQ_VENC (1 << 11)
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#define PMC_NOC_POWER_IDLEREQ_VDEC (1 << 10)
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#define PMC_NOC_POWER_IDLEREQ_ISP (1 << 5)
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#define PMC_NOC_POWER_IDLEREQ_VCODEC (1 << 4)
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#define DDRPHY_BYPASS_MODE (1 << 0)
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#define PMC_NOC_POWER_IDLEACK_REG (PMC_REG_BASE + 0x384)
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#define PMC_NOC_POWER_IDLE_REG (PMC_REG_BASE + 0x388)
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#define PMU_SSI0_REG_BASE 0xFFF34000
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#define PMU_SSI0_LDO8_CTRL0_REG (PMU_SSI0_REG_BASE + (0x68 << 2))
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#define LDO8_CTRL0_EN_1_8V 0x02
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#define PMU_SSI0_CLK_TOP_CTRL7_REG (PMU_SSI0_REG_BASE + (0x10C << 2))
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#define NP_XO_ABB_DIG (1 << 1)
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#define LP_CONFIG_REG_BASE 0xFFF3F000
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#define DMAC_BASE 0xFDF30000
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#define CCI400_REG_BASE 0xE8100000
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#define CCI400_SL_IFACE3_CLUSTER_IX 0
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#define CCI400_SL_IFACE4_CLUSTER_IX 1
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#define GICD_REG_BASE 0xE82B1000
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#define GICC_REG_BASE 0xE82B2000
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/*
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* GIC400 interrupt handling related constants
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*/
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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#define IRQ_SEC_SGI_8 16
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#define IPC_REG_BASE 0xE896A000
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#define IPC_BASE (IPC_REG_BASE)
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#define IOMG_REG_BASE 0xE896C000
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/* GPIO46: HUB 3.3V enable. active low */
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#define IOMG_044_REG (IOMG_REG_BASE + 0x0B0)
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#define IOMG_UART5_RX_REG (IOMG_REG_BASE + 0x0BC)
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#define IOMG_UART5_TX_REG (IOMG_REG_BASE + 0x0C0)
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#define IOCG_REG_BASE 0xE896C800
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/* GPIO005: PMIC SSI. (2 << 4) */
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#define IOCG_006_REG (IOCG_REG_BASE + 0x018)
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#define TIMER9_REG_BASE 0xE8A00000
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#define WDT0_REG_BASE 0xE8A06000
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#define WDT1_REG_BASE 0xE8A07000
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#define WDT_CONTROL_OFFSET 0x008
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#define WDT_LOCK_OFFSET 0xC00
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#define WDT_UNLOCK 0x1ACCE551
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#define WDT_LOCKED 1
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#define PCTRL_REG_BASE 0xE8A09000
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#define PCTRL_PERI_CTRL3_REG (PCTRL_REG_BASE + 0x010)
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#define PCTRL_PERI_CTRL24_REG (PCTRL_REG_BASE + 0x064)
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#define GPIO0_BASE UL(0xE8A0B000)
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#define GPIO1_BASE UL(0xE8A0C000)
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#define GPIO2_BASE UL(0xE8A0D000)
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#define GPIO3_BASE UL(0xE8A0E000)
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#define GPIO4_BASE UL(0xE8A0F000)
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#define GPIO5_BASE UL(0xE8A10000)
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#define GPIO6_BASE UL(0xE8A11000)
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#define GPIO7_BASE UL(0xE8A12000)
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#define GPIO8_BASE UL(0xE8A13000)
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#define GPIO9_BASE UL(0xE8A14000)
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#define GPIO10_BASE UL(0xE8A15000)
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#define GPIO11_BASE UL(0xE8A16000)
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#define GPIO12_BASE UL(0xE8A17000)
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#define GPIO13_BASE UL(0xE8A18000)
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#define GPIO14_BASE UL(0xE8A19000)
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#define GPIO15_BASE UL(0xE8A1A000)
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#define GPIO16_BASE UL(0xE8A1B000)
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#define GPIO17_BASE UL(0xE8A1C000)
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#define GPIO20_BASE UL(0xE8A1F000)
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#define GPIO21_BASE UL(0xE8A20000)
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#define GPIO22_BASE UL(0xFFF0B000)
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#define GPIO23_BASE UL(0xFFF0C000)
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#define GPIO24_BASE UL(0xFFF0D000)
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#define GPIO25_BASE UL(0xFFF0E000)
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#define GPIO26_BASE UL(0xFFF0F000)
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#define GPIO27_BASE UL(0xFFF10000)
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#define GPIO28_BASE UL(0xFFF1D000)
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#define TZC_REG_BASE 0xE8A21000
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#define TZC_STAT0_REG (TZC_REG_BASE + 0x800)
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#define TZC_EN0_REG (TZC_REG_BASE + 0x804)
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#define TZC_DIS0_REG (TZC_REG_BASE + 0x808)
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#define TZC_STAT1_REG (TZC_REG_BASE + 0x80C)
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#define TZC_EN1_REG (TZC_REG_BASE + 0x810)
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#define TZC_DIS1_REG (TZC_REG_BASE + 0x814)
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#define TZC_STAT2_REG (TZC_REG_BASE + 0x818)
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#define TZC_EN2_REG (TZC_REG_BASE + 0x81C)
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#define TZC_DIS2_REG (TZC_REG_BASE + 0x820)
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#define TZC_STAT3_REG (TZC_REG_BASE + 0x824)
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#define TZC_EN3_REG (TZC_REG_BASE + 0x828)
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#define TZC_DIS3_REG (TZC_REG_BASE + 0x82C)
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#define TZC_STAT4_REG (TZC_REG_BASE + 0x830)
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#define TZC_EN4_REG (TZC_REG_BASE + 0x834)
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#define TZC_DIS4_REG (TZC_REG_BASE + 0x838)
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#define TZC_STAT5_REG (TZC_REG_BASE + 0x83C)
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#define TZC_EN5_REG (TZC_REG_BASE + 0x840)
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#define TZC_DIS5_REG (TZC_REG_BASE + 0x844)
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#define TZC_STAT6_REG (TZC_REG_BASE + 0x848)
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#define TZC_EN6_REG (TZC_REG_BASE + 0x84C)
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#define TZC_DIS6_REG (TZC_REG_BASE + 0x850)
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#define TZC_STAT7_REG (TZC_REG_BASE + 0x854)
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#define TZC_EN7_REG (TZC_REG_BASE + 0x858)
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#define TZC_DIS7_REG (TZC_REG_BASE + 0x85C)
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#define TZC_STAT8_REG (TZC_REG_BASE + 0x860)
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#define TZC_EN8_REG (TZC_REG_BASE + 0x864)
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#define TZC_DIS8_REG (TZC_REG_BASE + 0x868)
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#define MMBUF_BASE 0xEA800000
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#define ACPU_DMCPACK0_BASE 0xEA900000
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#define ACPU_DMCPACK1_BASE 0xEA920000
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#define ACPU_DMCPACK2_BASE 0xEA940000
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#define ACPU_DMCPACK3_BASE 0xEA960000
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#define UART5_REG_BASE 0xFDF05000
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#define USB3OTG_REG_BASE 0xFF100000
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#define UFS_REG_BASE 0xFF3B0000
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#define UFS_SYS_REG_BASE 0xFF3B1000
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#define UFS_SYS_PSW_POWER_CTRL_REG (UFS_SYS_REG_BASE + 0x004)
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#define UFS_SYS_PHY_ISO_EN_REG (UFS_SYS_REG_BASE + 0x008)
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#define UFS_SYS_HC_LP_CTRL_REG (UFS_SYS_REG_BASE + 0x00C)
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#define UFS_SYS_PHY_CLK_CTRL_REG (UFS_SYS_REG_BASE + 0x010)
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#define UFS_SYS_PSW_CLK_CTRL_REG (UFS_SYS_REG_BASE + 0x014)
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#define UFS_SYS_CLOCK_GATE_BYPASS_REG (UFS_SYS_REG_BASE + 0x018)
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#define UFS_SYS_RESET_CTRL_EN_REG (UFS_SYS_REG_BASE + 0x01C)
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#define UFS_SYS_MONITOR_HH_REG (UFS_SYS_REG_BASE + 0x03C)
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#define UFS_SYS_UFS_SYSCTRL_REG (UFS_SYS_REG_BASE + 0x05C)
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#define UFS_SYS_UFS_DEVICE_RESET_CTRL_REG (UFS_SYS_REG_BASE + 0x060)
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#define UFS_SYS_UFS_APB_ADDR_MASK_REG (UFS_SYS_REG_BASE + 0x064)
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#define BIT_UFS_PSW_ISO_CTRL (1 << 16)
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#define BIT_UFS_PSW_MTCMOS_EN (1 << 0)
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#define BIT_UFS_REFCLK_ISO_EN (1 << 16)
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#define BIT_UFS_PHY_ISO_CTRL (1 << 0)
|
||||
#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16)
|
||||
#define BIT_SYSCTRL_PWR_READY (1 << 8)
|
||||
#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24)
|
||||
#define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8)
|
||||
#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF)
|
||||
#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4)
|
||||
#define MASK_UFS_CLK_GATE_BYPASS (0x3F)
|
||||
#define BIT_SYSCTRL_LP_RESET_N (1 << 0)
|
||||
#define BIT_UFS_REFCLK_SRC_SE1 (1 << 0)
|
||||
#define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16)
|
||||
#define MASK_UFS_DEVICE_RESET (1 << 16)
|
||||
#define BIT_UFS_DEVICE_RESET (1 << 0)
|
||||
|
||||
#define GPIO18_BASE UL(0xFF3B4000)
|
||||
#define GPIO19_BASE UL(0xFF3B5000)
|
||||
|
||||
#define IOMG_FIX_REG_BASE 0xFF3B6000
|
||||
|
||||
/* GPIO150: LED */
|
||||
#define IOMG_FIX_006_REG (IOMG_FIX_REG_BASE + 0x018)
|
||||
/* GPIO151: LED */
|
||||
#define IOMG_FIX_007_REG (IOMG_FIX_REG_BASE + 0x01C)
|
||||
|
||||
#define IOMG_AO_REG_BASE 0xFFF11000
|
||||
|
||||
/* GPIO189: LED */
|
||||
#define IOMG_AO_011_REG (IOMG_AO_REG_BASE + 0x02C)
|
||||
/* GPIO190: LED */
|
||||
#define IOMG_AO_012_REG (IOMG_AO_REG_BASE + 0x030)
|
||||
/* GPIO202: type C enable. active low */
|
||||
#define IOMG_AO_023_REG (IOMG_AO_REG_BASE + 0x05C)
|
||||
/* GPIO206: USB switch. active low */
|
||||
#define IOMG_AO_026_REG (IOMG_AO_REG_BASE + 0x068)
|
||||
/* GPIO219: PD interrupt. pull up */
|
||||
#define IOMG_AO_039_REG (IOMG_AO_REG_BASE + 0x09C)
|
||||
/* GPIO213: PCIE_CLKREQ_N */
|
||||
#define IOMG_AO_033_REG (IOMG_AO_REG_BASE + 0x084)
|
||||
|
||||
#define IOCG_AO_REG_BASE 0xFFF1187C
|
||||
/* GPIO219: PD interrupt. pull up */
|
||||
#define IOCG_AO_043_REG (IOCG_AO_REG_BASE + 0x030)
|
||||
|
||||
#define EDMAC_BASE 0xfdf30000
|
||||
#define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694)
|
||||
#define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6))
|
||||
#define EDMAC_SEC_CTRL_INTR_SEC (1 << 1)
|
||||
#define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0)
|
||||
#define EDMAC_CHANNEL_NUMS 16
|
||||
|
||||
#define IOMCU_DMAC_BASE 0xffd77000
|
||||
#define IOMCU_DMAC_SEC_CTRL (IOMCU_DMAC_BASE + 0x694)
|
||||
#define IOMCU_DMAC_AXI_CONF(x) (IOMCU_DMAC_BASE + 0x820 + ((x) << 6))
|
||||
#define IOMCU_DMAC_AXI_CONF_ARPROT_NS (1 << 6)
|
||||
#define IOMCU_DMAC_AXI_CONF_AWPROT_NS (1 << 18)
|
||||
#define IOMCU_DMAC_SEC_CTRL_INTR_SEC (1 << 1)
|
||||
#define IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC (1 << 0)
|
||||
#define IOMCU_DMAC_CHANNEL_NUMS 8
|
||||
|
||||
#endif /* HI3660_H */
|
||||
+179
@@ -0,0 +1,179 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef HI3660_CRG_H
|
||||
#define HI3660_CRG_H
|
||||
|
||||
#define CRG_REG_BASE 0xFFF35000
|
||||
|
||||
#define CRG_PEREN0_REG (CRG_REG_BASE + 0x000)
|
||||
#define CRG_PERDIS0_REG (CRG_REG_BASE + 0x004)
|
||||
#define CRG_PERSTAT0_REG (CRG_REG_BASE + 0x008)
|
||||
#define PEREN0_GT_CLK_AOMM (1U << 31)
|
||||
|
||||
#define CRG_PEREN1_REG (CRG_REG_BASE + 0x010)
|
||||
#define CRG_PERDIS1_REG (CRG_REG_BASE + 0x014)
|
||||
#define CRG_PERSTAT1_REG (CRG_REG_BASE + 0x018)
|
||||
#define CRG_PEREN2_REG (CRG_REG_BASE + 0x020)
|
||||
#define CRG_PERDIS2_REG (CRG_REG_BASE + 0x024)
|
||||
#define CRG_PERSTAT2_REG (CRG_REG_BASE + 0x028)
|
||||
#define PEREN2_HKADCSSI (1 << 24)
|
||||
|
||||
#define CRG_PEREN3_REG (CRG_REG_BASE + 0x030)
|
||||
#define CRG_PERDIS3_REG (CRG_REG_BASE + 0x034)
|
||||
|
||||
#define CRG_PEREN4_REG (CRG_REG_BASE + 0x040)
|
||||
#define CRG_PERDIS4_REG (CRG_REG_BASE + 0x044)
|
||||
#define CRG_PERCLKEN4_REG (CRG_REG_BASE + 0x048)
|
||||
#define CRG_PERSTAT4_REG (CRG_REG_BASE + 0x04C)
|
||||
#define GT_ACLK_USB3OTG (1 << 1)
|
||||
#define GT_CLK_USB3OTG_REF (1 << 0)
|
||||
|
||||
#define CRG_PEREN5_REG (CRG_REG_BASE + 0x050)
|
||||
#define CRG_PERDIS5_REG (CRG_REG_BASE + 0x054)
|
||||
#define CRG_PERSTAT5_REG (CRG_REG_BASE + 0x058)
|
||||
#define CRG_PERRSTEN0_REG (CRG_REG_BASE + 0x060)
|
||||
#define CRG_PERRSTDIS0_REG (CRG_REG_BASE + 0x064)
|
||||
#define CRG_PERRSTSTAT0_REG (CRG_REG_BASE + 0x068)
|
||||
#define CRG_PERRSTEN1_REG (CRG_REG_BASE + 0x06C)
|
||||
#define CRG_PERRSTDIS1_REG (CRG_REG_BASE + 0x070)
|
||||
#define CRG_PERRSTSTAT1_REG (CRG_REG_BASE + 0x074)
|
||||
#define CRG_PERRSTEN2_REG (CRG_REG_BASE + 0x078)
|
||||
#define CRG_PERRSTDIS2_REG (CRG_REG_BASE + 0x07C)
|
||||
#define CRG_PERRSTSTAT2_REG (CRG_REG_BASE + 0x080)
|
||||
#define PERRSTEN2_HKADCSSI (1 << 24)
|
||||
|
||||
#define CRG_PERRSTEN3_REG (CRG_REG_BASE + 0x084)
|
||||
#define CRG_PERRSTDIS3_REG (CRG_REG_BASE + 0x088)
|
||||
#define CRG_PERRSTSTAT3_REG (CRG_REG_BASE + 0x08C)
|
||||
#define CRG_PERRSTEN4_REG (CRG_REG_BASE + 0x090)
|
||||
#define CRG_PERRSTDIS4_REG (CRG_REG_BASE + 0x094)
|
||||
#define CRG_PERRSTSTAT4_REG (CRG_REG_BASE + 0x098)
|
||||
#define IP_RST_USB3OTG_MUX (1 << 8)
|
||||
#define IP_RST_USB3OTG_AHBIF (1 << 7)
|
||||
#define IP_RST_USB3OTG_32K (1 << 6)
|
||||
#define IP_RST_USB3OTG (1 << 5)
|
||||
#define IP_RST_USB3OTGPHY_POR (1 << 3)
|
||||
|
||||
#define CRG_PERRSTEN5_REG (CRG_REG_BASE + 0x09C)
|
||||
#define CRG_PERRSTDIS5_REG (CRG_REG_BASE + 0x0A0)
|
||||
#define CRG_PERRSTSTAT5_REG (CRG_REG_BASE + 0x0A4)
|
||||
|
||||
/* bit fields in CRG_PERI */
|
||||
#define PERI_PCLK_PCTRL_BIT (1U << 31)
|
||||
#define PERI_TIMER12_BIT (1 << 25)
|
||||
#define PERI_TIMER11_BIT (1 << 24)
|
||||
#define PERI_TIMER10_BIT (1 << 23)
|
||||
#define PERI_TIMER9_BIT (1 << 22)
|
||||
#define PERI_UART5_BIT (1 << 15)
|
||||
#define PERI_UFS_BIT (1 << 12)
|
||||
#define PERI_ARST_UFS_BIT (1 << 7)
|
||||
#define PERI_PPLL2_EN_CPU (1 << 3)
|
||||
#define PERI_PWM_BIT (1 << 0)
|
||||
#define PERI_DDRC_BIT (1 << 0)
|
||||
#define PERI_DDRC_D_BIT (1 << 4)
|
||||
#define PERI_DDRC_C_BIT (1 << 3)
|
||||
#define PERI_DDRC_B_BIT (1 << 2)
|
||||
#define PERI_DDRC_A_BIT (1 << 1)
|
||||
#define PERI_DDRC_DMUX_BIT (1 << 0)
|
||||
|
||||
#define CRG_CLKDIV0_REG (CRG_REG_BASE + 0x0A0)
|
||||
#define SC_DIV_LPMCU_MASK ((0x1F << 5) << 16)
|
||||
#define SC_DIV_LPMCU(x) (((x) & 0x1F) << 5)
|
||||
|
||||
#define CRG_CLKDIV1_REG (CRG_REG_BASE + 0x0B0)
|
||||
#define SEL_LPMCU_PLL_MASK ((1 << 1) << 16)
|
||||
#define SEL_SYSBUS_MASK ((1 << 0) << 16)
|
||||
#define SEL_LPMCU_PLL1 (1 << 1)
|
||||
#define SEL_LPMCU_PLL0 (0 << 1)
|
||||
#define SEL_SYSBUS_PLL0 (1 << 0)
|
||||
#define SEL_SYSBUS_PLL1 (0 << 0)
|
||||
|
||||
#define CRG_CLKDIV3_REG (CRG_REG_BASE + 0x0B4)
|
||||
#define CRG_CLKDIV5_REG (CRG_REG_BASE + 0x0BC)
|
||||
#define CRG_CLKDIV8_REG (CRG_REG_BASE + 0x0C8)
|
||||
|
||||
#define CRG_CLKDIV12_REG (CRG_REG_BASE + 0x0D8)
|
||||
#define SC_DIV_A53HPM_MASK (0x7 << 13)
|
||||
#define SC_DIV_A53HPM(x) (((x) & 0x7) << 13)
|
||||
|
||||
#define CRG_CLKDIV16_REG (CRG_REG_BASE + 0x0E8)
|
||||
#define DDRC_CLK_SW_REQ_CFG_MASK (0x3 << 12)
|
||||
#define DDRC_CLK_SW_REQ_CFG(x) (((x) & 0x3) << 12)
|
||||
#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9)
|
||||
#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9)
|
||||
#define DDRCPLL_SW (1 << 8)
|
||||
|
||||
#define CRG_CLKDIV17_REG (CRG_REG_BASE + 0x0EC)
|
||||
#define SC_DIV_UFS_PERIBUS (1 << 14)
|
||||
|
||||
#define CRG_CLKDIV18_REG (CRG_REG_BASE + 0x0F0)
|
||||
#define CRG_CLKDIV19_REG (CRG_REG_BASE + 0x0F4)
|
||||
#define CRG_CLKDIV20_REG (CRG_REG_BASE + 0x0F8)
|
||||
#define CLKDIV20_GT_CLK_AOMM (1 << 3)
|
||||
|
||||
#define CRG_CLKDIV22_REG (CRG_REG_BASE + 0x100)
|
||||
#define SEL_PLL_320M_MASK (1 << 16)
|
||||
#define SEL_PLL2_320M (1 << 0)
|
||||
#define SEL_PLL0_320M (0 << 0)
|
||||
|
||||
#define CRG_CLKDIV23_REG (CRG_REG_BASE + 0x104)
|
||||
#define PERI_DDRC_SW_BIT (1 << 13)
|
||||
#define DIV_CLK_DDRSYS_MASK (0x3 << 10)
|
||||
#define DIV_CLK_DDRSYS(x) (((x) & 0x3) << 10)
|
||||
#define GET_DIV_CLK_DDRSYS(x) (((x) & DIV_CLK_DDRSYS_MASK) >> 10)
|
||||
#define DIV_CLK_DDRCFG_MASK (0x6 << 5)
|
||||
#define DIV_CLK_DDRCFG(x) (((x) & 0x6) << 5)
|
||||
#define GET_DIV_CLK_DDRCFG(x) (((x) & DIV_CLK_DDRCFG_MASK) >> 5)
|
||||
#define DIV_CLK_DDRC_MASK 0x1F
|
||||
#define DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK)
|
||||
#define GET_DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK)
|
||||
|
||||
#define CRG_CLKDIV25_REG (CRG_REG_BASE + 0x10C)
|
||||
#define DIV_SYSBUS_PLL_MASK (0xF << 16)
|
||||
#define DIV_SYSBUS_PLL(x) ((x) & 0xF)
|
||||
|
||||
#define CRG_PERI_CTRL2_REG (CRG_REG_BASE + 0x128)
|
||||
#define PERI_TIME_STAMP_CLK_MASK (0x7 << 28)
|
||||
#define PERI_TIME_STAMP_CLK_DIV(x) (((x) & 0x7) << 22)
|
||||
|
||||
#define CRG_ISODIS_REG (CRG_REG_BASE + 0x148)
|
||||
#define CRG_PERPWREN_REG (CRG_REG_BASE + 0x150)
|
||||
|
||||
#define CRG_PEREN7_REG (CRG_REG_BASE + 0x420)
|
||||
#define CRG_PERDIS7_REG (CRG_REG_BASE + 0x424)
|
||||
#define CRG_PERSTAT7_REG (CRG_REG_BASE + 0x428)
|
||||
#define GT_CLK_UFSPHY_CFG (1 << 14)
|
||||
|
||||
#define CRG_PEREN8_REG (CRG_REG_BASE + 0x430)
|
||||
#define CRG_PERDIS8_REG (CRG_REG_BASE + 0x434)
|
||||
#define CRG_PERSTAT8_REG (CRG_REG_BASE + 0x438)
|
||||
#define PERI_DMC_D_BIT (1 << 22)
|
||||
#define PERI_DMC_C_BIT (1 << 21)
|
||||
#define PERI_DMC_B_BIT (1 << 20)
|
||||
#define PERI_DMC_A_BIT (1 << 19)
|
||||
#define PERI_DMC_BIT (1 << 18)
|
||||
|
||||
#define CRG_PEREN11_REG (CRG_REG_BASE + 0x460)
|
||||
#define PPLL1_GATE_CPU (1 << 18)
|
||||
|
||||
#define CRG_PERSTAT11_REG (CRG_REG_BASE + 0x46C)
|
||||
#define PPLL3_EN_STAT (1 << 21)
|
||||
#define PPLL2_EN_STAT (1 << 20)
|
||||
#define PPLL1_EN_STAT (1 << 19)
|
||||
|
||||
#define CRG_IVP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC04)
|
||||
#define CRG_ISP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC84)
|
||||
|
||||
#define CRG_RVBAR(c, n) (0xE00 + (0x10 * c) + (0x4 * n))
|
||||
#define CRG_GENERAL_SEC_RSTEN_REG (CRG_REG_BASE + 0xE20)
|
||||
#define CRG_GENERAL_SEC_RSTDIS_REG (CRG_REG_BASE + 0xE24)
|
||||
#define IP_RST_GPIO0_SEC (1 << 2)
|
||||
|
||||
#define CRG_GENERAL_SEC_CLKDIV0_REG (CRG_REG_BASE + 0xE90)
|
||||
#define SC_DIV_AO_HISE_MASK 3
|
||||
#define SC_DIV_AO_HISE(x) ((x) & 0x3)
|
||||
|
||||
#endif /* HI3660_CRG_H */
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef HI3660_HKADC_H
|
||||
#define HI3660_HKADC_H
|
||||
|
||||
#define HKADC_SSI_REG_BASE 0xE82B8000
|
||||
|
||||
#define HKADC_DSP_START_REG (HKADC_SSI_REG_BASE + 0x000)
|
||||
#define HKADC_WR_NUM_REG (HKADC_SSI_REG_BASE + 0x008)
|
||||
#define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C)
|
||||
#define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020)
|
||||
|
||||
#define WR1_WRITE_MODE (1U << 31)
|
||||
#define WR1_READ_MODE (0 << 31)
|
||||
#define WR1_ADDR(x) (((x) & 0x7F) << 24)
|
||||
#define WR1_DATA(x) (((x) & 0xFF) << 16)
|
||||
#define WR0_WRITE_MODE (1 << 15)
|
||||
#define WR0_READ_MODE (0 << 15)
|
||||
#define WR0_ADDR(x) (((x) & 0x7F) << 8)
|
||||
#define WR0_DATA(x) ((x) & 0xFF)
|
||||
|
||||
#define HKADC_WR23_DATA_REG (HKADC_SSI_REG_BASE + 0x024)
|
||||
#define HKADC_WR45_DATA_REG (HKADC_SSI_REG_BASE + 0x028)
|
||||
#define HKADC_DELAY01_REG (HKADC_SSI_REG_BASE + 0x030)
|
||||
#define HKADC_DELAY23_REG (HKADC_SSI_REG_BASE + 0x034)
|
||||
#define HKADC_DELAY45_REG (HKADC_SSI_REG_BASE + 0x038)
|
||||
#define HKADC_DSP_RD2_DATA_REG (HKADC_SSI_REG_BASE + 0x048)
|
||||
#define HKADC_DSP_RD3_DATA_REG (HKADC_SSI_REG_BASE + 0x04C)
|
||||
|
||||
/* HKADC Internal Registers */
|
||||
#define HKADC_CTRL_ADDR 0x00
|
||||
#define HKADC_START_ADDR 0x01
|
||||
#define HKADC_DATA1_ADDR 0x03 /* high 8 bits */
|
||||
#define HKADC_DATA0_ADDR 0x04 /* low 8 bits */
|
||||
#define HKADC_MODE_CFG 0x0A
|
||||
|
||||
#define HKADC_VALUE_HIGH 0x0FF0
|
||||
#define HKADC_VALUE_LOW 0x000F
|
||||
#define HKADC_VALID_VALUE 0x0FFF
|
||||
|
||||
#define HKADC_CHANNEL_MAX 15
|
||||
#define HKADC_VREF_1V8 1800
|
||||
#define HKADC_ACCURACY 0x0FFF
|
||||
|
||||
#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \
|
||||
(0x1 << 16))
|
||||
#define HKADC_WR23_VALUE ((0x1u << 31) | \
|
||||
(HKADC_DATA0_ADDR << 24) | \
|
||||
(1 << 15) | \
|
||||
(HKADC_DATA1_ADDR << 8))
|
||||
#define HKADC_WR45_VALUE (0x80)
|
||||
#define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF)
|
||||
#define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200)
|
||||
#define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8)
|
||||
#define START_DELAY_TIMEOUT 2000
|
||||
#define HKADC_WR_NUM_VALUE 4
|
||||
|
||||
#endif /* HI3660_HKADC_H */
|
||||
+20
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HI3660_MEM_MAP_H
|
||||
#define HI3660_MEM_MAP_H
|
||||
|
||||
#define HISI_DATA_HEAD_BASE (0x89C44400)
|
||||
|
||||
#define HISI_RESERVED_MEM_BASE (0x89C80000)
|
||||
#define HISI_RESERVED_MEM_SIZE (0x00040000)
|
||||
|
||||
#define HISI_DATA0_BASE (0x89C96180)
|
||||
#define HISI_DATA0_SIZE (0x000003A0)
|
||||
#define HISI_DATA1_BASE (0x89C93480)
|
||||
#define HISI_DATA1_SIZE (0x00002D00)
|
||||
|
||||
#endif /* HI3660_MEM_MAP_H */
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HISI_IPC_H
|
||||
#define HISI_IPC_H
|
||||
|
||||
enum pm_mode {
|
||||
PM_ON = 0,
|
||||
PM_OFF,
|
||||
};
|
||||
|
||||
void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster,
|
||||
enum pm_mode mode);
|
||||
void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster,
|
||||
unsigned int affinity_level);
|
||||
void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster);
|
||||
void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster,
|
||||
unsigned int cmd_id);
|
||||
int hisi_ipc_init(void);
|
||||
|
||||
#endif /* HISI_IPC_H */
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef PLAT_LD_S
|
||||
#define PLAT_LD_S
|
||||
|
||||
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||
|
||||
MEMORY {
|
||||
RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
ram2_region (NOLOAD) : {
|
||||
*(ram2_region)
|
||||
}>RAM2
|
||||
}
|
||||
|
||||
#endif /* PLAT_LD_S */
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_MACROS_S
|
||||
#define PLAT_MACROS_S
|
||||
|
||||
#include <drivers/arm/cci.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <hi3660.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
.section .rodata.gic_reg_name, "aS"
|
||||
gicc_regs:
|
||||
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
|
||||
gicd_pend_reg:
|
||||
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
|
||||
newline:
|
||||
.asciz "\n"
|
||||
spacer:
|
||||
.asciz ":\t\t0x"
|
||||
|
||||
.section .rodata.cci_reg_name, "aS"
|
||||
cci_iface_regs:
|
||||
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below macro prints out relevant GIC
|
||||
* registers whenever an unhandled exception is
|
||||
* taken in BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
mov_imm x16, GICD_REG_BASE
|
||||
mov_imm x17, GICC_REG_BASE
|
||||
|
||||
/* Load the gicc reg list to x6 */
|
||||
adr x6, gicc_regs
|
||||
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
|
||||
ldr w8, [x17, #GICC_HPPIR]
|
||||
ldr w9, [x17, #GICC_AHPPIR]
|
||||
ldr w10, [x17, #GICC_CTLR]
|
||||
/* Store to the crash buf and print to cosole */
|
||||
bl str_in_crash_buf_print
|
||||
|
||||
/* Print the GICD_ISPENDR regs */
|
||||
add x7, x16, #GICD_ISPENDR
|
||||
adr x4, gicd_pend_reg
|
||||
bl asm_print_str
|
||||
2:
|
||||
sub x4, x7, x16
|
||||
cmp x4, #0x280
|
||||
b.eq 1f
|
||||
bl asm_print_hex
|
||||
adr x4, spacer
|
||||
bl asm_print_str
|
||||
ldr x4, [x7], #8
|
||||
bl asm_print_hex
|
||||
adr x4, newline
|
||||
bl asm_print_str
|
||||
b 2b
|
||||
1:
|
||||
adr x6, cci_iface_regs
|
||||
/* Store in x7 the base address of the first interface */
|
||||
mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
|
||||
CCI400_SL_IFACE3_CLUSTER_IX))
|
||||
ldr w8, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store in x7 the base address of the second interface */
|
||||
mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
|
||||
CCI400_SL_IFACE4_CLUSTER_IX))
|
||||
ldr w9, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
.endm
|
||||
|
||||
#endif /* PLAT_MACROS_S */
|
||||
+150
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include "../hikey960_def.h"
|
||||
|
||||
/* Special value used to verify platform parameters from BL2 to BL3-1 */
|
||||
#define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
|
||||
|
||||
/*
|
||||
* Generic platform constants
|
||||
*/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
|
||||
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
|
||||
|
||||
#define PLATFORM_CACHE_LINE_SIZE 64
|
||||
#define PLATFORM_CLUSTER_COUNT U(2)
|
||||
#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
|
||||
PLATFORM_CORE_COUNT_PER_CLUSTER)
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER_COUNT + 1)
|
||||
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
|
||||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
/* UFS RPMB and UFS User Data */
|
||||
#define MAX_IO_BLOCK_DEVICES U(2)
|
||||
|
||||
|
||||
/*
|
||||
* Platform memory map related constants
|
||||
*/
|
||||
|
||||
/*
|
||||
* BL1 specific defines.
|
||||
*/
|
||||
#define BL1_RO_BASE (0x1AC00000)
|
||||
#define BL1_RO_LIMIT (BL1_RO_BASE + 0x20000)
|
||||
#define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */
|
||||
#define BL1_RW_SIZE (0x00188000)
|
||||
#define BL1_RW_LIMIT (0x1B000000)
|
||||
|
||||
/*
|
||||
* BL2 specific defines.
|
||||
*/
|
||||
#define BL2_BASE (0x1AC00000)
|
||||
#define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
|
||||
|
||||
/*
|
||||
* BL31 specific defines.
|
||||
*/
|
||||
#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
|
||||
#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
|
||||
|
||||
/*
|
||||
* BL3-2 specific defines.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The TSP currently executes from TZC secured area of DRAM.
|
||||
*/
|
||||
#define BL32_DRAM_BASE DDR_SEC_BASE
|
||||
#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
|
||||
|
||||
#ifdef SPD_opteed
|
||||
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
|
||||
#define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
|
||||
#define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
|
||||
#endif
|
||||
|
||||
#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
|
||||
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
|
||||
#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
|
||||
#define BL32_BASE BL32_DRAM_BASE
|
||||
#define BL32_LIMIT BL32_DRAM_LIMIT
|
||||
#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
|
||||
#error "SRAM storage of TSP payload is currently unsupported"
|
||||
#else
|
||||
#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
|
||||
#endif
|
||||
|
||||
/* BL32 is mandatory in AArch32 */
|
||||
#ifdef __aarch64__
|
||||
#ifdef SPD_none
|
||||
#undef BL32_BASE
|
||||
#endif /* SPD_none */
|
||||
#endif
|
||||
|
||||
#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
|
||||
#define NS_BL1U_SIZE (0x00100000)
|
||||
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
|
||||
|
||||
#define HIKEY960_NS_IMAGE_OFFSET (0x1AC28000) /* offset in l-loader */
|
||||
#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
|
||||
|
||||
#define SCP_BL2_BASE (0x89C80000)
|
||||
#define SCP_BL2_SIZE (0x00040000)
|
||||
|
||||
/*
|
||||
* Platform specific page table and MMU setup constants
|
||||
*/
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
|
||||
|
||||
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
|
||||
#define MAX_XLAT_TABLES 3
|
||||
#endif
|
||||
|
||||
#if defined(IMAGE_BL2)
|
||||
#define MAX_XLAT_TABLES 5
|
||||
#endif
|
||||
|
||||
#if defined(IMAGE_BL31)
|
||||
#if defined(SPMC_AT_EL3)
|
||||
#define MAX_XLAT_TABLES 17
|
||||
#else
|
||||
#define MAX_XLAT_TABLES 5
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
/*
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
Reference in New Issue
Block a user