GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HI3798CV200_H
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#define HI3798CV200_H
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#include <lib/utils_def.h>
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/* PL011 */
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#define PL011_UART0_BASE (0xF8B00000)
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#define PL011_BAUDRATE (115200)
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#define PL011_UART0_CLK_IN_HZ (75000000)
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/* Sys Counter */
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#define SYS_COUNTER_FREQ_IN_TICKS (24000000)
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#define SYS_COUNTER_FREQ_IN_MHZ (24)
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/* Timer */
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#define SEC_TIMER0_BASE (0xF8008000)
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#define TIMER00_LOAD (SEC_TIMER0_BASE + 0x000)
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#define TIMER00_VALUE (SEC_TIMER0_BASE + 0x004)
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#define TIMER00_CONTROL (SEC_TIMER0_BASE + 0x008)
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#define TIMER00_BGLOAD (SEC_TIMER0_BASE + 0x018)
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#define SEC_TIMER2_BASE (0xF8009000)
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#define TIMER20_LOAD (SEC_TIMER2_BASE + 0x000)
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#define TIMER20_VALUE (SEC_TIMER2_BASE + 0x004)
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#define TIMER20_CONTROL (SEC_TIMER2_BASE + 0x008)
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#define TIMER20_BGLOAD (SEC_TIMER2_BASE + 0x018)
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/* GPIO */
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#define GPIO_MAX (13)
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#define GPIO_BASE(x) (x != 5 ? \
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0xf820000 + x * 0x1000 : 0xf8004000)
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/* SCTL */
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#define REG_BASE_SCTL (0xF8000000)
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#define REG_SC_GEN12 (0x00B0)
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/* CRG */
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#define REG_BASE_CRG (0xF8A22000)
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#define REG_CPU_LP (0x48)
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#define REG_CPU_RST (0x50)
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#define REG_PERI_CRG39 (0x9C)
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#define REG_PERI_CRG40 (0xA0)
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/* MCI */
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#define REG_BASE_MCI (0xF9830000)
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#define MCI_CDETECT (0x50)
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#define MCI_VERID (0x6C)
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#define MCI_VERID_VALUE (0x5342250A)
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#define MCI_VERID_VALUE2 (0x5342270A)
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/* EMMC */
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#define REG_EMMC_PERI_CRG REG_PERI_CRG40
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#define REG_SDCARD_PERI_CRG REG_PERI_CRG39
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#define EMMC_CLK_MASK (0x7 << 8)
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#define EMMC_SRST_REQ (0x1 << 4)
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#define EMMC_CKEN (0x1 << 1)
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#define EMMC_BUS_CKEN (0x1 << 0)
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#define EMMC_CLK_100M (0 << 8)
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#define EMMC_CLK_50M (1 << 8)
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#define EMMC_CLK_25M (2 << 8)
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#define EMMC_DESC_SIZE U(0x00100000) /* 1MB */
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#define EMMC_INIT_PARAMS(base) \
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{ .bus_width = MMC_BUS_WIDTH_8, \
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.clk_rate = 25 * 1000 * 1000, \
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.desc_base = (base), \
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.desc_size = EMMC_DESC_SIZE, \
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.flags = MMC_FLAG_CMD23, \
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.reg_base = REG_BASE_MCI, \
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}
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/* GIC-400 */
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#define GICD_BASE (0xF1001000)
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#define GICC_BASE (0xF1002000)
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#define GICR_BASE (0xF1000000)
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/* FIQ platform related define */
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#define HISI_IRQ_SEC_SGI_0 8
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#define HISI_IRQ_SEC_SGI_1 9
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#define HISI_IRQ_SEC_SGI_2 10
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#define HISI_IRQ_SEC_SGI_3 11
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#define HISI_IRQ_SEC_SGI_4 12
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#define HISI_IRQ_SEC_SGI_5 13
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#define HISI_IRQ_SEC_SGI_6 14
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#define HISI_IRQ_SEC_SGI_7 15
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#define HISI_IRQ_SEC_PPI_0 29
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#define HISI_IRQ_SEC_TIMER0 60
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#define HISI_IRQ_SEC_TIMER1 50
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#define HISI_IRQ_SEC_TIMER2 52
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#define HISI_IRQ_SEC_TIMER3 88
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#define HISI_IRQ_SEC_AXI 110
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/* Watchdog */
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#define HISI_WDG0_BASE (0xF8A2C000)
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#define HISI_TZPC_BASE (0xF8A80000)
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#define HISI_TZPC_SEC_ATTR_CTRL (HISI_TZPC_BASE + 0x10)
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#endif /* HI3798CV200_H */
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+10
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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.section .rodata.gic_reg_name, "aS"
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.macro plat_crash_print_regs
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nop
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.endm
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+37
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PRIVATE_H
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#define PLAT_PRIVATE_H
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#include <common/bl_common.h>
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#include "hi3798cv200.h"
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void plat_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit);
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void plat_configure_mmu_el1(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit);
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void plat_io_setup(void);
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unsigned int poplar_calc_core_pos(u_register_t mpidr);
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void poplar_gic_driver_init(void);
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void poplar_gic_init(void);
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void poplar_gic_cpuif_enable(void);
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void poplar_gic_pcpu_init(void);
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#endif /* PLAT_PRIVATE_H */
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+171
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/interrupt_props.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include "hi3798cv200.h"
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#include "poplar_layout.h" /* BL memory region sizes, etc */
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define POPLAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define POPLAR_CRASH_UART_BASE PL011_UART0_BASE
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#define POPLAR_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ
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#define POPLAR_CONSOLE_BAUDRATE PL011_BAUDRATE
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/* Generic platform constants */
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#define PLATFORM_STACK_SIZE (0x800)
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define BOOT_EMMC_NAME "l-loader.bin"
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#define PLATFORM_CACHE_LINE_SIZE (64)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CORE_COUNT U(4)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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/* IO framework user */
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#define MAX_IO_DEVICES (4)
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#define MAX_IO_HANDLES (4)
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#define MAX_IO_BLOCK_DEVICES U(2)
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/* Memory size options */
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#define POPLAR_DRAM_SIZE_1G 0
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#define POPLAR_DRAM_SIZE_2G 1
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/* Memory map related constants */
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#define DDR_BASE (0x00000000)
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#if (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_2G)
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#define DDR_SIZE (0x80000000)
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#elif (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_1G)
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#define DDR_SIZE (0x40000000)
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#else
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#error "Currently unsupported POPLAR_DRAM_SIZE_ID value"
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#endif
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#define DEVICE_BASE (0xF0000000)
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#define DEVICE_SIZE (0x0F000000)
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#define TEE_SEC_MEM_BASE (0x70000000)
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#define TEE_SEC_MEM_SIZE (0x10000000)
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/* Memory location options for TSP */
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#define POPLAR_SRAM_ID 0
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#define POPLAR_DRAM_ID 1
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/*
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* DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several
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* regions:
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* - Secure DDR (default is the top 16MB) used by OP-TEE
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* - Non-secure DDR (4MB) reserved for OP-TEE's future use
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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*/
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#define DDR_SEC_SIZE 0x01000000
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#define DDR_SEC_BASE 0x03000000
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM.
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*/
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#define BL32_DRAM_BASE 0x03000000
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#define BL32_DRAM_LIMIT 0x04000000
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */
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#endif
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#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID)
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#error "SRAM storage of TSP payload is currently unsupported"
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#else
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#error "Currently unsupported POPLAR_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifdef __aarch64__
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#define POPLAR_EMMC_DATA_BASE U(0x02200000)
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#define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE
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#define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE)
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#define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE
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#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
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/* Page table and MMU setup constants */
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES (4)
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#define MAX_MMAP_REGIONS (16)
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Power states */
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#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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/* Interrupt controller */
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#define POPLAR_GICD_BASE GICD_BASE
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#define POPLAR_GICC_BASE GICC_BASE
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#define POPLAR_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define POPLAR_G0_IRQ_PROPS(grp)
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#endif /* PLATFORM_DEF_H */
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+132
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef POPLAR_LAYOUT_H
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#define POPLAR_LAYOUT_H
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/*
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* Boot memory layout definitions for the HiSilicon Poplar board
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*/
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/*
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* When Poplar is powered on, boot ROM verifies the initial content of
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* boot media, loads it into low memory, and begins executing it
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* in 32-bit mode. The image loaded is "l-loader.bin", which contains
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* a small amount code along with an embedded ARM Trusted Firmware
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* BL1 image. The main purpose of "l-loader" is to prepare the
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* processor to execute the BL1 image in 64-bit mode, and to trigger
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* that execution.
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*
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* Also embedded in "l-loader.bin" is a FIP image that contains
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* other ARM Trusted Firmware images: BL2; BL31; and for BL33,
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* U-Boot. When BL1 executes, it unpacks the BL2 image from the FIP
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* image into a region of memory set aside to hold it. Similarly,
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* BL2 unpacks BL31 into memory reserved for it, and unpacks U-Boot
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* into high memory.
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*
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* Because the BL1 code is embedded in "l-loader", its base address
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* in memory is derived from the base address of the "l-loader"
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* text section, together with an offset. Memory space for BL2 is
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* reserved immediately following BL1, and memory space is reserved
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* for BL31 after that. ARM Trusted Firmware requires each of these
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* memory regions to be aligned on page boundaries, so the size of
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* each region is a multiple of a page size (ending in 000). Note
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* that ARM Trusted Firmware requires the read-only and read-write
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* regions of memory used for BL1 to be defined separately.
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*
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* ---------------------
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* | (unused memory) |
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* +-------------------+ - - - - -
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* | (l-loader text) | \
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* +-------------------+ \
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* | BL1 (read-only) | \ \
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* |- - - - - - - - - -| | |
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* | BL1 (read-write) | | |
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* +-------------------+ > BL Memory |
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* | Reserved for BL2 | | > "l-loader.bin" image
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* +-------------------+ | |
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* | Reserved for BL31 | / |
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* +-------------------+ |
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* . . . /
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* +-------------------+ /
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* | FIP | /
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* +-------------------+ - - - - -
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* . . .
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* | (unused memory) |
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* . . .
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* +-------------------+
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* |Reserved for U-Boot|
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* +-------------------+
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* . . .
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* | (unused memory) |
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* ---------------------
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*
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* The size of each of these regions is defined below. The base
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* address of the "l-loader" TEXT section and the offset of the BL1
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* image within that serve as anchors for defining the positions of
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* all other regions. The FIP is placed in a section of its own.
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*
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* A "BASE" is the memory address of the start of a region; a "LIMIT"
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* marks its end. A "SIZE" is the size of a region (in bytes). An
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* "OFFSET" is an offset to the start of a region relative to the
|
||||
* base of the "l-loader" TEXT section (also a multiple of page size).
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*/
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#define LLOADER_TEXT_BASE 0x02001000 /* page aligned */
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#define BL1_OFFSET 0x0000D000 /* page multiple */
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||||
#define FIP_BASE 0x02040000
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||||
/*
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* FIP_BASE_EMMC = 0x40000 - 0x1000
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* = fip.bin offset - l-loader text offset
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||||
* in l-loader.bin
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*/
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||||
#define FIP_BASE_EMMC 0x0003f000
|
||||
|
||||
#define BL1_RO_SIZE 0x00008000 /* page multiple */
|
||||
#define BL1_RW_SIZE 0x00008000 /* page multiple */
|
||||
#define BL1_SIZE (BL1_RO_SIZE + BL1_RW_SIZE)
|
||||
#define BL2_SIZE 0x0000d000 /* page multiple */
|
||||
#define BL31_SIZE 0x00014000
|
||||
#if !POPLAR_RECOVERY
|
||||
/*
|
||||
* emmc partition1 4096KB
|
||||
* - l-loader.bin 1984KB
|
||||
* |- l-loader + bl1.bin 256KB
|
||||
* |- fip.bin 1728KB (0x001b0000)
|
||||
* - u-boot persistent data 64KB
|
||||
* - uefi persistent data 2048KB
|
||||
*/
|
||||
#define FIP_SIZE 0x001b0000 /* absolute max */
|
||||
#else
|
||||
/*
|
||||
* same as above, but bootrom can only load an image (l-loader.bin) of
|
||||
* 1024KB max, so after deducting the size of l-loader + bl1.bin (256KB),
|
||||
* that leaves 768KB (0x000c0000) for fip.bin
|
||||
*/
|
||||
#define FIP_SIZE 0x000c0000 /* absolute max */
|
||||
#endif
|
||||
|
||||
/* BL1_OFFSET */ /* (Defined above) */
|
||||
#define BL1_BASE (LLOADER_TEXT_BASE + BL1_OFFSET)
|
||||
#define BL1_LIMIT (BL1_BASE + BL1_SIZE)
|
||||
|
||||
#define BL1_RO_OFFSET (BL1_OFFSET)
|
||||
#define BL1_RO_BASE (LLOADER_TEXT_BASE + BL1_RO_OFFSET)
|
||||
#define BL1_RO_LIMIT (BL1_RO_BASE + BL1_RO_SIZE)
|
||||
|
||||
#define BL1_RW_OFFSET (BL1_RO_OFFSET + BL1_RO_SIZE)
|
||||
#define BL1_RW_BASE (LLOADER_TEXT_BASE + BL1_RW_OFFSET)
|
||||
#define BL1_RW_LIMIT (BL1_RW_BASE + BL1_RW_SIZE)
|
||||
|
||||
#define BL2_OFFSET (BL1_OFFSET + BL1_SIZE)
|
||||
#define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET)
|
||||
#define BL2_LIMIT (BL2_BASE + BL2_SIZE)
|
||||
|
||||
#define BL31_OFFSET (BL2_OFFSET + BL2_SIZE)
|
||||
#define BL31_BASE (LLOADER_TEXT_BASE + BL31_OFFSET)
|
||||
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
|
||||
|
||||
#endif /* POPLAR_LAYOUT_H */
|
||||
Reference in New Issue
Block a user