GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <console_macros.S>
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#include <assert_macros.S>
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#include "imx_uart.h"
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.globl console_imx_uart_register
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.globl console_imx_uart_putc
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.globl console_imx_uart_getc
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.globl console_imx_uart_flush
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func console_imx_uart_register
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push {r4, lr}
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mov r4, r3
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cmp r4, #0
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beq register_fail
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str r0, [r4, #CONSOLE_T_BASE]
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bl console_imx_uart_core_init
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cmp r0, #0
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bne register_fail
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mov r0, r4
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pop {r4, lr}
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finish_console_register imx_uart putc=1, getc=1, flush=1
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register_fail:
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pop {r4, pc}
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endfunc console_imx_uart_register
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func console_imx_uart_putc
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ldr r1, [r1, #CONSOLE_T_BASE]
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b console_imx_uart_core_putc
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endfunc console_imx_uart_putc
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func console_imx_uart_getc
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ldr r0, [r0, #CONSOLE_T_BASE]
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b console_imx_uart_core_getc
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endfunc console_imx_uart_getc
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func console_imx_uart_flush
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ldr r0, [r0, #CONSOLE_T_BASE]
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b console_imx_uart_core_flush
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endfunc console_imx_uart_flush
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@@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <imx_regs.h>
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#include <imx_clock.h>
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static void imx7_clock_uart_init(void)
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{
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unsigned int i;
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for (i = 0; i < MXC_MAX_UART_NUM; i++)
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imx_clock_disable_uart(i);
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}
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static void imx7_clock_wdog_init(void)
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{
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unsigned int i;
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for (i = 0; i < MXC_MAX_WDOG_NUM; i++)
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imx_clock_disable_wdog(i);
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}
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static void imx7_clock_usb_init(void)
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{
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/* Disable the clock root */
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imx_clock_target_clr(CCM_TRT_ID_USB_HSIC_CLK_ROOT, 0xFFFFFFFF);
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}
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void imx_clock_init(void)
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{
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/*
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* The BootROM hands off to the next stage with the internal 24 MHz XTAL
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* crystal already clocking the main PLL, which is very handy.
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* Here we should enable whichever peripherals are required for ATF and
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* OPTEE.
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*
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* Subsequent stages in the boot process such as u-boot and Linux
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* already have a significant and mature code-base around clocks, so our
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* objective should be to enable what we need for ATF/OPTEE without
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* breaking any existing upstream code in Linux and u-boot.
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*/
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/* Initialize UART clocks */
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imx7_clock_uart_init();
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/* Watchdog clocks */
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imx7_clock_wdog_init();
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/* USB clocks */
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imx7_clock_usb_init();
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}
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@@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <cortex_a35.h>
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_calc_core_pos
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.globl plat_reset_handler
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl imx_mailbox_init
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/* --------------------------------------------------------------------
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* Helper macro that reads the part number of the current CPU and jumps
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* to the given label if it matches the CPU MIDR provided.
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*
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* Clobbers x0.
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* --------------------------------------------------------------------
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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/* ----------------------------------------------
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* The mailbox_base is used to distinguish warm/cold
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* reset. The mailbox_base is in the data section, not
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* in .bss, this allows function to start using this
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* variable before the runtime memory is initialized.
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* ----------------------------------------------
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*/
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.section .data.mailbox_base
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.align 3
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mailbox_base: .quad 0x0
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/* ----------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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* This function checks if this is the primary CPU
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* ----------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ----------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This Function uses the plat_calc_core_pos()
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* to get the index of the calling CPU.
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* ----------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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/*
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* unsigned int plat_calc_core_pos(uint64_t mpidr)
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* helper function to calculate the core position.
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* With this function.
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*/
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func plat_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_calc_core_pos
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/* ---------------------------------------------
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* function to get the entrypoint.
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* ---------------------------------------------
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*/
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func plat_get_my_entrypoint
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adrp x1, mailbox_base
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ldr x0, [x1, :lo12:mailbox_base]
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ret
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endfunc plat_get_my_entrypoint
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func imx_mailbox_init
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adrp x1, mailbox_base
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str x0, [x1, :lo12:mailbox_base]
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ret
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endfunc imx_mailbox_init
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func plat_secondary_cold_boot_setup
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b .
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endfunc plat_secondary_cold_boot_setup
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func plat_crash_console_init
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mov x0, #1
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ret
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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ret
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov x0, #0
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ret
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endfunc plat_crash_console_flush
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func platform_mem_init
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ret
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endfunc platform_mem_init
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@@ -0,0 +1,62 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <plat_imx8.h>
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#include <sci/sci.h>
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void __dead2 imx_system_off(void)
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{
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sc_pm_set_sys_power_mode(ipc_handle, SC_PM_PW_MODE_OFF);
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wfi();
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ERROR("power off failed.\n");
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panic();
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}
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void __dead2 imx_system_reset(void)
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{
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sc_pm_reset(ipc_handle, SC_PM_RESET_TYPE_BOARD);
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wfi();
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ERROR("system reset failed.\n");
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panic();
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}
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int imx_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int pwr_type = psci_get_pstate_type(power_state);
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int state_id = psci_get_pstate_id(power_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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if (pwr_type == PSTATE_TYPE_POWERDOWN) {
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
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if (!state_id)
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE;
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else
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE;
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}
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return PSCI_E_SUCCESS;
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}
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void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int i;
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/* CPU & cluster off, system in retention */
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for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
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}
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@@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <plat/common/platform.h>
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const unsigned char imx_power_domain_tree_desc[] = {
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PWR_DOMAIN_AT_MAX_LVL,
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PLATFORM_CLUSTER_COUNT,
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PLATFORM_CLUSTER0_CORE_COUNT,
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PLATFORM_CLUSTER1_CORE_COUNT,
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};
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return imx_power_domain_tree_desc;
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}
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
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return -1;
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cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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if (cluster_id > PLATFORM_CLUSTER_COUNT ||
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cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER)
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return -1;
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return (cpu_id + (cluster_id * 4));
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}
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@@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <imx_aips.h>
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#include <imx_regs.h>
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static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
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{
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int i;
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uintptr_t addr;
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/*
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* See section 4.7.7.1 AIPSTZ_MPR field descriptions
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
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* 0111 ->
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* 0: Write Access from master not buffered
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* 1: Master is trusted for read access
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* 1: Master is trsuted for write access
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* 1: Access from master is not forced to user mode
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*/
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addr = (uintptr_t)&aips_regs->aipstz_mpr;
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mmio_write_32(addr, 0x77777777);
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/*
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* Helpfully the OPACR registers have the logical inversion of the above
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* See section 4.7.7.1 AIPSTZ_MPR field descriptions
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
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* 0000 ->
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* 0: Write Access to the peripheral is not buffered by AIPSTZ
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* 0: The peripheral does not require supervisor priv to access
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* 0: Master is trsuted for write access
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* 0: Access from master is not forced to user mode
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*/
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for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
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addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
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mmio_write_32(addr, 0x00000000);
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}
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}
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void imx_aips_init(void)
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{
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int i;
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struct aipstz_regs *aips_regs[] = {
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(struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
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(struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
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(struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
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};
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for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
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imx_aips_set_default_access(aips_regs[i]);
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}
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@@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <lib/mmio.h>
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#include <imx_caam.h>
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void imx_caam_init(void)
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{
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struct caam_ctrl *caam = (struct caam_ctrl *)CAAM_AIPS_BASE;
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uint32_t reg;
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int i;
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for (i = 0; i < CAAM_NUM_JOB_RINGS; i++) {
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reg = mmio_read_32((uintptr_t)&caam->jr[i].jrmidr_ms);
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reg |= JROWN_NS | JROWN_MID;
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mmio_write_32((uintptr_t)&caam->jr[i].jrmidr_ms, reg);
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}
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}
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@@ -0,0 +1,155 @@
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/*
|
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <arch.h>
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#include <lib/mmio.h>
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#include <imx_regs.h>
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#include <imx_clock.h>
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void imx_clock_target_set(unsigned int id, uint32_t val)
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{
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struct ccm *ccm = ((struct ccm *)CCM_BASE);
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uintptr_t addr;
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if (id > CCM_ROOT_CTRL_NUM)
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return;
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addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root;
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mmio_write_32(addr, val);
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}
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void imx_clock_target_clr(unsigned int id, uint32_t val)
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{
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struct ccm *ccm = ((struct ccm *)CCM_BASE);
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uintptr_t addr;
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if (id > CCM_ROOT_CTRL_NUM)
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return;
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addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root_clr;
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mmio_write_32(addr, val);
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}
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void imx_clock_gate_enable(unsigned int id, bool enable)
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{
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struct ccm *ccm = ((struct ccm *)CCM_BASE);
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uintptr_t addr;
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if (id > CCM_CLK_GATE_CTRL_NUM)
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return;
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/* TODO: add support for more than DOMAIN0 clocks */
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if (enable)
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addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_set;
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else
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addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_clr;
|
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mmio_write_32(addr, CCM_CCGR_SETTING0_DOM_CLK_ALWAYS);
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}
|
||||
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||||
void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits)
|
||||
{
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||||
unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
|
||||
unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
|
||||
|
||||
/* Check for error */
|
||||
if (uart_id > MXC_MAX_UART_NUM)
|
||||
return;
|
||||
|
||||
/* Set target register values */
|
||||
imx_clock_target_set(ccm_trgt_id, uart_clk_en_bits);
|
||||
|
||||
/* Enable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_id, true);
|
||||
}
|
||||
|
||||
void imx_clock_disable_uart(unsigned int uart_id)
|
||||
{
|
||||
unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
|
||||
unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
|
||||
|
||||
/* Check for error */
|
||||
if (uart_id > MXC_MAX_UART_NUM)
|
||||
return;
|
||||
|
||||
/* Disable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_id, false);
|
||||
|
||||
/* Clear the target */
|
||||
imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits)
|
||||
{
|
||||
unsigned int ccm_trgt_id = CCM_TRT_ID_USDHC1_CLK_ROOT + usdhc_id;
|
||||
unsigned int ccm_ccgr_id = CCM_CCGR_ID_USBHDC1 + usdhc_id;
|
||||
|
||||
/* Check for error */
|
||||
if (usdhc_id > MXC_MAX_USDHC_NUM)
|
||||
return;
|
||||
|
||||
/* Set target register values */
|
||||
imx_clock_target_set(ccm_trgt_id, usdhc_clk_en_bits);
|
||||
|
||||
/* Enable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_id, true);
|
||||
}
|
||||
|
||||
void imx_clock_enable_wdog(unsigned int wdog_id)
|
||||
{
|
||||
unsigned int ccm_ccgr_id = CCM_CCGR_ID_WDOG1 + wdog_id;
|
||||
|
||||
/* Check for error */
|
||||
if (wdog_id > MXC_MAX_WDOG_NUM)
|
||||
return;
|
||||
|
||||
/* Enable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_id, true);
|
||||
}
|
||||
|
||||
void imx_clock_disable_wdog(unsigned int wdog_id)
|
||||
{
|
||||
unsigned int ccm_trgt_id = CCM_TRT_ID_WDOG_CLK_ROOT;
|
||||
unsigned int ccm_ccgr_id = CCM_CCGR_ID_WDOG1 + wdog_id;
|
||||
|
||||
/* Check for error */
|
||||
if (wdog_id > MXC_MAX_WDOG_NUM)
|
||||
return;
|
||||
|
||||
/* Disable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_id, false);
|
||||
|
||||
/* Clear the target */
|
||||
imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits)
|
||||
{
|
||||
/* Enable the common clock root just once */
|
||||
imx_clock_target_set(CCM_TRT_ID_WDOG_CLK_ROOT, wdog_clk_root_en_bits);
|
||||
}
|
||||
|
||||
void imx_clock_enable_usb(unsigned int ccm_ccgr_usb_id)
|
||||
{
|
||||
/* Enable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_usb_id, true);
|
||||
}
|
||||
|
||||
void imx_clock_disable_usb(unsigned int ccm_ccgr_usb_id)
|
||||
{
|
||||
/* Disable the clock gate */
|
||||
imx_clock_gate_enable(ccm_ccgr_usb_id, false);
|
||||
}
|
||||
|
||||
void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits)
|
||||
{
|
||||
/* Enable the common clock root just once */
|
||||
imx_clock_target_set(CCM_TRT_ID_USB_HSIC_CLK_ROOT, usb_clk_root_en_bits);
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <imx_csu.h>
|
||||
#include <imx_regs.h>
|
||||
|
||||
void imx_csu_init(void)
|
||||
{
|
||||
int i;
|
||||
uintptr_t *csl_reg = (uintptr_t *)CSU_BASE;
|
||||
|
||||
for (i = 0; i < MXC_MAX_CSU_REGS; i++, csl_reg++)
|
||||
mmio_write_32((uintptr_t)csl_reg, CSU_CSL_OPEN_ACCESS);
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <bl31/ehf.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
ehf_pri_desc_t imx_exceptions[] = {
|
||||
#if SDEI_SUPPORT
|
||||
/* Critical priority SDEI */
|
||||
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
|
||||
|
||||
/* Normal priority SDEI */
|
||||
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Plug in ARM exceptions to Exception Handling Framework. */
|
||||
EHF_REGISTER_PRIORITIES(imx_exceptions, ARRAY_SIZE(imx_exceptions), PLAT_PRI_BITS);
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <imx_regs.h>
|
||||
#include <imx_io_mux.h>
|
||||
|
||||
void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function)
|
||||
{
|
||||
uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_mux_offset);
|
||||
|
||||
mmio_write_32(addr, alt_function);
|
||||
}
|
||||
|
||||
void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features)
|
||||
{
|
||||
uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_feature_offset);
|
||||
|
||||
mmio_write_32(addr, pad_features);
|
||||
}
|
||||
@@ -0,0 +1,301 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/io/io_block.h>
|
||||
#include <drivers/io/io_driver.h>
|
||||
#include <drivers/io/io_fip.h>
|
||||
#include <drivers/io/io_memmap.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <tbbr_img_def.h>
|
||||
#include <tools_share/firmware_image_package.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
static const io_dev_connector_t *fip_dev_con;
|
||||
static uintptr_t fip_dev_handle;
|
||||
|
||||
#ifndef IMX_FIP_MMAP
|
||||
static const io_dev_connector_t *mmc_dev_con;
|
||||
static uintptr_t mmc_dev_handle;
|
||||
|
||||
static const io_block_spec_t mmc_fip_spec = {
|
||||
.offset = IMX_FIP_MMC_BASE,
|
||||
.length = IMX_FIP_SIZE
|
||||
};
|
||||
|
||||
static const io_block_dev_spec_t mmc_dev_spec = {
|
||||
/* It's used as temp buffer in block driver. */
|
||||
.buffer = {
|
||||
.offset = IMX_FIP_BASE,
|
||||
/* do we need a new value? */
|
||||
.length = IMX_FIP_SIZE
|
||||
},
|
||||
.ops = {
|
||||
.read = mmc_read_blocks,
|
||||
.write = mmc_write_blocks,
|
||||
},
|
||||
.block_size = MMC_BLOCK_SIZE,
|
||||
};
|
||||
|
||||
static int open_mmc(const uintptr_t spec);
|
||||
|
||||
#else
|
||||
static const io_dev_connector_t *memmap_dev_con;
|
||||
static uintptr_t memmap_dev_handle;
|
||||
|
||||
static const io_block_spec_t fip_block_spec = {
|
||||
.offset = IMX_FIP_BASE,
|
||||
.length = IMX_FIP_SIZE
|
||||
};
|
||||
static int open_memmap(const uintptr_t spec);
|
||||
#endif
|
||||
|
||||
static int open_fip(const uintptr_t spec);
|
||||
|
||||
static const io_uuid_spec_t bl31_uuid_spec = {
|
||||
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl32_uuid_spec = {
|
||||
.uuid = UUID_SECURE_PAYLOAD_BL32,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl32_extra1_uuid_spec = {
|
||||
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl32_extra2_uuid_spec = {
|
||||
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl33_uuid_spec = {
|
||||
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
|
||||
};
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
|
||||
.uuid = UUID_TRUSTED_BOOT_FW_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
|
||||
.uuid = UUID_TRUSTED_KEY_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
|
||||
.uuid = UUID_SOC_FW_KEY_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
|
||||
.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
|
||||
.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t soc_fw_content_cert_uuid_spec = {
|
||||
.uuid = UUID_SOC_FW_CONTENT_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
|
||||
.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
|
||||
.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
|
||||
};
|
||||
#endif /* TRUSTED_BOARD_BOOT */
|
||||
|
||||
/* TODO: this structure is replicated multiple times. rationalize it ! */
|
||||
struct plat_io_policy {
|
||||
uintptr_t *dev_handle;
|
||||
uintptr_t image_spec;
|
||||
int (*check)(const uintptr_t spec);
|
||||
};
|
||||
|
||||
static const struct plat_io_policy policies[] = {
|
||||
#ifndef IMX_FIP_MMAP
|
||||
[FIP_IMAGE_ID] = {
|
||||
&mmc_dev_handle,
|
||||
(uintptr_t)&mmc_fip_spec,
|
||||
open_mmc
|
||||
},
|
||||
#else
|
||||
[FIP_IMAGE_ID] = {
|
||||
&memmap_dev_handle,
|
||||
(uintptr_t)&fip_block_spec,
|
||||
open_memmap
|
||||
},
|
||||
#endif
|
||||
[BL31_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl31_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[BL32_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl32_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[BL32_EXTRA1_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl32_extra1_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[BL32_EXTRA2_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl32_extra2_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[BL33_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl33_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
[TRUSTED_BOOT_FW_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&tb_fw_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[SOC_FW_KEY_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&soc_fw_key_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[TRUSTED_KEY_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&trusted_key_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[TRUSTED_OS_FW_KEY_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&tos_fw_key_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[NON_TRUSTED_FW_KEY_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&nt_fw_key_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[SOC_FW_CONTENT_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&soc_fw_content_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&tos_fw_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&nt_fw_cert_uuid_spec,
|
||||
open_fip
|
||||
},
|
||||
#endif /* TRUSTED_BOARD_BOOT */
|
||||
};
|
||||
|
||||
static int open_fip(const uintptr_t spec)
|
||||
{
|
||||
int result;
|
||||
uintptr_t local_image_handle;
|
||||
|
||||
/* See if a Firmware Image Package is available */
|
||||
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
|
||||
if (result == 0) {
|
||||
result = io_open(fip_dev_handle, spec, &local_image_handle);
|
||||
if (result == 0) {
|
||||
VERBOSE("Using FIP\n");
|
||||
io_close(local_image_handle);
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifndef IMX_FIP_MMAP
|
||||
static int open_mmc(const uintptr_t spec)
|
||||
{
|
||||
int result;
|
||||
uintptr_t local_handle;
|
||||
|
||||
result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
|
||||
if (result == 0) {
|
||||
result = io_open(mmc_dev_handle, spec, &local_handle);
|
||||
if (result == 0) {
|
||||
io_close(local_handle);
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#else
|
||||
static int open_memmap(const uintptr_t spec)
|
||||
{
|
||||
int result;
|
||||
uintptr_t local_image_handle;
|
||||
|
||||
result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
|
||||
if (result == 0) {
|
||||
result = io_open(memmap_dev_handle, spec, &local_image_handle);
|
||||
if (result == 0) {
|
||||
VERBOSE("Using Memmap\n");
|
||||
io_close(local_image_handle);
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
|
||||
uintptr_t *image_spec)
|
||||
{
|
||||
int result;
|
||||
const struct plat_io_policy *policy;
|
||||
|
||||
assert(image_id < ARRAY_SIZE(policies));
|
||||
|
||||
policy = &policies[image_id];
|
||||
result = policy->check(policy->image_spec);
|
||||
assert(result == 0);
|
||||
|
||||
*image_spec = policy->image_spec;
|
||||
*dev_handle = *policy->dev_handle;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
void plat_imx_io_setup(void)
|
||||
{
|
||||
int result __unused;
|
||||
|
||||
#ifndef IMX_FIP_MMAP
|
||||
result = register_io_dev_block(&mmc_dev_con);
|
||||
assert(result == 0);
|
||||
|
||||
result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
|
||||
&mmc_dev_handle);
|
||||
assert(result == 0);
|
||||
|
||||
#else
|
||||
result = register_io_dev_memmap(&memmap_dev_con);
|
||||
assert(result == 0);
|
||||
|
||||
result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
|
||||
&memmap_dev_handle);
|
||||
assert(result == 0);
|
||||
#endif
|
||||
|
||||
result = register_io_dev_fip(&fip_dev_con);
|
||||
assert(result == 0);
|
||||
|
||||
result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
|
||||
&fip_dev_handle);
|
||||
assert(result == 0);
|
||||
}
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* SDEI configuration for ARM platforms */
|
||||
|
||||
#include <bl31/ehf.h>
|
||||
#include <common/debug.h>
|
||||
#include <services/sdei.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/* Private event mappings */
|
||||
static sdei_ev_map_t imx_sdei_private[] = {
|
||||
SDEI_DEFINE_EVENT_0(PLAT_SDEI_SGI_PRIVATE),
|
||||
};
|
||||
|
||||
/* Shared event mappings */
|
||||
static sdei_ev_map_t imx_sdei_shared[] = {
|
||||
};
|
||||
|
||||
void plat_sdei_setup(void)
|
||||
{
|
||||
INFO("SDEI platform setup\n");
|
||||
}
|
||||
|
||||
/* Export ARM SDEI events */
|
||||
REGISTER_SDEI_MAP(imx_sdei_private, imx_sdei_shared);
|
||||
@@ -0,0 +1,255 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <services/std_svc.h>
|
||||
#include <string.h>
|
||||
#include <platform_def.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <imx_sip_svc.h>
|
||||
#include <lib/el3_runtime/context_mgmt.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <sci/sci.h>
|
||||
|
||||
#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
|
||||
|
||||
#ifdef PLAT_imx8qm
|
||||
const static int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
|
||||
SC_R_A53, SC_R_A72,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int imx_srtc_set_time(uint32_t year_mon,
|
||||
unsigned long day_hour,
|
||||
unsigned long min_sec)
|
||||
{
|
||||
return sc_timer_set_rtc_time(ipc_handle,
|
||||
year_mon >> 16, year_mon & 0xffff,
|
||||
day_hour >> 16, day_hour & 0xffff,
|
||||
min_sec >> 16, min_sec & 0xffff);
|
||||
}
|
||||
|
||||
int imx_srtc_handler(uint32_t smc_fid,
|
||||
void *handle,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (x1) {
|
||||
case IMX_SIP_SRTC_SET_TIME:
|
||||
ret = imx_srtc_set_time(x2, x3, x4);
|
||||
break;
|
||||
default:
|
||||
ret = SMC_UNK;
|
||||
}
|
||||
|
||||
SMC_RET1(handle, ret);
|
||||
}
|
||||
|
||||
static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq)
|
||||
{
|
||||
sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq;
|
||||
|
||||
#ifdef PLAT_imx8qm
|
||||
sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate);
|
||||
#endif
|
||||
#ifdef PLAT_imx8qx
|
||||
sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate);
|
||||
#endif
|
||||
}
|
||||
|
||||
int imx_cpufreq_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3)
|
||||
{
|
||||
switch (x1) {
|
||||
case IMX_SIP_SET_CPUFREQ:
|
||||
imx_cpufreq_set_target(x2, x3);
|
||||
break;
|
||||
default:
|
||||
return SMC_UNK;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool wakeup_src_irqsteer;
|
||||
|
||||
bool imx_is_wakeup_src_irqsteer(void)
|
||||
{
|
||||
return wakeup_src_irqsteer;
|
||||
}
|
||||
|
||||
int imx_wakeup_src_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3)
|
||||
{
|
||||
switch (x1) {
|
||||
case IMX_SIP_WAKEUP_SRC_IRQSTEER:
|
||||
wakeup_src_irqsteer = true;
|
||||
break;
|
||||
case IMX_SIP_WAKEUP_SRC_SCU:
|
||||
wakeup_src_irqsteer = false;
|
||||
break;
|
||||
default:
|
||||
return SMC_UNK;
|
||||
}
|
||||
|
||||
return SMC_OK;
|
||||
}
|
||||
|
||||
int imx_otp_handler(uint32_t smc_fid,
|
||||
void *handle,
|
||||
u_register_t x1,
|
||||
u_register_t x2)
|
||||
{
|
||||
int ret;
|
||||
uint32_t fuse;
|
||||
|
||||
switch (smc_fid) {
|
||||
case IMX_SIP_OTP_READ:
|
||||
ret = sc_misc_otp_fuse_read(ipc_handle, x1, &fuse);
|
||||
SMC_RET2(handle, ret, fuse);
|
||||
break;
|
||||
case IMX_SIP_OTP_WRITE:
|
||||
ret = sc_misc_otp_fuse_write(ipc_handle, x1, x2);
|
||||
SMC_RET1(handle, ret);
|
||||
break;
|
||||
default:
|
||||
ret = SMC_UNK;
|
||||
SMC_RET1(handle, ret);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int imx_misc_set_temp_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4)
|
||||
{
|
||||
return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4);
|
||||
}
|
||||
|
||||
#endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
|
||||
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
|
||||
int imx_src_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
void *handle)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
switch (x1) {
|
||||
case IMX_SIP_SRC_SET_SECONDARY_BOOT:
|
||||
if (x2 != 0U) {
|
||||
mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
|
||||
SRC_GPR10_PERSIST_SECONDARY_BOOT);
|
||||
} else {
|
||||
mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
|
||||
SRC_GPR10_PERSIST_SECONDARY_BOOT);
|
||||
}
|
||||
break;
|
||||
case IMX_SIP_SRC_IS_SECONDARY_BOOT:
|
||||
val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET);
|
||||
return !!(val & SRC_GPR10_PERSIST_SECONDARY_BOOT);
|
||||
default:
|
||||
return SMC_UNK;
|
||||
|
||||
};
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
|
||||
|
||||
static uint64_t imx_get_commit_hash(u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4)
|
||||
{
|
||||
/* Parse the version_string */
|
||||
char *parse = (char *)version_string;
|
||||
uint64_t hash = 0;
|
||||
|
||||
do {
|
||||
parse = strchr(parse, '-');
|
||||
if (parse) {
|
||||
parse += 1;
|
||||
if (*(parse) == 'g') {
|
||||
/* Default is 7 hexadecimal digits */
|
||||
memcpy((void *)&hash, (void *)(parse + 1), 7);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
} while (parse != NULL);
|
||||
|
||||
return hash;
|
||||
}
|
||||
|
||||
uint64_t imx_buildinfo_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
switch (x1) {
|
||||
case IMX_SIP_BUILDINFO_GET_COMMITHASH:
|
||||
ret = imx_get_commit_hash(x2, x3, x4);
|
||||
break;
|
||||
default:
|
||||
return SMC_UNK;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int imx_kernel_entry_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4)
|
||||
{
|
||||
static entry_point_info_t bl33_image_ep_info;
|
||||
entry_point_info_t *next_image_info;
|
||||
unsigned int mode;
|
||||
|
||||
if (x1 < (PLAT_NS_IMAGE_OFFSET & 0xF0000000))
|
||||
return SMC_UNK;
|
||||
|
||||
mode = MODE32_svc;
|
||||
|
||||
next_image_info = &bl33_image_ep_info;
|
||||
|
||||
next_image_info->pc = x1;
|
||||
|
||||
next_image_info->spsr = SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE,
|
||||
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT));
|
||||
|
||||
next_image_info->args.arg0 = 0;
|
||||
next_image_info->args.arg1 = 0;
|
||||
next_image_info->args.arg2 = x3;
|
||||
|
||||
SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE);
|
||||
|
||||
cm_init_my_context(next_image_info);
|
||||
cm_prepare_el3_exit(NON_SECURE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <lib/pmf/pmf.h>
|
||||
#include <tools_share/uuid.h>
|
||||
#include <imx_sip_svc.h>
|
||||
|
||||
static int32_t imx_sip_setup(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uintptr_t imx_sip_handler(unsigned int smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags)
|
||||
{
|
||||
switch (smc_fid) {
|
||||
case IMX_SIP_AARCH32:
|
||||
SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4));
|
||||
break;
|
||||
#if defined(PLAT_imx8mq)
|
||||
case IMX_SIP_GET_SOC_INFO:
|
||||
SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3));
|
||||
break;
|
||||
#endif
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
|
||||
case IMX_SIP_DDR_DVFS:
|
||||
return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
|
||||
case IMX_SIP_GPC:
|
||||
SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
|
||||
break;
|
||||
#endif
|
||||
#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
|
||||
case IMX_SIP_SRTC:
|
||||
return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4);
|
||||
case IMX_SIP_CPUFREQ:
|
||||
SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3));
|
||||
break;
|
||||
case IMX_SIP_WAKEUP_SRC:
|
||||
SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3));
|
||||
case IMX_SIP_OTP_READ:
|
||||
case IMX_SIP_OTP_WRITE:
|
||||
return imx_otp_handler(smc_fid, handle, x1, x2);
|
||||
case IMX_SIP_MISC_SET_TEMP:
|
||||
SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
|
||||
#endif
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
|
||||
case IMX_SIP_SRC:
|
||||
SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
|
||||
break;
|
||||
#endif
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
|
||||
case IMX_SIP_HAB:
|
||||
SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4));
|
||||
break;
|
||||
#endif
|
||||
case IMX_SIP_BUILDINFO:
|
||||
SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
|
||||
default:
|
||||
WARN("Unimplemented i.MX SiP Service Call: 0x%x\n", smc_fid);
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Define a runtime service descriptor for fast SMC calls */
|
||||
DECLARE_RT_SVC(
|
||||
imx_sip_svc,
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
imx_sip_setup,
|
||||
imx_sip_handler
|
||||
);
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <imx_regs.h>
|
||||
#include <imx_snvs.h>
|
||||
|
||||
void imx_snvs_init(void)
|
||||
{
|
||||
struct snvs *snvs = (struct snvs *)SNVS_BASE;
|
||||
uintptr_t addr;
|
||||
uint32_t val;
|
||||
|
||||
addr = (uintptr_t)&snvs->hpcomr;
|
||||
val = mmio_read_32(addr);
|
||||
val |= HPCOMR_NPSWA_EN;
|
||||
mmio_write_32(addr, val);
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <console_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include "imx_uart.h"
|
||||
|
||||
#define URXD 0x0 /* Receiver Register */
|
||||
#define UTXD 0x40 /* Transmitter Register */
|
||||
#define UTS 0xb4 /* UART Test Register (mx31) */
|
||||
#define URXD_RX_DATA (0xFF)
|
||||
|
||||
.globl console_imx_uart_register
|
||||
.globl console_imx_uart_init
|
||||
.globl console_imx_uart_putc
|
||||
.globl console_imx_uart_getc
|
||||
.globl console_imx_uart_flush
|
||||
|
||||
func console_imx_uart_register
|
||||
mov x7, x30
|
||||
mov x6, x3
|
||||
cbz x6, register_fail
|
||||
str x0, [x6, #CONSOLE_T_BASE]
|
||||
|
||||
bl console_imx_uart_init
|
||||
cbz x0, register_fail
|
||||
|
||||
mov x0, x6
|
||||
mov x30, x7
|
||||
finish_console_register imx_uart putc=1, getc=1, flush=1
|
||||
|
||||
register_fail:
|
||||
ret x7
|
||||
endfunc console_imx_uart_register
|
||||
|
||||
func console_imx_uart_init
|
||||
mov w0, #1
|
||||
ret
|
||||
endfunc console_imx_uart_init
|
||||
|
||||
func console_imx_uart_putc
|
||||
ldr x1, [x1, #CONSOLE_T_BASE]
|
||||
cbz x1, putc_error
|
||||
|
||||
/* Prepare '\r' to '\n' */
|
||||
cmp w0, #0xA
|
||||
b.ne 2f
|
||||
1:
|
||||
/* Check if the transmit FIFO is full */
|
||||
ldr w2, [x1, #UTS]
|
||||
tbz w2, #6, 1b
|
||||
mov w2, #0xD
|
||||
str w2, [x1, #UTXD]
|
||||
2:
|
||||
/* Check if the transmit FIFO is full */
|
||||
ldr w2, [x1, #UTS]
|
||||
tbz w2, #6, 2b
|
||||
str w0, [x1, #UTXD]
|
||||
ret
|
||||
putc_error:
|
||||
mov w0, #-1
|
||||
ret
|
||||
endfunc console_imx_uart_putc
|
||||
|
||||
func console_imx_uart_getc
|
||||
ldr x0, [x0, #CONSOLE_T_BASE]
|
||||
cbz x0, getc_error
|
||||
1:
|
||||
ldr w1, [x0, #UTS]
|
||||
tbnz w1, #5, 1b
|
||||
|
||||
ldr w1, [x0, #URXD]
|
||||
and w0, w1, #URXD_RX_DATA
|
||||
|
||||
ret
|
||||
getc_error:
|
||||
mov w0, #-1
|
||||
ret
|
||||
endfunc console_imx_uart_getc
|
||||
|
||||
func console_imx_uart_flush
|
||||
ret
|
||||
endfunc console_imx_uart_flush
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <imx_regs.h>
|
||||
#include <imx_wdog.h>
|
||||
|
||||
static void imx_wdog_power_down(unsigned long base)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)base;
|
||||
|
||||
mmio_write_16((uintptr_t)&wdog->wmcr, 0);
|
||||
}
|
||||
|
||||
void imx_wdog_init(void)
|
||||
{
|
||||
imx_wdog_power_down(WDOG1_BASE);
|
||||
imx_wdog_power_down(WDOG2_BASE);
|
||||
imx_wdog_power_down(WDOG3_BASE);
|
||||
imx_wdog_power_down(WDOG4_BASE);
|
||||
}
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8_IOMUX_H
|
||||
#define IMX8_IOMUX_H
|
||||
|
||||
#define PADRING_IFMUX_EN_SHIFT U(31)
|
||||
#define PADRING_IFMUX_EN_MASK (U(0x1) << PADRING_IFMUX_EN_SHIFT)
|
||||
#define PADRING_GP_EN_SHIFT U(30)
|
||||
#define PADRING_GP_EN_MASK (U(0x1) << PADRING_GP_EN_SHIFT)
|
||||
#define PADRING_IFMUX_SHIFT U(27)
|
||||
#define PADRING_IFMUX_MASK (U(0x7) << PADRING_IFMUX_SHIFT)
|
||||
#define PADRING_CONFIG_SHIFT U(25)
|
||||
#define PADRING_CONFIG_MASK (U(0x3) << PADRING_CONFIG_SHIFT)
|
||||
#define PADRING_LPCONFIG_SHIFT U(23)
|
||||
#define PADRING_LPCONFIG_MASK (U(0x3) << PADRING_LPCONFIG_SHIFT)
|
||||
#define PADRING_PULL_SHIFT U(5)
|
||||
#define PADRING_PULL_MASK (U(0x3) << PADRING_PULL_SHIFT)
|
||||
#define PADRING_DSE_SHIFT U(0)
|
||||
#define PADRING_DSE_MASK (U(0x7) << PADRING_DSE_SHIFT)
|
||||
|
||||
#endif /* IMX8_IOMUX_H */
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8_LPUART_H
|
||||
#define IMX8_LPUART_H
|
||||
|
||||
#include <drivers/console.h>
|
||||
|
||||
#define VERID 0x0
|
||||
#define PARAM 0x4
|
||||
#define GLOBAL 0x8
|
||||
#define PINCFG 0xC
|
||||
#define BAUD 0x10
|
||||
#define STAT 0x14
|
||||
#define CTRL 0x18
|
||||
#define DATA 0x1C
|
||||
#define MATCH 0x20
|
||||
#define MODIR 0x24
|
||||
#define FIFO 0x28
|
||||
#define WATER 0x2c
|
||||
|
||||
#define US1_TDRE (1 << 23)
|
||||
#define US1_RDRF (1 << 21)
|
||||
|
||||
#define CTRL_TE (1 << 19)
|
||||
#define CTRL_RE (1 << 18)
|
||||
|
||||
#define FIFO_TXFE 0x80
|
||||
#define FIFO_RXFE 0x40
|
||||
|
||||
#define WATER_TXWATER_OFF 1
|
||||
#define WATER_RXWATER_OFF 16
|
||||
|
||||
#define LPUART_CTRL_PT_MASK 0x1
|
||||
#define LPUART_CTRL_PE_MASK 0x2
|
||||
#define LPUART_CTRL_M_MASK 0x10
|
||||
|
||||
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
|
||||
#define LPUART_BAUD_OSR_SHIFT (24U)
|
||||
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
|
||||
|
||||
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
|
||||
#define LPUART_BAUD_SBR_SHIFT (0U)
|
||||
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
|
||||
|
||||
#define LPUART_BAUD_SBNS_MASK (0x2000U)
|
||||
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
|
||||
#define LPUART_BAUD_M10_MASK (0x20000000U)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
int console_lpuart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
|
||||
console_t *console);
|
||||
#endif /*__ASSEMBLER__*/
|
||||
|
||||
#endif /* IMX8_LPUART_H */
|
||||
@@ -0,0 +1,293 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file used to configure SoC pad list.
|
||||
*/
|
||||
|
||||
#ifndef IMX8QM_PADS_H
|
||||
#define IMX8QM_PADS_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Pad Definitions
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
|
||||
#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
|
||||
#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
|
||||
#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
|
||||
#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
|
||||
#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */
|
||||
#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
|
||||
#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
|
||||
#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
|
||||
#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
|
||||
#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
|
||||
#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
|
||||
#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
|
||||
#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
|
||||
#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
|
||||
#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
|
||||
#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
|
||||
#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
|
||||
#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
|
||||
#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
|
||||
#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
|
||||
#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
|
||||
#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
|
||||
#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
|
||||
#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
|
||||
#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
|
||||
#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
|
||||
#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */
|
||||
#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
|
||||
#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */
|
||||
#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */
|
||||
#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */
|
||||
#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */
|
||||
#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */
|
||||
#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
|
||||
#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
|
||||
#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
|
||||
#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
|
||||
#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
|
||||
#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
|
||||
#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
|
||||
#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
|
||||
#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */
|
||||
#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */
|
||||
#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */
|
||||
#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */
|
||||
#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
|
||||
#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
|
||||
#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
|
||||
#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
|
||||
#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
|
||||
#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
|
||||
#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
|
||||
#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
|
||||
#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
|
||||
#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
|
||||
#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
|
||||
#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
|
||||
#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
|
||||
#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
|
||||
#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
|
||||
#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
|
||||
#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
|
||||
#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
|
||||
#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
|
||||
#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
|
||||
#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
|
||||
#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */
|
||||
#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
|
||||
#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
|
||||
#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
|
||||
#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
|
||||
#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
|
||||
#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
|
||||
#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
|
||||
#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
|
||||
#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
|
||||
#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
|
||||
#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
|
||||
#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
|
||||
#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
|
||||
#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
|
||||
#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
|
||||
#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
|
||||
#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
|
||||
#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */
|
||||
#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
|
||||
#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
|
||||
#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
|
||||
#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
|
||||
#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
|
||||
#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
|
||||
#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
|
||||
#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
|
||||
#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
|
||||
#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
|
||||
#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
|
||||
#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */
|
||||
#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
|
||||
#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
|
||||
#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
|
||||
#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
|
||||
#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
|
||||
#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
|
||||
#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
|
||||
#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
|
||||
#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
|
||||
#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
|
||||
#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
|
||||
#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
|
||||
#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
|
||||
#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
|
||||
#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
|
||||
#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */
|
||||
#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
|
||||
#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
|
||||
#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
|
||||
#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
|
||||
#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
|
||||
#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
|
||||
#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
|
||||
#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
|
||||
#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
|
||||
#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
|
||||
#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */
|
||||
#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
|
||||
#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
|
||||
#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
|
||||
#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
|
||||
#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
|
||||
#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */
|
||||
#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
|
||||
#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
|
||||
#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
|
||||
#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
|
||||
#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */
|
||||
#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
|
||||
#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
|
||||
#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
|
||||
#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
|
||||
#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
|
||||
#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */
|
||||
#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
|
||||
#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
|
||||
#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
|
||||
#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
|
||||
#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
|
||||
#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */
|
||||
#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
|
||||
#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
|
||||
#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
|
||||
#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
|
||||
#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
|
||||
#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
|
||||
#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
|
||||
#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */
|
||||
#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */
|
||||
#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */
|
||||
#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */
|
||||
#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */
|
||||
#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */
|
||||
#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */
|
||||
#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
|
||||
#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */
|
||||
#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */
|
||||
#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */
|
||||
#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */
|
||||
#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */
|
||||
#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */
|
||||
#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */
|
||||
#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */
|
||||
#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
|
||||
#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
|
||||
#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
|
||||
#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
|
||||
#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */
|
||||
#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
|
||||
#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
|
||||
#define SC_P_CALIBRATION_0_HSIC 207 /* */
|
||||
#define SC_P_CALIBRATION_1_HSIC 208 /* */
|
||||
#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */
|
||||
#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
|
||||
#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
|
||||
#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
|
||||
#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
|
||||
#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
|
||||
#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
|
||||
#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
|
||||
#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
|
||||
#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
|
||||
#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
|
||||
#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */
|
||||
#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */
|
||||
#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
|
||||
#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
|
||||
#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
|
||||
#define SC_P_CTL_NAND_RE_P_N 226 /* */
|
||||
#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
|
||||
#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
|
||||
#define SC_P_CTL_NAND_DQS_P_N 229 /* */
|
||||
#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
|
||||
#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
|
||||
#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
|
||||
#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
|
||||
#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */
|
||||
#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
|
||||
#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
|
||||
#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
|
||||
#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
|
||||
#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
|
||||
#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */
|
||||
#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
|
||||
#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
|
||||
#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
|
||||
#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
|
||||
#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
|
||||
#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
|
||||
#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
|
||||
#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
|
||||
#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
|
||||
#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
|
||||
#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
|
||||
#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */
|
||||
#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
|
||||
#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
|
||||
#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
|
||||
#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
|
||||
#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
|
||||
#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
|
||||
#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
|
||||
#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
|
||||
#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
|
||||
#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
|
||||
#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
|
||||
#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */
|
||||
/*@}*/
|
||||
|
||||
#endif /* IMX8QM_PADS_H */
|
||||
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file used to configure SoC pad list.
|
||||
*/
|
||||
|
||||
#ifndef IMX8QX_PADS_H
|
||||
#define IMX8QX_PADS_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Pad Definitions
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */
|
||||
#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
|
||||
#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
|
||||
#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
|
||||
#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
|
||||
#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */
|
||||
#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
|
||||
#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
|
||||
#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
|
||||
#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
|
||||
#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
|
||||
#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */
|
||||
#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
|
||||
#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
|
||||
#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
|
||||
#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
|
||||
#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
|
||||
#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */
|
||||
#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
|
||||
#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
|
||||
#define SC_P_CTL_NAND_RE_P_N 25 /* */
|
||||
#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
|
||||
#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
|
||||
#define SC_P_CTL_NAND_DQS_P_N 28 /* */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */
|
||||
#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
|
||||
#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
|
||||
#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
|
||||
#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
|
||||
#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
|
||||
#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */
|
||||
#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
|
||||
#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
|
||||
#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
|
||||
#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
|
||||
#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
|
||||
#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */
|
||||
#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
|
||||
#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
|
||||
#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
|
||||
#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
|
||||
#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
|
||||
#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */
|
||||
#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
|
||||
#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
|
||||
#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */
|
||||
#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
|
||||
#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
|
||||
#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
|
||||
#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
|
||||
#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
|
||||
#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
|
||||
#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
|
||||
#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
|
||||
#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
|
||||
#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
|
||||
#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
|
||||
#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
|
||||
#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */
|
||||
#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
|
||||
#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
|
||||
#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
|
||||
#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
|
||||
#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
|
||||
#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
|
||||
#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
|
||||
#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
|
||||
#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
|
||||
#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
|
||||
#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
|
||||
#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */
|
||||
#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
|
||||
#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
|
||||
#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
|
||||
#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
|
||||
#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
|
||||
#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
|
||||
#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
|
||||
#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
|
||||
#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
|
||||
#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
|
||||
#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
|
||||
#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
|
||||
#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
|
||||
#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
|
||||
#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
|
||||
#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */
|
||||
#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
|
||||
#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
|
||||
#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
|
||||
#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
|
||||
#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
|
||||
#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
|
||||
#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
|
||||
#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
|
||||
#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
|
||||
#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
|
||||
#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
|
||||
#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
|
||||
#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
|
||||
#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
|
||||
#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
|
||||
#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */
|
||||
#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
|
||||
#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
|
||||
#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
|
||||
#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */
|
||||
#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
|
||||
#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
|
||||
#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */
|
||||
#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */
|
||||
#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */
|
||||
#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
|
||||
#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
|
||||
#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */
|
||||
#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */
|
||||
#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */
|
||||
#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */
|
||||
#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */
|
||||
#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */
|
||||
#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
|
||||
#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */
|
||||
#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
|
||||
#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */
|
||||
#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
|
||||
#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
|
||||
#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
|
||||
#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
|
||||
#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
|
||||
#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
|
||||
#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
|
||||
#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
|
||||
#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
|
||||
#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
|
||||
#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
|
||||
#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */
|
||||
#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
|
||||
#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
|
||||
#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
|
||||
#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
|
||||
#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
|
||||
#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
|
||||
#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
|
||||
#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */
|
||||
/*@}*/
|
||||
|
||||
#endif /* IMX8QX_PADS_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_AIPS_H
|
||||
#define IMX_AIPS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define AIPSTZ_OAPCR_COUNT 0x05
|
||||
|
||||
struct aipstz_regs {
|
||||
uint32_t aipstz_mpr;
|
||||
uint32_t res[15];
|
||||
uint32_t aipstz_opacr[AIPSTZ_OAPCR_COUNT];
|
||||
};
|
||||
|
||||
void imx_aips_init(void);
|
||||
|
||||
#endif /* IMX_AIPS_H */
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_CAAM_H
|
||||
#define IMX_CAAM_H
|
||||
|
||||
#include <cdefs.h>
|
||||
#include <stdint.h>
|
||||
#include <arch.h>
|
||||
#include <imx_regs.h>
|
||||
|
||||
struct caam_job_ring {
|
||||
uint32_t jrmidr_ms;
|
||||
uint32_t jrmidr_ls;
|
||||
};
|
||||
|
||||
struct caam_rtic_mid {
|
||||
uint32_t rticmidr_ms;
|
||||
uint32_t rticmidr_ls;
|
||||
};
|
||||
|
||||
struct caam_deco {
|
||||
uint32_t deco_mid_ms;
|
||||
uint32_t deco_mid_ls;
|
||||
};
|
||||
|
||||
#define JOB_RING_OFFSET 0x10
|
||||
#define DEBUGCTL_OFFSET 0x58
|
||||
#define RES2_SIZE (DEBUGCTL_OFFSET - JOB_RING_OFFSET - \
|
||||
(sizeof(struct caam_job_ring) * CAAM_NUM_JOB_RINGS))
|
||||
|
||||
#define RTIC_MID_OFFSET 0x60
|
||||
#define DECORR_OFFSET 0x9C
|
||||
#define RES3_SIZE (DECORR_OFFSET - RTIC_MID_OFFSET - \
|
||||
(sizeof(struct caam_rtic_mid) * CAAM_NUM_RTIC))
|
||||
|
||||
#define DECO_MID_OFFSET 0xA0
|
||||
#define DAR_OFFSET 0x120
|
||||
#define RES4_SIZE (DAR_OFFSET - DECO_MID_OFFSET - \
|
||||
(sizeof(struct caam_deco) * CAAM_NUM_DECO))
|
||||
|
||||
struct caam_ctrl {
|
||||
uint32_t res0;
|
||||
uint32_t mcfgr;
|
||||
uint32_t res1;
|
||||
uint32_t scfgr;
|
||||
struct caam_job_ring jr[CAAM_NUM_JOB_RINGS];
|
||||
uint8_t res2[RES2_SIZE];
|
||||
uint32_t debuctl;
|
||||
uint32_t jrstartr;
|
||||
struct caam_rtic_mid mid[CAAM_NUM_RTIC];
|
||||
uint8_t res3[RES3_SIZE];
|
||||
uint32_t decorr;
|
||||
struct caam_deco deco[CAAM_NUM_DECO];
|
||||
uint8_t res4[RES4_SIZE];
|
||||
uint32_t dar;
|
||||
uint32_t drr;
|
||||
} __packed;
|
||||
|
||||
/* Job ring control bits */
|
||||
#define JROWN_NS BIT(3)
|
||||
#define JROWN_MID 0x01
|
||||
|
||||
/* Declare CAAM API */
|
||||
void imx_caam_init(void);
|
||||
|
||||
#endif /* IMX_CAAM_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef IMX_CSU_H
|
||||
#define IMX_CSU_H
|
||||
|
||||
#include <arch.h>
|
||||
|
||||
/*
|
||||
* Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
|
||||
* Rev. 0, 03/2017 Section 3.3.1
|
||||
*
|
||||
* Config secure level register (CSU_CSLn)
|
||||
*/
|
||||
#define CSU_CSL_LOCK_S1 BIT(24)
|
||||
#define CSU_CSL_NSW_S1 BIT(23)
|
||||
#define CSU_CSL_NUW_S1 BIT(22)
|
||||
#define CSU_CSL_SSW_S1 BIT(21)
|
||||
#define CSU_CSL_SUW_S1 BIT(20)
|
||||
#define CSU_CSL_NSR_S1 BIT(19)
|
||||
#define CSU_CSL_NUR_S1 BIT(18)
|
||||
#define CSU_CSL_SSR_S1 BIT(17)
|
||||
#define CSU_CSL_SUR_S1 BIT(16)
|
||||
#define CSU_CSL_LOCK_S2 BIT(8)
|
||||
#define CSU_CSL_NSW_S2 BIT(7)
|
||||
#define CSU_CSL_NUW_S2 BIT(6)
|
||||
#define CSU_CSL_SSW_S2 BIT(5)
|
||||
#define CSU_CSL_SUW_S2 BIT(4)
|
||||
#define CSU_CSL_NSR_S2 BIT(3)
|
||||
#define CSU_CSL_NUR_S2 BIT(2)
|
||||
#define CSU_CSL_SSR_S2 BIT(1)
|
||||
#define CSU_CSL_SUR_S2 BIT(0)
|
||||
|
||||
#define CSU_CSL_OPEN_ACCESS (CSU_CSL_NSW_S1 | CSU_CSL_NUW_S1 | CSU_CSL_SSW_S1 |\
|
||||
CSU_CSL_SUW_S1 | CSU_CSL_NSR_S1 | CSU_CSL_NUR_S1 |\
|
||||
CSU_CSL_SSR_S1 | CSU_CSL_SUR_S1 | CSU_CSL_NSW_S2 |\
|
||||
CSU_CSL_NUW_S2 | CSU_CSL_SSW_S2 | CSU_CSL_SUW_S2 |\
|
||||
CSU_CSL_NSR_S2 | CSU_CSL_NUR_S2 | CSU_CSL_SSR_S2 |\
|
||||
CSU_CSL_SUR_S2)
|
||||
void imx_csu_init(void);
|
||||
|
||||
#endif /* IMX_CSU_H */
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef IMX_HAB_H
|
||||
#define IMX_HAB_H
|
||||
|
||||
#include <imx_hab_arch.h>
|
||||
#include <imx_regs.h>
|
||||
|
||||
#define HAB_ROM_VECTOR_BASE\
|
||||
(BOOTROM_BASE + HAB_CALLBACK_OFFSET)
|
||||
/*
|
||||
* Section 4.5 of the High Assurance Boot Version 4 Application Programming
|
||||
* Interface Reference Manual defines the ROM Vector table as coming after a 4
|
||||
* byte header
|
||||
*
|
||||
* A series of function pointers are enumerated at fixed addresses, which are
|
||||
* described below
|
||||
*/
|
||||
#define HAB_ROM_VECTOR_TABLE_ENTRY (HAB_ROM_VECTOR_BASE + 0x04)
|
||||
#define HAB_ROM_VECTOR_TABLE_EXIT (HAB_ROM_VECTOR_BASE + 0x08)
|
||||
#define HAB_ROM_VECTOR_TABLE_CHECK_TARGET (HAB_ROM_VECTOR_BASE + 0x0C)
|
||||
#define HAB_ROM_VECTOR_TABLE_AUTHENTICATE_IMAGE (HAB_ROM_VECTOR_BASE + 0x10)
|
||||
#define HAB_ROM_VECTOR_TABLE_RUN_DCD (HAB_ROM_VECTOR_BASE + 0x14)
|
||||
#define HAB_ROM_VECTOR_TABLE_RUN_CSF (HAB_ROM_VECTOR_BASE + 0x18)
|
||||
#define HAB_ROM_VECTOR_TABLE_ASSERT (HAB_ROM_VECTOR_BASE + 0x1C)
|
||||
#define HAB_ROM_VECTOR_TABLE_REPORT_EVENT (HAB_ROM_VECTOR_BASE + 0x20)
|
||||
#define HAB_ROM_VECTOR_TABLE_REPORT_STATUS (HAB_ROM_VECTOR_BASE + 0x24)
|
||||
#define HAB_ROM_VECTOR_TABLE_FAILSAFE (HAB_ROM_VECTOR_BASE + 0x28)
|
||||
|
||||
#endif /* IMX_HAB_H */
|
||||
@@ -0,0 +1,652 @@
|
||||
/*
|
||||
* Copyright 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_IO_MUX_H
|
||||
#define IMX_IO_MUX_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*
|
||||
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
|
||||
* Section 8.2.7 IOMUXC Memory Map/Register Definition
|
||||
*/
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_OFFSET 0x0014
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_OFFSET 0x0018
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_OFFSET 0x001C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0)
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_OFFSET 0x0038
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_OFFSET 0x003C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_OFFSET 0x0040
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_OFFSET 0x0044
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_OFFSET 0x0048
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_OFFSET 0x004C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_OFFSET 0x0050
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_OFFSET 0x0054
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_OFFSET 0x0058
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_OFFSET 0x005C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_OFFSET 0x0060
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_OFFSET 0x0064
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_OFFSET 0x0068
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_OFFSET 0x006C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_OFFSET 0x0070
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_OFFSET 0x0074
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_OFFSET 0x0078
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_OFFSET 0x007C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_OFFSET 0x0080
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_OFFSET 0x0084
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_OFFSET 0x0088
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_OFFSET 0x008C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_OFFSET 0x0090
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_OFFSET 0x0094
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_OFFSET 0x0098
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_OFFSET 0x009C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_OFFSET 0x00A0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_OFFSET 0x00A4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_OFFSET 0x00A8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_OFFSET 0x00AC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x00B0
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_OFFSET 0x00B4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_OFFSET 0x00B8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_OFFSET 0x00BC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_OFFSET 0x00C0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_OFFSET 0x00C4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_OFFSET 0x00C8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_OFFSET 0x00CC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_OFFSET 0x00D0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_OFFSET 0x00D4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_OFFSET 0x00D8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_OFFSET 0x00DC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_OFFSET 0x00E0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_OFFSET 0x00E4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_OFFSET 0x00E8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_OFFSET 0x00EC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_OFFSET 0x00F0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_OFFSET 0x00F4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_OFFSET 0x00F8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_OFFSET 0x00FC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_OFFSET 0x0100
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_OFFSET 0x0104
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_OFFSET 0x0108
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_OFFSET 0x010C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_OFFSET 0x0110
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_OFFSET 0x0114
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_OFFSET 0x0118
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_OFFSET 0x011C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_OFFSET 0x0120
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_OFFSET 0x0124
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET 0x0128
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 0x00
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET 0x012C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 0x00
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT3_ECSPI1_SS2 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT4_ENET2_1588_EVENT0_OUT BIT(3)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT5_GPIO4_IO1 (BIT(2) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT6_ENET1_MDC (BIT(2) | BIT(1))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION BIT(3)
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_OFFSET 0x0130
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_OFFSET 0x0134
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_OFFSET 0x0138
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_OFFSET 0x013C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_OFFSET 0x0140
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_OFFSET 0x0144
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_OFFSET 0x0148
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_OFFSET 0x014C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_OFFSET 0x0150
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT0_I2C4_SCL 0x0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA BIT(0)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT2_WDOG4_WDOG_B BIT(1)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT4_USB_OTG1_ID BIT(2)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14 (BIT(2) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0 (BIT(2) | BIT(1))
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT0_I2C4_SDA 0x0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA BIT(0)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT2_WDOG4_WDOG_RST_B_DEB BIT(1)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT4_USB_OTG2_ID BIT(2)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1 (BIT(2) | BIT(1))
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA BIT(0)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT2_SD2_DATA4 BIT(1)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT3_CSI_DATA2 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT5_GPIO4_IO16 (BIT(2) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT6_EPDC_PWR_COM (BIT(2) | (BIT(1))
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET 0x016C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT0_ECSPI1_MOSI 0x00
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA BIT(0)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT2_SD2_DATA5 BIT(1)
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT3_CSI_DATA3 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT5_GPIO4_IO17 (BIT(2) | BIT(0))
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT6_EPDC_PWR_STAT (BIT(2) | (BIT(1))
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_OFFSET 0x0170
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_OFFSET 0x0174
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_OFFSET 0x0178
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_OFFSET 0x017C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_OFFSET 0x0180
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_OFFSET 0x0184
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_OFFSET 0x0188
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_OFFSET 0x018C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_OFFSET 0x0190
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_OFFSET 0x0194
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_OFFSET 0x0198
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_OFFSET 0x019C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_OFFSET 0x01A0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_OFFSET 0x01A4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_OFFSET 0x01A8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_OFFSET 0x01AC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_OFFSET 0x01B0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_OFFSET 0x01B4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_OFFSET 0x01B8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_OFFSET 0x01BC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_OFFSET 0x01C0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET 0x01DC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET 0x01E0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET 0x01E4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET 0x01E8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET 0x01EC
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET 0x01F0
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET 0x01F4
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_OFFSET 0x01F8
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_OFFSET 0x01FC
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0200
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0204
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0208
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_OFFSET 0x020C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0210
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0214
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_OFFSET 0x0218
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x021C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0220
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0224
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0228
|
||||
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x022C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x0230
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x0234
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x0238
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x023C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x0240
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x0244
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x0248
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x024C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x0250
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x0254
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x0258
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_OFFSET 0x025C
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_OFFSET 0x0260
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_OFFSET 0x0264
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_OFFSET 0x0268
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_OFFSET 0x026C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_OFFSET 0x0270
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_OFFSET 0x0274
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_OFFSET 0x0278
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_OFFSET 0x027C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_OFFSET 0x0280
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET 0x0284
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_OFFSET 0x0288
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_OFFSET 0x028C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_OFFSET 0x0290
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_OFFSET 0x0294
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_OFFSET 0x0298
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_OFFSET 0x029C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_OFFSET 0x02A0
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_OFFSET 0x02A4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_OFFSET 0x02A8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_OFFSET 0x02AC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_OFFSET 0x02B0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_OFFSET 0x02B4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_OFFSET 0x02B8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_OFFSET 0x02BC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_OFFSET 0x02C0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_OFFSET 0x02C4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_OFFSET 0x02C8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_OFFSET 0x02CC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_OFFSET 0x02D0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_OFFSET 0x02D4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_OFFSET 0x02D8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_OFFSET 0x02DC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_OFFSET 0x02E0
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_OFFSET 0x02E4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_OFFSET 0x02E8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_OFFSET 0x02EC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_OFFSET 0x02F0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_OFFSET 0x02F4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_OFFSET 0x02F8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_OFFSET 0x02FC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_OFFSET 0x0300
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_OFFSET 0x0304
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_OFFSET 0x0308
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_OFFSET 0x030C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_OFFSET 0x0310
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_OFFSET 0x0314
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_OFFSET 0x0318
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_OFFSET 0x031C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x0320
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_OFFSET 0x0324
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_OFFSET 0x0328
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_OFFSET 0x032C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_OFFSET 0x0330
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_OFFSET 0x0334
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_OFFSET 0x0338
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_OFFSET 0x033C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_OFFSET 0x0340
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_OFFSET 0x0344
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_OFFSET 0x0348
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_OFFSET 0x034C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_OFFSET 0x0350
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_OFFSET 0x0354
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_OFFSET 0x0358
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_OFFSET 0x035C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_OFFSET 0x0360
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_OFFSET 0x0364
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_OFFSET 0x0368
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_OFFSET 0x036C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_OFFSET 0x0370
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_OFFSET 0x0374
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_OFFSET 0x0378
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_OFFSET 0x037C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_OFFSET 0x0380
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_OFFSET 0x0384
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_OFFSET 0x0388
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_OFFSET 0x038C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_OFFSET 0x0390
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_OFFSET 0x0394
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET 0x0398
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_0_X1 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4 BIT(0)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_2_X2 BIT(1)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_FAST 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SLOW BIT(2)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN BIT(3)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN BIT(4)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_0_100K_PD 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_1_5K_PU BIT(5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_2_47K_PU BIT(6)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET 0x039C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_0_X1 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4 BIT(0)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_2_X2 BIT(1)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_FAST 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SLOW BIT(2)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN BIT(3)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN BIT(4)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_0_100K_PD 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_1_5K_PU BIT(5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_2_47K_PU BIT(6)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_OFFSET 0x03A0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_OFFSET 0x03A4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_OFFSET 0x03A8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_OFFSET 0x03AC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_OFFSET 0x03B0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_OFFSET 0x03B4
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_OFFSET 0x03B8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_OFFSET 0x03BC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_OFFSET 0x03C0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_OFFSET 0x03C4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_OFFSET 0x03C8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_OFFSET 0x03CC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_OFFSET 0x03D0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_OFFSET 0x03D4
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET 0x03D8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_0_X1 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4 BIT(0)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_2_X2 BIT(1)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_3_X6 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_FAST 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SLOW BIT(2)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN BIT(3)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN BIT(4)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_0_100K_PD 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_1_5K_PU BIT(5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_2_47K_PU BIT(6)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU (BIT(6) | BIT(5))
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET 0x03DC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_0_X1 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4 BIT(0)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_2_X2 BIT(1)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_3_X6 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_FAST 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SLOW BIT(2)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN BIT(3)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_DIS 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN BIT(4)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_0_100K_PD 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_1_5K_PU BIT(5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_2_47K_PU BIT(6)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU (BIT(6) | BIT(5))
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_OFFSET 0x03E0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_OFFSET 0x03E4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_OFFSET 0x03E8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_OFFSET 0x03EC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_OFFSET 0x03F0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_OFFSET 0x03F4
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_OFFSET 0x03F8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_OFFSET 0x03FC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_OFFSET 0x0400
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_OFFSET 0x0404
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_OFFSET 0x0408
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_OFFSET 0x040C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_OFFSET 0x0410
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_OFFSET 0x0414
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_OFFSET 0x0418
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_OFFSET 0x041C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_OFFSET 0x0420
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_OFFSET 0x0424
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_OFFSET 0x0428
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_OFFSET 0x042C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_OFFSET 0x0430
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET 0x044C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET 0x0450
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET 0x0454
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET 0x0458
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET 0x045C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET 0x0460
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_0_X1 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_2_X2 BIT(1)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_1_X4 BIT(0)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW BIT(2)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_FAST 0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_HYS BIT(3)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_PE BIT(4)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_PD_100K (0 << 5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_5K (1 << 5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K (2 << 5)
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_PU_100K (3 << 5)
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0478
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_OFFSET 0x047C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0480
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0484
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_OFFSET 0x0488
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x048C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0490
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0494
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0498
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x049C
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x04A0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x04A4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x04A8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x04AC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x04B0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x04B4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x04B8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x04BC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x04C0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x04C4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x04C8
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_OFFSET 0x04CC
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_OFFSET 0x04D0
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_OFFSET 0x04D4
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_OFFSET 0x04D8
|
||||
|
||||
#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_OFFSET 0x04DC
|
||||
#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_OFFSET 0x04E0
|
||||
|
||||
#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_OFFSET 0x04E4
|
||||
#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_OFFSET 0x04E8
|
||||
#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_OFFSET 0x04EC
|
||||
#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_OFFSET 0x04F0
|
||||
|
||||
#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_OFFSET 0x04F4
|
||||
|
||||
#define IOMUXC_CSI_DATA2_SELECT_INPUT_OFFSET 0x04F8
|
||||
#define IOMUXC_CSI_DATA3_SELECT_INPUT_OFFSET 0x04FC
|
||||
#define IOMUXC_CSI_DATA4_SELECT_INPUT_OFFSET 0x0500
|
||||
#define IOMUXC_CSI_DATA5_SELECT_INPUT_OFFSET 0x0504
|
||||
#define IOMUXC_CSI_DATA6_SELECT_INPUT_OFFSET 0x0508
|
||||
#define IOMUXC_CSI_DATA7_SELECT_INPUT_OFFSET 0x050C
|
||||
#define IOMUXC_CSI_DATA8_SELECT_INPUT_OFFSET 0x0510
|
||||
#define IOMUXC_CSI_DATA9_SELECT_INPUT_OFFSET 0x0514
|
||||
#define IOMUXC_CSI_HSYNC_SELECT_INPUT_OFFSET 0x0518
|
||||
#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_OFFSET 0x051C
|
||||
#define IOMUXC_CSI_VSYNC_SELECT_INPUT_OFFSET 0x0520
|
||||
|
||||
#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_OFFSET 0x0524
|
||||
#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_OFFSET 0x0528
|
||||
#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_OFFSET 0x052C
|
||||
#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_OFFSET 0x0530
|
||||
#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_OFFSET 0x0534
|
||||
#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_OFFSET 0x0538
|
||||
#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_OFFSET 0x053C
|
||||
#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_OFFSET 0x0540
|
||||
#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_OFFSET 0x0544
|
||||
#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_OFFSET 0x0548
|
||||
#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_OFFSET 0x054C
|
||||
#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_OFFSET 0x0550
|
||||
#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_OFFSET 0x0554
|
||||
#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_OFFSET 0x0558
|
||||
#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_OFFSET 0x055C
|
||||
#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_OFFSET 0x0560
|
||||
|
||||
#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_OFFSET 0x0564
|
||||
#define IOMUXC_ENET1_MDIO_SELECT_INPUT_OFFSET 0x0568
|
||||
#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_OFFSET 0x056C
|
||||
#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_OFFSET 0x0570
|
||||
#define IOMUXC_ENET2_MDIO_SELECT_INPUT_OFFSET 0x0574
|
||||
#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_OFFSET 0x0578
|
||||
|
||||
#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_OFFSET 0x057C
|
||||
#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_OFFSET 0x0580
|
||||
|
||||
#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_OFFSET 0x0584
|
||||
#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_OFFSET 0x0588
|
||||
#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_OFFSET 0x058C
|
||||
#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_OFFSET 0x0590
|
||||
#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_OFFSET 0x0594
|
||||
#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_OFFSET 0x0598
|
||||
#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_OFFSET 0x059C
|
||||
#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_OFFSET 0x05A0
|
||||
#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_OFFSET 0x05A4
|
||||
#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_OFFSET 0x05A8
|
||||
#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_OFFSET 0x05AC
|
||||
#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_OFFSET 0x05B0
|
||||
#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_OFFSET 0x05B4
|
||||
#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_OFFSET 0x05B8
|
||||
#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_OFFSET 0x05BC
|
||||
#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_OFFSET 0x05C0
|
||||
#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_OFFSET 0x05C4
|
||||
#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_OFFSET 0x05C8
|
||||
#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_OFFSET 0x05CC
|
||||
#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_OFFSET 0x05D0
|
||||
|
||||
#define IOMUXC_I2C1_SCL_SELECT_INPUT_OFFSET 0x05D4
|
||||
#define IOMUXC_I2C1_SDA_SELECT_INPUT_OFFSET 0x05D8
|
||||
#define IOMUXC_I2C2_SCL_SELECT_INPUT_OFFSET 0x05DC
|
||||
#define IOMUXC_I2C2_SDA_SELECT_INPUT_OFFSET 0x05E0
|
||||
#define IOMUXC_I2C3_SCL_SELECT_INPUT_OFFSET 0x05E4
|
||||
#define IOMUXC_I2C3_SDA_SELECT_INPUT_OFFSET 0x05E8
|
||||
#define IOMUXC_I2C4_SCL_SELECT_INPUT_OFFSET 0x05EC
|
||||
#define IOMUXC_I2C4_SDA_SELECT_INPUT_OFFSET 0x05F0
|
||||
|
||||
#define IOMUXC_KPP_COL0_SELECT_INPUT_OFFSET 0x05F4
|
||||
#define IOMUXC_KPP_COL1_SELECT_INPUT_OFFSET 0x05F8
|
||||
#define IOMUXC_KPP_COL2_SELECT_INPUT_OFFSET 0x05FC
|
||||
#define IOMUXC_KPP_COL3_SELECT_INPUT_OFFSET 0x0600
|
||||
#define IOMUXC_KPP_COL4_SELECT_INPUT_OFFSET 0x0604
|
||||
#define IOMUXC_KPP_COL5_SELECT_INPUT_OFFSET 0x0608
|
||||
#define IOMUXC_KPP_COL6_SELECT_INPUT_OFFSET 0x060C
|
||||
#define IOMUXC_KPP_COL7_SELECT_INPUT_OFFSET 0x0610
|
||||
#define IOMUXC_KPP_ROW0_SELECT_INPUT_OFFSET 0x0614
|
||||
#define IOMUXC_KPP_ROW1_SELECT_INPUT_OFFSET 0x0618
|
||||
#define IOMUXC_KPP_ROW2_SELECT_INPUT_OFFSET 0x061C
|
||||
#define IOMUXC_KPP_ROW3_SELECT_INPUT_OFFSET 0x0620
|
||||
#define IOMUXC_KPP_ROW4_SELECT_INPUT_OFFSET 0x0624
|
||||
#define IOMUXC_KPP_ROW5_SELECT_INPUT_OFFSET 0x0628
|
||||
#define IOMUXC_KPP_ROW6_SELECT_INPUT_OFFSET 0x062C
|
||||
#define IOMUXC_KPP_ROW7_SELECT_INPUT_OFFSET 0x0630
|
||||
|
||||
#define IOMUXC_LCD_BUSY_SELECT_INPUT_OFFSET 0x0634
|
||||
#define IOMUXC_LCD_DATA00_SELECT_INPUT_OFFSET 0x0638
|
||||
#define IOMUXC_LCD_DATA01_SELECT_INPUT_OFFSET 0x063C
|
||||
#define IOMUXC_LCD_DATA02_SELECT_INPUT_OFFSET 0x0640
|
||||
#define IOMUXC_LCD_DATA03_SELECT_INPUT_OFFSET 0x0644
|
||||
#define IOMUXC_LCD_DATA04_SELECT_INPUT_OFFSET 0x0648
|
||||
#define IOMUXC_LCD_DATA05_SELECT_INPUT_OFFSET 0x064C
|
||||
#define IOMUXC_LCD_DATA06_SELECT_INPUT_OFFSET 0x0650
|
||||
#define IOMUXC_LCD_DATA07_SELECT_INPUT_OFFSET 0x0654
|
||||
#define IOMUXC_LCD_DATA08_SELECT_INPUT_OFFSET 0x0658
|
||||
#define IOMUXC_LCD_DATA09_SELECT_INPUT_OFFSET 0x065C
|
||||
#define IOMUXC_LCD_DATA10_SELECT_INPUT_OFFSET 0x0660
|
||||
#define IOMUXC_LCD_DATA11_SELECT_INPUT_OFFSET 0x0664
|
||||
#define IOMUXC_LCD_DATA12_SELECT_INPUT_OFFSET 0x0668
|
||||
#define IOMUXC_LCD_DATA13_SELECT_INPUT_OFFSET 0x066C
|
||||
#define IOMUXC_LCD_DATA14_SELECT_INPUT_OFFSET 0x0670
|
||||
#define IOMUXC_LCD_DATA15_SELECT_INPUT_OFFSET 0x0674
|
||||
#define IOMUXC_LCD_DATA16_SELECT_INPUT_OFFSET 0x0678
|
||||
#define IOMUXC_LCD_DATA17_SELECT_INPUT_OFFSET 0x067C
|
||||
#define IOMUXC_LCD_DATA18_SELECT_INPUT_OFFSET 0x0680
|
||||
#define IOMUXC_LCD_DATA19_SELECT_INPUT_OFFSET 0x0684
|
||||
#define IOMUXC_LCD_DATA20_SELECT_INPUT_OFFSET 0x0688
|
||||
#define IOMUXC_LCD_DATA21_SELECT_INPUT_OFFSET 0x068C
|
||||
#define IOMUXC_LCD_DATA22_SELECT_INPUT_OFFSET 0x0690
|
||||
#define IOMUXC_LCD_DATA23_SELECT_INPUT_OFFSET 0x0694
|
||||
#define IOMUXC_LCD_VSYNC_SELECT_INPUT_OFFSET 0x0698
|
||||
|
||||
#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_OFFSET 0x069C
|
||||
#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_OFFSET 0x06A0
|
||||
#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_OFFSET 0x06A4
|
||||
#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_OFFSET 0x06A8
|
||||
#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_OFFSET 0x06AC
|
||||
#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_OFFSET 0x06B0
|
||||
#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_OFFSET 0x06B4
|
||||
#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_OFFSET 0x06B8
|
||||
#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_OFFSET 0x06BC
|
||||
#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_OFFSET 0x06C0
|
||||
#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_OFFSET 0x06C4
|
||||
#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_OFFSET 0x06C8
|
||||
#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_OFFSET 0x06CC
|
||||
#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_OFFSET 0x06D0
|
||||
#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_OFFSET 0x06D4
|
||||
#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_OFFSET 0x06D8
|
||||
#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_OFFSET 0x06DC
|
||||
|
||||
#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_OFFSET 0x06E0
|
||||
#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06E4
|
||||
#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_OFFSET 0x06E8
|
||||
#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06EC
|
||||
|
||||
#define IOMUXC_UART1_RTS_B_SELECT_INPUT_OFFSET 0x06F0
|
||||
#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_OFFSET 0x06F4
|
||||
#define IOMUXC_UART2_RTS_B_SELECT_INPUT_OFFSET 0x06F8
|
||||
#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_OFFSET 0x06FC
|
||||
#define IOMUXC_UART3_RTS_B_SELECT_INPUT_OFFSET 0x0700
|
||||
#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_OFFSET 0x0704
|
||||
#define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708
|
||||
#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C
|
||||
#define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710
|
||||
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SCL_ALT1 0x00
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_I2C4_SDA_ALT1 BIT(0)
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_RX_DATA_ALT2 BIT(1)
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_SAI1_TX_BCLK_ALT2 (BIT(1) | BIT(0))
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO06_ALT3 BIT(2)
|
||||
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_GPIO1_IO07_ALT3 (BIT(2) | BIT(1))
|
||||
|
||||
#define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718
|
||||
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C
|
||||
#define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720
|
||||
#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_OFFSET 0x0724
|
||||
|
||||
#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_OFFSET 0x0728
|
||||
#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_OFFSET 0x072C
|
||||
#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_OFFSET 0x0730
|
||||
#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_OFFSET 0x0734
|
||||
#define IOMUXC_SD3_CD_B_SELECT_INPUT_OFFSET 0x0738
|
||||
#define IOMUXC_SD3_WP_SELECT_INPUT_OFFSET 0x073C
|
||||
|
||||
/* Pad mux/feature set routines */
|
||||
|
||||
void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function);
|
||||
void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features);
|
||||
|
||||
#endif /* IMX_IO_MUX_H */
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __IMX_SIP_SVC_H__
|
||||
#define __IMX_SIP_SVC_H__
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
#define IMX_SIP_GPC 0xC2000000
|
||||
|
||||
#define IMX_SIP_CPUFREQ 0xC2000001
|
||||
#define IMX_SIP_SET_CPUFREQ 0x00
|
||||
|
||||
#define IMX_SIP_SRTC 0xC2000002
|
||||
#define IMX_SIP_SRTC_SET_TIME 0x00
|
||||
|
||||
#define IMX_SIP_BUILDINFO 0xC2000003
|
||||
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
|
||||
|
||||
#define IMX_SIP_DDR_DVFS 0xc2000004
|
||||
|
||||
#define IMX_SIP_SRC 0xC2000005
|
||||
#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
|
||||
#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
|
||||
|
||||
#define IMX_SIP_GET_SOC_INFO 0xC2000006
|
||||
|
||||
#define IMX_SIP_HAB 0xC2000007
|
||||
#define IMX_SIP_HAB_AUTH_IMG 0x00
|
||||
#define IMX_SIP_HAB_ENTRY 0x01
|
||||
#define IMX_SIP_HAB_EXIT 0x02
|
||||
#define IMX_SIP_HAB_REPORT_EVENT 0x03
|
||||
#define IMX_SIP_HAB_REPORT_STATUS 0x04
|
||||
#define IMX_SIP_HAB_FAILSAFE 0x05
|
||||
#define IMX_SIP_HAB_CHECK_TARGET 0x06
|
||||
#define IMX_SIP_HAB_GET_VERSION 0x07
|
||||
#define IMX_SIP_HAB_AUTH_IMG_NO_DCD 0x08
|
||||
|
||||
#define IMX_SIP_WAKEUP_SRC 0xC2000009
|
||||
#define IMX_SIP_WAKEUP_SRC_SCU 0x1
|
||||
#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2
|
||||
|
||||
#define IMX_SIP_OTP_READ 0xC200000A
|
||||
#define IMX_SIP_OTP_WRITE 0xC200000B
|
||||
|
||||
#define IMX_SIP_MISC_SET_TEMP 0xC200000C
|
||||
|
||||
#define IMX_SIP_AARCH32 0xC20000FD
|
||||
|
||||
int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3,
|
||||
u_register_t x4);
|
||||
#if defined(PLAT_imx8mq)
|
||||
int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3);
|
||||
#endif
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
|
||||
int dram_dvfs_handler(uint32_t smc_fid, void *handle,
|
||||
u_register_t x1, u_register_t x2, u_register_t x3);
|
||||
|
||||
int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3);
|
||||
#endif
|
||||
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
|
||||
int imx_src_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3, void *handle);
|
||||
#endif
|
||||
|
||||
#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
|
||||
int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3, u_register_t x4);
|
||||
#endif
|
||||
|
||||
#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
|
||||
int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3);
|
||||
int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3, u_register_t x4);
|
||||
int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3);
|
||||
int imx_otp_handler(uint32_t smc_fid, void *handle,
|
||||
u_register_t x1, u_register_t x2);
|
||||
int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3,
|
||||
u_register_t x4);
|
||||
#endif
|
||||
uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3,
|
||||
u_register_t x4);
|
||||
|
||||
#endif /* __IMX_SIP_SVC_H__ */
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (C) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef IMX_SNVS_H
|
||||
#define IMX_SNVS_H
|
||||
|
||||
#include <cdefs.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch.h>
|
||||
|
||||
struct snvs {
|
||||
uint32_t hplr;
|
||||
uint32_t hpcomr;
|
||||
uint32_t hpcr;
|
||||
uint32_t hpsicr;
|
||||
uint32_t hpsvcr;
|
||||
uint32_t hpsr;
|
||||
uint32_t hpsvsr;
|
||||
uint32_t hphacivr;
|
||||
uint32_t hphacr;
|
||||
uint32_t hprtcmr;
|
||||
uint32_t hprtclr;
|
||||
uint32_t hptamr;
|
||||
uint32_t hptalr;
|
||||
uint32_t lplr;
|
||||
uint32_t lpcr;
|
||||
uint32_t lpmkcr;
|
||||
uint32_t lpsvcr;
|
||||
uint32_t lptgfcr;
|
||||
uint32_t lptdcr;
|
||||
uint32_t lpsr;
|
||||
uint32_t lpsrtcmr;
|
||||
uint32_t lpsrtclr;
|
||||
uint32_t lptar;
|
||||
uint32_t lpsmcmr;
|
||||
uint32_t lpsmclr;
|
||||
uint32_t lppgdr;
|
||||
uint32_t lpgpr0_alias;
|
||||
uint8_t lpzmkr[32];
|
||||
uint16_t res0;
|
||||
uint32_t lpgpr0[4];
|
||||
uint32_t lptdc2r;
|
||||
uint32_t lptdsr;
|
||||
uint32_t lptgf1cr;
|
||||
uint32_t lptgf2cr;
|
||||
uint32_t res1[4];
|
||||
uint32_t lpat1cr;
|
||||
uint32_t lpat2cr;
|
||||
uint32_t lpat3cr;
|
||||
uint32_t lpat4cr;
|
||||
uint32_t lpat5cr;
|
||||
uint32_t res2[3];
|
||||
uint32_t lpatctlr;
|
||||
uint32_t lpatclkr;
|
||||
uint32_t lpatrc1r;
|
||||
uint32_t lpatrc2r;
|
||||
uint32_t res3[706];
|
||||
uint32_t hpvidr1;
|
||||
uint32_t hpvidr2;
|
||||
} __packed;
|
||||
|
||||
/* Define the HPCOMR bits */
|
||||
#define HPCOMR_NPSWA_EN BIT(31)
|
||||
#define HPCOMR_HAC_STOP BIT(19)
|
||||
#define HPCOMR_HAC_CLEAR BIT(18)
|
||||
#define HPCOMR_HAC_LOAD BIT(17)
|
||||
#define HPCOMR_HAC_EN BIT(16)
|
||||
#define HPCOMR_MKS_EN BIT(13)
|
||||
#define HPCOMR_PROG_ZMK BIT(12)
|
||||
#define HPCOMR_SW_LPSV BIT(10)
|
||||
#define HPCOMR_SW_FSV BIT(9)
|
||||
#define HPCOMR_SW_SV BIT(8)
|
||||
#define HPCOMR_LP_SWR_DIS BIT(5)
|
||||
#define HPCOMR_LP_SWR BIT(4)
|
||||
#define HPCOMR_SSM_SFNS_DIS BIT(2)
|
||||
#define HPCOMR_SSM_ST_DIS BIT(1)
|
||||
#define HPCOMR_SSM_ST BIT(0)
|
||||
|
||||
void imx_snvs_init(void);
|
||||
|
||||
#endif /* IMX_SNVS_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_UART_H
|
||||
#define IMX_UART_H
|
||||
|
||||
#include <drivers/console.h>
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
|
||||
console_t *console);
|
||||
#endif /*__ASSEMBLER__*/
|
||||
|
||||
#endif /* IMX_UART_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_WDOG_H
|
||||
#define IMX_WDOG_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch.h>
|
||||
|
||||
struct wdog_regs {
|
||||
uint16_t wcr;
|
||||
uint16_t wsr;
|
||||
uint16_t wrsr;
|
||||
uint16_t wicr;
|
||||
uint16_t wmcr;
|
||||
};
|
||||
|
||||
/* WCR bits */
|
||||
#define WCR_WDZST BIT(0)
|
||||
#define WCR_WDBG BIT(1)
|
||||
#define WCR_WDE BIT(2)
|
||||
#define WCR_WDT BIT(3)
|
||||
#define WCR_SRS BIT(4)
|
||||
#define WCR_WDA BIT(5)
|
||||
#define WCR_SRE BIT(6)
|
||||
#define WCR_WDW BIT(7)
|
||||
#define WCR_WT(x) ((x) << 8)
|
||||
|
||||
/* WSR bits */
|
||||
#define WSR_FIRST 0x5555
|
||||
#define WSR_SECOND 0xAAAA
|
||||
|
||||
/* WRSR bits */
|
||||
#define WRSR_SFTW BIT(0)
|
||||
#define WRSR_TOUT BIT(1)
|
||||
#define WRSR_POR BIT(4)
|
||||
|
||||
/* WICR bits */
|
||||
static inline int wicr_calc_wict(int sec, int half_sec)
|
||||
{
|
||||
int wict_bits;
|
||||
|
||||
/* Represents WICR bits 7 - 0 */
|
||||
wict_bits = ((sec << 1) | (half_sec ? 1 : 0));
|
||||
|
||||
return wict_bits;
|
||||
}
|
||||
|
||||
#define WICR_WTIS BIT(14)
|
||||
#define WICR_WIE BIT(15)
|
||||
|
||||
/* WMCR bits */
|
||||
#define WMCR_PDE BIT(0)
|
||||
|
||||
/* External facing API */
|
||||
void imx_wdog_init(void);
|
||||
|
||||
#endif /* IMX_WDOG_H */
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_IMX8_H
|
||||
#define PLAT_IMX8_H
|
||||
|
||||
#include <drivers/arm/gicv3.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
struct plat_gic_ctx {
|
||||
gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
|
||||
gicv3_dist_ctx_t dist_ctx;
|
||||
};
|
||||
|
||||
unsigned int plat_calc_core_pos(uint64_t mpidr);
|
||||
void imx_mailbox_init(uintptr_t base_addr);
|
||||
void plat_gic_driver_init(void);
|
||||
void plat_gic_init(void);
|
||||
void plat_gic_cpuif_enable(void);
|
||||
void plat_gic_cpuif_disable(void);
|
||||
void plat_gic_pcpu_init(void);
|
||||
|
||||
void __dead2 imx_system_off(void);
|
||||
void __dead2 imx_system_reset(void);
|
||||
int imx_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state);
|
||||
void imx_get_sys_suspend_power_state(psci_power_state_t *req_state);
|
||||
bool imx_is_wakeup_src_irqsteer(void);
|
||||
void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx);
|
||||
void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx);
|
||||
|
||||
#endif /* PLAT_IMX8_H */
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* the below macros print out relevant GIC
|
||||
* registers whenever an unhandled exception is
|
||||
* taken in BL3-1
|
||||
*/
|
||||
.macro plat_print_gic_regs
|
||||
/* TODO */
|
||||
.endm
|
||||
|
||||
/*
|
||||
* the below macros print out relevant interconnect
|
||||
* registers whenever an unhandled exception is
|
||||
* taken in BL3-1
|
||||
*/
|
||||
.macro plat_print_interconnect_regs
|
||||
/* TODO */
|
||||
.endm
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below required platform porting macro
|
||||
* prints out relevant platform registers
|
||||
* whenever an unhandled exception is taken in
|
||||
* BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
/* TODO */
|
||||
.endm
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SCI_H
|
||||
#define SCI_H
|
||||
|
||||
/* Defines */
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_ipc.h>
|
||||
#include <sci/svc/pad/sci_pad_api.h>
|
||||
#include <sci/svc/pm/sci_pm_api.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/svc/timer/sci_timer_api.h>
|
||||
#include <sci/svc/misc/sci_misc_api.h>
|
||||
|
||||
#endif /* SCI_H */
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the IPC implementation.
|
||||
*/
|
||||
|
||||
#ifndef SCI_IPC_H
|
||||
#define SCI_IPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/* Types */
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This function opens an IPC channel.
|
||||
*
|
||||
* @param[out] ipc return pointer for ipc handle
|
||||
* @param[in] id id of channel to open
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC
|
||||
* otherwise).
|
||||
*
|
||||
* The \a id parameter is implementation specific. Could be an MU
|
||||
* address, pointer to a driver path, channel index, etc.
|
||||
*/
|
||||
sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id);
|
||||
|
||||
/*!
|
||||
* This function closes an IPC channel.
|
||||
*
|
||||
* @param[in] ipc id of channel to close
|
||||
*/
|
||||
void sc_ipc_close(sc_ipc_t ipc);
|
||||
|
||||
/*!
|
||||
* This function reads a message from an IPC channel.
|
||||
*
|
||||
* @param[in] ipc id of channel read from
|
||||
* @param[out] data pointer to message buffer to read
|
||||
*
|
||||
* This function will block if no message is available to be read.
|
||||
*/
|
||||
void sc_ipc_read(sc_ipc_t ipc, void *data);
|
||||
|
||||
/*!
|
||||
* This function writes a message to an IPC channel.
|
||||
*
|
||||
* @param[in] ipc id of channel to write to
|
||||
* @param[in] data pointer to message buffer to write
|
||||
*
|
||||
* This function will block if the outgoing buffer is full.
|
||||
*/
|
||||
void sc_ipc_write(sc_ipc_t ipc, void *data);
|
||||
|
||||
extern sc_ipc_t ipc_handle;
|
||||
|
||||
#endif /* SCI_IPC_H */
|
||||
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the RPC implementation.
|
||||
*/
|
||||
|
||||
#ifndef SCI_RPC_H
|
||||
#define SCI_RPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/sci_ipc.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
#define SC_RPC_VERSION 1U
|
||||
|
||||
#define SC_RPC_MAX_MSG 8U
|
||||
|
||||
#define RPC_VER(MSG) ((MSG)->version)
|
||||
#define RPC_SIZE(MSG) ((MSG)->size)
|
||||
#define RPC_SVC(MSG) ((MSG)->svc)
|
||||
#define RPC_FUNC(MSG) ((MSG)->func)
|
||||
#define RPC_R8(MSG) ((MSG)->func)
|
||||
#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
|
||||
#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
|
||||
#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
|
||||
#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
|
||||
#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
|
||||
#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
|
||||
|
||||
#define SC_RPC_SVC_UNKNOWN 0U
|
||||
#define SC_RPC_SVC_RETURN 1U
|
||||
#define SC_RPC_SVC_PM 2U
|
||||
#define SC_RPC_SVC_RM 3U
|
||||
#define SC_RPC_SVC_TIMER 5U
|
||||
#define SC_RPC_SVC_PAD 6U
|
||||
#define SC_RPC_SVC_MISC 7U
|
||||
#define SC_RPC_SVC_IRQ 8U
|
||||
#define SC_RPC_SVC_ABORT 9U
|
||||
|
||||
#define SC_RPC_ASYNC_STATE_RD_START 0U
|
||||
#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U
|
||||
#define SC_RPC_ASYNC_STATE_RD_DONE 2U
|
||||
#define SC_RPC_ASYNC_STATE_WR_START 3U
|
||||
#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U
|
||||
#define SC_RPC_ASYNC_STATE_WR_DONE 5U
|
||||
|
||||
#define SC_RPC_MU_GIR_SVC 0x1U
|
||||
#define SC_RPC_MU_GIR_DBG 0x8U
|
||||
|
||||
/* Types */
|
||||
|
||||
typedef uint8_t sc_rpc_svc_t;
|
||||
|
||||
typedef struct sc_rpc_msg_s {
|
||||
uint8_t version;
|
||||
uint8_t size;
|
||||
uint8_t svc;
|
||||
uint8_t func;
|
||||
union {
|
||||
int32_t i32[(SC_RPC_MAX_MSG - 1U)];
|
||||
int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U];
|
||||
int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U];
|
||||
uint32_t u32[(SC_RPC_MAX_MSG - 1U)];
|
||||
uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U];
|
||||
uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U];
|
||||
} DATA;
|
||||
} sc_rpc_msg_t;
|
||||
|
||||
typedef uint8_t sc_rpc_async_state_t;
|
||||
|
||||
typedef struct sc_rpc_async_msg_s {
|
||||
sc_rpc_async_state_t state;
|
||||
uint8_t wordIdx;
|
||||
sc_rpc_msg_t msg;
|
||||
uint32_t timeStamp;
|
||||
} sc_rpc_async_msg_t;
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This is an internal function to send an RPC message over an IPC
|
||||
* channel. It is called by client-side SCFW API function shims.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in,out] msg handle to a message
|
||||
* @param[in] no_resp response flag
|
||||
*
|
||||
* If \a no_resp is SC_FALSE then this function waits for a response
|
||||
* and returns the result in \a msg.
|
||||
*/
|
||||
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
|
||||
|
||||
/*!
|
||||
* This is an internal function to dispath an RPC call that has
|
||||
* arrived via IPC over an MU. It is called by server-side SCFW.
|
||||
*
|
||||
* @param[in] mu MU message arrived on
|
||||
* @param[in,out] msg handle to a message
|
||||
*
|
||||
* The function result is returned in \a msg.
|
||||
*/
|
||||
void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg);
|
||||
|
||||
/*!
|
||||
* This function translates an RPC message and forwards on to the
|
||||
* normal RPC API. It is used only by hypervisors.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in,out] msg handle to a message
|
||||
*
|
||||
* This function decodes a message, calls macros to translate the
|
||||
* resources, pads, addresses, partitions, memory regions, etc. and
|
||||
* then forwards on to the hypervisors SCFW API.Return results are
|
||||
* translated back abd placed back into the message to be returned
|
||||
* to the original API.
|
||||
*/
|
||||
void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
|
||||
|
||||
#endif /* SCI_RPC_H */
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SCI_SCFW_H
|
||||
#define SCI_SCFW_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/*!
|
||||
* This type is used to declare a handle for an IPC communication
|
||||
* channel. Its meaning is specific to the IPC implementation.
|
||||
*/
|
||||
typedef uint64_t sc_ipc_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare an ID for an IPC communication
|
||||
* channel. For the reference IPC implementation, this ID
|
||||
* selects the base address of the MU used for IPC.
|
||||
*/
|
||||
typedef uint64_t sc_ipc_id_t;
|
||||
|
||||
|
||||
#endif /* SCI_SCFW_H */
|
||||
+849
@@ -0,0 +1,849 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file containing types used across multiple service APIs.
|
||||
*/
|
||||
|
||||
#ifndef SCI_TYPES_H
|
||||
#define SCI_TYPES_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_scfw.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for common frequencies
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_32KHZ 32768U /* 32KHz */
|
||||
#define SC_10MHZ 10000000U /* 10MHz */
|
||||
#define SC_20MHZ 20000000U /* 20MHz */
|
||||
#define SC_25MHZ 25000000U /* 25MHz */
|
||||
#define SC_27MHZ 27000000U /* 27MHz */
|
||||
#define SC_40MHZ 40000000U /* 40MHz */
|
||||
#define SC_45MHZ 45000000U /* 45MHz */
|
||||
#define SC_50MHZ 50000000U /* 50MHz */
|
||||
#define SC_60MHZ 60000000U /* 60MHz */
|
||||
#define SC_66MHZ 66666666U /* 66MHz */
|
||||
#define SC_74MHZ 74250000U /* 74.25MHz */
|
||||
#define SC_80MHZ 80000000U /* 80MHz */
|
||||
#define SC_83MHZ 83333333U /* 83MHz */
|
||||
#define SC_84MHZ 84375000U /* 84.37MHz */
|
||||
#define SC_100MHZ 100000000U /* 100MHz */
|
||||
#define SC_125MHZ 125000000U /* 125MHz */
|
||||
#define SC_133MHZ 133333333U /* 133MHz */
|
||||
#define SC_135MHZ 135000000U /* 135MHz */
|
||||
#define SC_150MHZ 150000000U /* 150MHz */
|
||||
#define SC_160MHZ 160000000U /* 160MHz */
|
||||
#define SC_166MHZ 166666666U /* 166MHz */
|
||||
#define SC_175MHZ 175000000U /* 175MHz */
|
||||
#define SC_180MHZ 180000000U /* 180MHz */
|
||||
#define SC_200MHZ 200000000U /* 200MHz */
|
||||
#define SC_250MHZ 250000000U /* 250MHz */
|
||||
#define SC_266MHZ 266666666U /* 266MHz */
|
||||
#define SC_300MHZ 300000000U /* 300MHz */
|
||||
#define SC_312MHZ 312500000U /* 312.5MHZ */
|
||||
#define SC_320MHZ 320000000U /* 320MHz */
|
||||
#define SC_325MHZ 325000000U /* 325MHz */
|
||||
#define SC_333MHZ 333333333U /* 333MHz */
|
||||
#define SC_350MHZ 350000000U /* 350MHz */
|
||||
#define SC_372MHZ 372000000U /* 372MHz */
|
||||
#define SC_375MHZ 375000000U /* 375MHz */
|
||||
#define SC_400MHZ 400000000U /* 400MHz */
|
||||
#define SC_500MHZ 500000000U /* 500MHz */
|
||||
#define SC_594MHZ 594000000U /* 594MHz */
|
||||
#define SC_625MHZ 625000000U /* 625MHz */
|
||||
#define SC_640MHZ 640000000U /* 640MHz */
|
||||
#define SC_650MHZ 650000000U /* 650MHz */
|
||||
#define SC_667MHZ 666666667U /* 667MHz */
|
||||
#define SC_675MHZ 675000000U /* 675MHz */
|
||||
#define SC_700MHZ 700000000U /* 700MHz */
|
||||
#define SC_720MHZ 720000000U /* 720MHz */
|
||||
#define SC_750MHZ 750000000U /* 750MHz */
|
||||
#define SC_800MHZ 800000000U /* 800MHz */
|
||||
#define SC_850MHZ 850000000U /* 850MHz */
|
||||
#define SC_900MHZ 900000000U /* 900MHz */
|
||||
#define SC_1000MHZ 1000000000U /* 1GHz */
|
||||
#define SC_1056MHZ 1056000000U /* 1.056GHz */
|
||||
#define SC_1188MHZ 1188000000U /* 1.188GHz */
|
||||
#define SC_1260MHZ 1260000000U /* 1.26GHz */
|
||||
#define SC_1280MHZ 1280000000U /* 1.28GHz */
|
||||
#define SC_1300MHZ 1300000000U /* 1.3GHz */
|
||||
#define SC_1400MHZ 1400000000U /* 1.4GHz */
|
||||
#define SC_1500MHZ 1500000000U /* 1.5GHz */
|
||||
#define SC_1600MHZ 1600000000U /* 1.6GHz */
|
||||
#define SC_1800MHZ 1800000000U /* 1.8GHz */
|
||||
#define SC_2000MHZ 2000000000U /* 2.0GHz */
|
||||
#define SC_2112MHZ 2112000000U /* 2.12GHz */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for 24M related frequencies
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_8MHZ 8000000U /* 8MHz */
|
||||
#define SC_12MHZ 12000000U /* 12MHz */
|
||||
#define SC_19MHZ 19800000U /* 19.8MHz */
|
||||
#define SC_24MHZ 24000000U /* 24MHz */
|
||||
#define SC_48MHZ 48000000U /* 48MHz */
|
||||
#define SC_120MHZ 120000000U /* 120MHz */
|
||||
#define SC_132MHZ 132000000U /* 132MHz */
|
||||
#define SC_144MHZ 144000000U /* 144MHz */
|
||||
#define SC_192MHZ 192000000U /* 192MHz */
|
||||
#define SC_211MHZ 211200000U /* 211.2MHz */
|
||||
#define SC_240MHZ 240000000U /* 240MHz */
|
||||
#define SC_264MHZ 264000000U /* 264MHz */
|
||||
#define SC_352MHZ 352000000U /* 352MHz */
|
||||
#define SC_360MHZ 360000000U /* 360MHz */
|
||||
#define SC_384MHZ 384000000U /* 384MHz */
|
||||
#define SC_396MHZ 396000000U /* 396MHz */
|
||||
#define SC_432MHZ 432000000U /* 432MHz */
|
||||
#define SC_480MHZ 480000000U /* 480MHz */
|
||||
#define SC_600MHZ 600000000U /* 600MHz */
|
||||
#define SC_744MHZ 744000000U /* 744MHz */
|
||||
#define SC_792MHZ 792000000U /* 792MHz */
|
||||
#define SC_864MHZ 864000000U /* 864MHz */
|
||||
#define SC_960MHZ 960000000U /* 960MHz */
|
||||
#define SC_1056MHZ 1056000000U /* 1056MHz */
|
||||
#define SC_1200MHZ 1200000000U /* 1.2GHz */
|
||||
#define SC_1464MHZ 1464000000U /* 1.464GHz */
|
||||
#define SC_2400MHZ 2400000000U /* 2.4GHz */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for A/V related frequencies
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_62MHZ 62937500U /* 62.9375MHz */
|
||||
#define SC_755MHZ 755250000U /* 755.25MHz */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for type widths
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_FADDR_W 36U /* Width of sc_faddr_t */
|
||||
#define SC_BOOL_W 1U /* Width of sc_bool_t */
|
||||
#define SC_ERR_W 4U /* Width of sc_err_t */
|
||||
#define SC_RSRC_W 10U /* Width of sc_rsrc_t */
|
||||
#define SC_CTRL_W 6U /* Width of sc_ctrl_t */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_bool_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_FALSE ((sc_bool_t) 0U) /* True */
|
||||
#define SC_TRUE ((sc_bool_t) 1U) /* False */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_err_t.
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_ERR_NONE 0U /* Success */
|
||||
#define SC_ERR_VERSION 1U /* Incompatible API version */
|
||||
#define SC_ERR_CONFIG 2U /* Configuration error */
|
||||
#define SC_ERR_PARM 3U /* Bad parameter */
|
||||
#define SC_ERR_NOACCESS 4U /* Permission error (no access) */
|
||||
#define SC_ERR_LOCKED 5U /* Permission error (locked) */
|
||||
#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */
|
||||
#define SC_ERR_NOTFOUND 7U /* Not found */
|
||||
#define SC_ERR_NOPOWER 8U /* No power */
|
||||
#define SC_ERR_IPC 9U /* Generic IPC error */
|
||||
#define SC_ERR_BUSY 10U /* Resource is currently busy/active */
|
||||
#define SC_ERR_FAIL 11U /* General I/O failure */
|
||||
#define SC_ERR_LAST 12U
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_rsrc_t.
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_R_A53 0U
|
||||
#define SC_R_A53_0 1U
|
||||
#define SC_R_A53_1 2U
|
||||
#define SC_R_A53_2 3U
|
||||
#define SC_R_A53_3 4U
|
||||
#define SC_R_A72 5U
|
||||
#define SC_R_A72_0 6U
|
||||
#define SC_R_A72_1 7U
|
||||
#define SC_R_A72_2 8U
|
||||
#define SC_R_A72_3 9U
|
||||
#define SC_R_CCI 10U
|
||||
#define SC_R_DB 11U
|
||||
#define SC_R_DRC_0 12U
|
||||
#define SC_R_DRC_1 13U
|
||||
#define SC_R_GIC_SMMU 14U
|
||||
#define SC_R_IRQSTR_M4_0 15U
|
||||
#define SC_R_IRQSTR_M4_1 16U
|
||||
#define SC_R_SMMU 17U
|
||||
#define SC_R_GIC 18U
|
||||
#define SC_R_DC_0_BLIT0 19U
|
||||
#define SC_R_DC_0_BLIT1 20U
|
||||
#define SC_R_DC_0_BLIT2 21U
|
||||
#define SC_R_DC_0_BLIT_OUT 22U
|
||||
#define SC_R_DC_0_CAPTURE0 23U
|
||||
#define SC_R_DC_0_CAPTURE1 24U
|
||||
#define SC_R_DC_0_WARP 25U
|
||||
#define SC_R_DC_0_INTEGRAL0 26U
|
||||
#define SC_R_DC_0_INTEGRAL1 27U
|
||||
#define SC_R_DC_0_VIDEO0 28U
|
||||
#define SC_R_DC_0_VIDEO1 29U
|
||||
#define SC_R_DC_0_FRAC0 30U
|
||||
#define SC_R_DC_0_FRAC1 31U
|
||||
#define SC_R_DC_0 32U
|
||||
#define SC_R_GPU_2_PID0 33U
|
||||
#define SC_R_DC_0_PLL_0 34U
|
||||
#define SC_R_DC_0_PLL_1 35U
|
||||
#define SC_R_DC_1_BLIT0 36U
|
||||
#define SC_R_DC_1_BLIT1 37U
|
||||
#define SC_R_DC_1_BLIT2 38U
|
||||
#define SC_R_DC_1_BLIT_OUT 39U
|
||||
#define SC_R_DC_1_CAPTURE0 40U
|
||||
#define SC_R_DC_1_CAPTURE1 41U
|
||||
#define SC_R_DC_1_WARP 42U
|
||||
#define SC_R_DC_1_INTEGRAL0 43U
|
||||
#define SC_R_DC_1_INTEGRAL1 44U
|
||||
#define SC_R_DC_1_VIDEO0 45U
|
||||
#define SC_R_DC_1_VIDEO1 46U
|
||||
#define SC_R_DC_1_FRAC0 47U
|
||||
#define SC_R_DC_1_FRAC1 48U
|
||||
#define SC_R_DC_1 49U
|
||||
#define SC_R_GPU_3_PID0 50U
|
||||
#define SC_R_DC_1_PLL_0 51U
|
||||
#define SC_R_DC_1_PLL_1 52U
|
||||
#define SC_R_SPI_0 53U
|
||||
#define SC_R_SPI_1 54U
|
||||
#define SC_R_SPI_2 55U
|
||||
#define SC_R_SPI_3 56U
|
||||
#define SC_R_UART_0 57U
|
||||
#define SC_R_UART_1 58U
|
||||
#define SC_R_UART_2 59U
|
||||
#define SC_R_UART_3 60U
|
||||
#define SC_R_UART_4 61U
|
||||
#define SC_R_EMVSIM_0 62U
|
||||
#define SC_R_EMVSIM_1 63U
|
||||
#define SC_R_DMA_0_CH0 64U
|
||||
#define SC_R_DMA_0_CH1 65U
|
||||
#define SC_R_DMA_0_CH2 66U
|
||||
#define SC_R_DMA_0_CH3 67U
|
||||
#define SC_R_DMA_0_CH4 68U
|
||||
#define SC_R_DMA_0_CH5 69U
|
||||
#define SC_R_DMA_0_CH6 70U
|
||||
#define SC_R_DMA_0_CH7 71U
|
||||
#define SC_R_DMA_0_CH8 72U
|
||||
#define SC_R_DMA_0_CH9 73U
|
||||
#define SC_R_DMA_0_CH10 74U
|
||||
#define SC_R_DMA_0_CH11 75U
|
||||
#define SC_R_DMA_0_CH12 76U
|
||||
#define SC_R_DMA_0_CH13 77U
|
||||
#define SC_R_DMA_0_CH14 78U
|
||||
#define SC_R_DMA_0_CH15 79U
|
||||
#define SC_R_DMA_0_CH16 80U
|
||||
#define SC_R_DMA_0_CH17 81U
|
||||
#define SC_R_DMA_0_CH18 82U
|
||||
#define SC_R_DMA_0_CH19 83U
|
||||
#define SC_R_DMA_0_CH20 84U
|
||||
#define SC_R_DMA_0_CH21 85U
|
||||
#define SC_R_DMA_0_CH22 86U
|
||||
#define SC_R_DMA_0_CH23 87U
|
||||
#define SC_R_DMA_0_CH24 88U
|
||||
#define SC_R_DMA_0_CH25 89U
|
||||
#define SC_R_DMA_0_CH26 90U
|
||||
#define SC_R_DMA_0_CH27 91U
|
||||
#define SC_R_DMA_0_CH28 92U
|
||||
#define SC_R_DMA_0_CH29 93U
|
||||
#define SC_R_DMA_0_CH30 94U
|
||||
#define SC_R_DMA_0_CH31 95U
|
||||
#define SC_R_I2C_0 96U
|
||||
#define SC_R_I2C_1 97U
|
||||
#define SC_R_I2C_2 98U
|
||||
#define SC_R_I2C_3 99U
|
||||
#define SC_R_I2C_4 100U
|
||||
#define SC_R_ADC_0 101U
|
||||
#define SC_R_ADC_1 102U
|
||||
#define SC_R_FTM_0 103U
|
||||
#define SC_R_FTM_1 104U
|
||||
#define SC_R_CAN_0 105U
|
||||
#define SC_R_CAN_1 106U
|
||||
#define SC_R_CAN_2 107U
|
||||
#define SC_R_DMA_1_CH0 108U
|
||||
#define SC_R_DMA_1_CH1 109U
|
||||
#define SC_R_DMA_1_CH2 110U
|
||||
#define SC_R_DMA_1_CH3 111U
|
||||
#define SC_R_DMA_1_CH4 112U
|
||||
#define SC_R_DMA_1_CH5 113U
|
||||
#define SC_R_DMA_1_CH6 114U
|
||||
#define SC_R_DMA_1_CH7 115U
|
||||
#define SC_R_DMA_1_CH8 116U
|
||||
#define SC_R_DMA_1_CH9 117U
|
||||
#define SC_R_DMA_1_CH10 118U
|
||||
#define SC_R_DMA_1_CH11 119U
|
||||
#define SC_R_DMA_1_CH12 120U
|
||||
#define SC_R_DMA_1_CH13 121U
|
||||
#define SC_R_DMA_1_CH14 122U
|
||||
#define SC_R_DMA_1_CH15 123U
|
||||
#define SC_R_DMA_1_CH16 124U
|
||||
#define SC_R_DMA_1_CH17 125U
|
||||
#define SC_R_DMA_1_CH18 126U
|
||||
#define SC_R_DMA_1_CH19 127U
|
||||
#define SC_R_DMA_1_CH20 128U
|
||||
#define SC_R_DMA_1_CH21 129U
|
||||
#define SC_R_DMA_1_CH22 130U
|
||||
#define SC_R_DMA_1_CH23 131U
|
||||
#define SC_R_DMA_1_CH24 132U
|
||||
#define SC_R_DMA_1_CH25 133U
|
||||
#define SC_R_DMA_1_CH26 134U
|
||||
#define SC_R_DMA_1_CH27 135U
|
||||
#define SC_R_DMA_1_CH28 136U
|
||||
#define SC_R_DMA_1_CH29 137U
|
||||
#define SC_R_DMA_1_CH30 138U
|
||||
#define SC_R_DMA_1_CH31 139U
|
||||
#define SC_R_UNUSED1 140U
|
||||
#define SC_R_UNUSED2 141U
|
||||
#define SC_R_UNUSED3 142U
|
||||
#define SC_R_UNUSED4 143U
|
||||
#define SC_R_GPU_0_PID0 144U
|
||||
#define SC_R_GPU_0_PID1 145U
|
||||
#define SC_R_GPU_0_PID2 146U
|
||||
#define SC_R_GPU_0_PID3 147U
|
||||
#define SC_R_GPU_1_PID0 148U
|
||||
#define SC_R_GPU_1_PID1 149U
|
||||
#define SC_R_GPU_1_PID2 150U
|
||||
#define SC_R_GPU_1_PID3 151U
|
||||
#define SC_R_PCIE_A 152U
|
||||
#define SC_R_SERDES_0 153U
|
||||
#define SC_R_MATCH_0 154U
|
||||
#define SC_R_MATCH_1 155U
|
||||
#define SC_R_MATCH_2 156U
|
||||
#define SC_R_MATCH_3 157U
|
||||
#define SC_R_MATCH_4 158U
|
||||
#define SC_R_MATCH_5 159U
|
||||
#define SC_R_MATCH_6 160U
|
||||
#define SC_R_MATCH_7 161U
|
||||
#define SC_R_MATCH_8 162U
|
||||
#define SC_R_MATCH_9 163U
|
||||
#define SC_R_MATCH_10 164U
|
||||
#define SC_R_MATCH_11 165U
|
||||
#define SC_R_MATCH_12 166U
|
||||
#define SC_R_MATCH_13 167U
|
||||
#define SC_R_MATCH_14 168U
|
||||
#define SC_R_PCIE_B 169U
|
||||
#define SC_R_SATA_0 170U
|
||||
#define SC_R_SERDES_1 171U
|
||||
#define SC_R_HSIO_GPIO 172U
|
||||
#define SC_R_MATCH_15 173U
|
||||
#define SC_R_MATCH_16 174U
|
||||
#define SC_R_MATCH_17 175U
|
||||
#define SC_R_MATCH_18 176U
|
||||
#define SC_R_MATCH_19 177U
|
||||
#define SC_R_MATCH_20 178U
|
||||
#define SC_R_MATCH_21 179U
|
||||
#define SC_R_MATCH_22 180U
|
||||
#define SC_R_MATCH_23 181U
|
||||
#define SC_R_MATCH_24 182U
|
||||
#define SC_R_MATCH_25 183U
|
||||
#define SC_R_MATCH_26 184U
|
||||
#define SC_R_MATCH_27 185U
|
||||
#define SC_R_MATCH_28 186U
|
||||
#define SC_R_LCD_0 187U
|
||||
#define SC_R_LCD_0_PWM_0 188U
|
||||
#define SC_R_LCD_0_I2C_0 189U
|
||||
#define SC_R_LCD_0_I2C_1 190U
|
||||
#define SC_R_PWM_0 191U
|
||||
#define SC_R_PWM_1 192U
|
||||
#define SC_R_PWM_2 193U
|
||||
#define SC_R_PWM_3 194U
|
||||
#define SC_R_PWM_4 195U
|
||||
#define SC_R_PWM_5 196U
|
||||
#define SC_R_PWM_6 197U
|
||||
#define SC_R_PWM_7 198U
|
||||
#define SC_R_GPIO_0 199U
|
||||
#define SC_R_GPIO_1 200U
|
||||
#define SC_R_GPIO_2 201U
|
||||
#define SC_R_GPIO_3 202U
|
||||
#define SC_R_GPIO_4 203U
|
||||
#define SC_R_GPIO_5 204U
|
||||
#define SC_R_GPIO_6 205U
|
||||
#define SC_R_GPIO_7 206U
|
||||
#define SC_R_GPT_0 207U
|
||||
#define SC_R_GPT_1 208U
|
||||
#define SC_R_GPT_2 209U
|
||||
#define SC_R_GPT_3 210U
|
||||
#define SC_R_GPT_4 211U
|
||||
#define SC_R_KPP 212U
|
||||
#define SC_R_MU_0A 213U
|
||||
#define SC_R_MU_1A 214U
|
||||
#define SC_R_MU_2A 215U
|
||||
#define SC_R_MU_3A 216U
|
||||
#define SC_R_MU_4A 217U
|
||||
#define SC_R_MU_5A 218U
|
||||
#define SC_R_MU_6A 219U
|
||||
#define SC_R_MU_7A 220U
|
||||
#define SC_R_MU_8A 221U
|
||||
#define SC_R_MU_9A 222U
|
||||
#define SC_R_MU_10A 223U
|
||||
#define SC_R_MU_11A 224U
|
||||
#define SC_R_MU_12A 225U
|
||||
#define SC_R_MU_13A 226U
|
||||
#define SC_R_MU_5B 227U
|
||||
#define SC_R_MU_6B 228U
|
||||
#define SC_R_MU_7B 229U
|
||||
#define SC_R_MU_8B 230U
|
||||
#define SC_R_MU_9B 231U
|
||||
#define SC_R_MU_10B 232U
|
||||
#define SC_R_MU_11B 233U
|
||||
#define SC_R_MU_12B 234U
|
||||
#define SC_R_MU_13B 235U
|
||||
#define SC_R_ROM_0 236U
|
||||
#define SC_R_FSPI_0 237U
|
||||
#define SC_R_FSPI_1 238U
|
||||
#define SC_R_IEE 239U
|
||||
#define SC_R_IEE_R0 240U
|
||||
#define SC_R_IEE_R1 241U
|
||||
#define SC_R_IEE_R2 242U
|
||||
#define SC_R_IEE_R3 243U
|
||||
#define SC_R_IEE_R4 244U
|
||||
#define SC_R_IEE_R5 245U
|
||||
#define SC_R_IEE_R6 246U
|
||||
#define SC_R_IEE_R7 247U
|
||||
#define SC_R_SDHC_0 248U
|
||||
#define SC_R_SDHC_1 249U
|
||||
#define SC_R_SDHC_2 250U
|
||||
#define SC_R_ENET_0 251U
|
||||
#define SC_R_ENET_1 252U
|
||||
#define SC_R_MLB_0 253U
|
||||
#define SC_R_DMA_2_CH0 254U
|
||||
#define SC_R_DMA_2_CH1 255U
|
||||
#define SC_R_DMA_2_CH2 256U
|
||||
#define SC_R_DMA_2_CH3 257U
|
||||
#define SC_R_DMA_2_CH4 258U
|
||||
#define SC_R_USB_0 259U
|
||||
#define SC_R_USB_1 260U
|
||||
#define SC_R_USB_0_PHY 261U
|
||||
#define SC_R_USB_2 262U
|
||||
#define SC_R_USB_2_PHY 263U
|
||||
#define SC_R_DTCP 264U
|
||||
#define SC_R_NAND 265U
|
||||
#define SC_R_LVDS_0 266U
|
||||
#define SC_R_LVDS_0_PWM_0 267U
|
||||
#define SC_R_LVDS_0_I2C_0 268U
|
||||
#define SC_R_LVDS_0_I2C_1 269U
|
||||
#define SC_R_LVDS_1 270U
|
||||
#define SC_R_LVDS_1_PWM_0 271U
|
||||
#define SC_R_LVDS_1_I2C_0 272U
|
||||
#define SC_R_LVDS_1_I2C_1 273U
|
||||
#define SC_R_LVDS_2 274U
|
||||
#define SC_R_LVDS_2_PWM_0 275U
|
||||
#define SC_R_LVDS_2_I2C_0 276U
|
||||
#define SC_R_LVDS_2_I2C_1 277U
|
||||
#define SC_R_M4_0_PID0 278U
|
||||
#define SC_R_M4_0_PID1 279U
|
||||
#define SC_R_M4_0_PID2 280U
|
||||
#define SC_R_M4_0_PID3 281U
|
||||
#define SC_R_M4_0_PID4 282U
|
||||
#define SC_R_M4_0_RGPIO 283U
|
||||
#define SC_R_M4_0_SEMA42 284U
|
||||
#define SC_R_M4_0_TPM 285U
|
||||
#define SC_R_M4_0_PIT 286U
|
||||
#define SC_R_M4_0_UART 287U
|
||||
#define SC_R_M4_0_I2C 288U
|
||||
#define SC_R_M4_0_INTMUX 289U
|
||||
#define SC_R_M4_0_SIM 290U
|
||||
#define SC_R_M4_0_WDOG 291U
|
||||
#define SC_R_M4_0_MU_0B 292U
|
||||
#define SC_R_M4_0_MU_0A0 293U
|
||||
#define SC_R_M4_0_MU_0A1 294U
|
||||
#define SC_R_M4_0_MU_0A2 295U
|
||||
#define SC_R_M4_0_MU_0A3 296U
|
||||
#define SC_R_M4_0_MU_1A 297U
|
||||
#define SC_R_M4_1_PID0 298U
|
||||
#define SC_R_M4_1_PID1 299U
|
||||
#define SC_R_M4_1_PID2 300U
|
||||
#define SC_R_M4_1_PID3 301U
|
||||
#define SC_R_M4_1_PID4 302U
|
||||
#define SC_R_M4_1_RGPIO 303U
|
||||
#define SC_R_M4_1_SEMA42 304U
|
||||
#define SC_R_M4_1_TPM 305U
|
||||
#define SC_R_M4_1_PIT 306U
|
||||
#define SC_R_M4_1_UART 307U
|
||||
#define SC_R_M4_1_I2C 308U
|
||||
#define SC_R_M4_1_INTMUX 309U
|
||||
#define SC_R_M4_1_SIM 310U
|
||||
#define SC_R_M4_1_WDOG 311U
|
||||
#define SC_R_M4_1_MU_0B 312U
|
||||
#define SC_R_M4_1_MU_0A0 313U
|
||||
#define SC_R_M4_1_MU_0A1 314U
|
||||
#define SC_R_M4_1_MU_0A2 315U
|
||||
#define SC_R_M4_1_MU_0A3 316U
|
||||
#define SC_R_M4_1_MU_1A 317U
|
||||
#define SC_R_SAI_0 318U
|
||||
#define SC_R_SAI_1 319U
|
||||
#define SC_R_SAI_2 320U
|
||||
#define SC_R_IRQSTR_SCU2 321U
|
||||
#define SC_R_IRQSTR_DSP 322U
|
||||
#define SC_R_UNUSED5 323U
|
||||
#define SC_R_OCRAM 324U
|
||||
#define SC_R_AUDIO_PLL_0 325U
|
||||
#define SC_R_PI_0 326U
|
||||
#define SC_R_PI_0_PWM_0 327U
|
||||
#define SC_R_PI_0_PWM_1 328U
|
||||
#define SC_R_PI_0_I2C_0 329U
|
||||
#define SC_R_PI_0_PLL 330U
|
||||
#define SC_R_PI_1 331U
|
||||
#define SC_R_PI_1_PWM_0 332U
|
||||
#define SC_R_PI_1_PWM_1 333U
|
||||
#define SC_R_PI_1_I2C_0 334U
|
||||
#define SC_R_PI_1_PLL 335U
|
||||
#define SC_R_SC_PID0 336U
|
||||
#define SC_R_SC_PID1 337U
|
||||
#define SC_R_SC_PID2 338U
|
||||
#define SC_R_SC_PID3 339U
|
||||
#define SC_R_SC_PID4 340U
|
||||
#define SC_R_SC_SEMA42 341U
|
||||
#define SC_R_SC_TPM 342U
|
||||
#define SC_R_SC_PIT 343U
|
||||
#define SC_R_SC_UART 344U
|
||||
#define SC_R_SC_I2C 345U
|
||||
#define SC_R_SC_MU_0B 346U
|
||||
#define SC_R_SC_MU_0A0 347U
|
||||
#define SC_R_SC_MU_0A1 348U
|
||||
#define SC_R_SC_MU_0A2 349U
|
||||
#define SC_R_SC_MU_0A3 350U
|
||||
#define SC_R_SC_MU_1A 351U
|
||||
#define SC_R_SYSCNT_RD 352U
|
||||
#define SC_R_SYSCNT_CMP 353U
|
||||
#define SC_R_DEBUG 354U
|
||||
#define SC_R_SYSTEM 355U
|
||||
#define SC_R_SNVS 356U
|
||||
#define SC_R_OTP 357U
|
||||
#define SC_R_VPU_PID0 358U
|
||||
#define SC_R_VPU_PID1 359U
|
||||
#define SC_R_VPU_PID2 360U
|
||||
#define SC_R_VPU_PID3 361U
|
||||
#define SC_R_VPU_PID4 362U
|
||||
#define SC_R_VPU_PID5 363U
|
||||
#define SC_R_VPU_PID6 364U
|
||||
#define SC_R_VPU_PID7 365U
|
||||
#define SC_R_VPU_UART 366U
|
||||
#define SC_R_VPUCORE 367U
|
||||
#define SC_R_VPUCORE_0 368U
|
||||
#define SC_R_VPUCORE_1 369U
|
||||
#define SC_R_VPUCORE_2 370U
|
||||
#define SC_R_VPUCORE_3 371U
|
||||
#define SC_R_DMA_4_CH0 372U
|
||||
#define SC_R_DMA_4_CH1 373U
|
||||
#define SC_R_DMA_4_CH2 374U
|
||||
#define SC_R_DMA_4_CH3 375U
|
||||
#define SC_R_DMA_4_CH4 376U
|
||||
#define SC_R_ISI_CH0 377U
|
||||
#define SC_R_ISI_CH1 378U
|
||||
#define SC_R_ISI_CH2 379U
|
||||
#define SC_R_ISI_CH3 380U
|
||||
#define SC_R_ISI_CH4 381U
|
||||
#define SC_R_ISI_CH5 382U
|
||||
#define SC_R_ISI_CH6 383U
|
||||
#define SC_R_ISI_CH7 384U
|
||||
#define SC_R_MJPEG_DEC_S0 385U
|
||||
#define SC_R_MJPEG_DEC_S1 386U
|
||||
#define SC_R_MJPEG_DEC_S2 387U
|
||||
#define SC_R_MJPEG_DEC_S3 388U
|
||||
#define SC_R_MJPEG_ENC_S0 389U
|
||||
#define SC_R_MJPEG_ENC_S1 390U
|
||||
#define SC_R_MJPEG_ENC_S2 391U
|
||||
#define SC_R_MJPEG_ENC_S3 392U
|
||||
#define SC_R_MIPI_0 393U
|
||||
#define SC_R_MIPI_0_PWM_0 394U
|
||||
#define SC_R_MIPI_0_I2C_0 395U
|
||||
#define SC_R_MIPI_0_I2C_1 396U
|
||||
#define SC_R_MIPI_1 397U
|
||||
#define SC_R_MIPI_1_PWM_0 398U
|
||||
#define SC_R_MIPI_1_I2C_0 399U
|
||||
#define SC_R_MIPI_1_I2C_1 400U
|
||||
#define SC_R_CSI_0 401U
|
||||
#define SC_R_CSI_0_PWM_0 402U
|
||||
#define SC_R_CSI_0_I2C_0 403U
|
||||
#define SC_R_CSI_1 404U
|
||||
#define SC_R_CSI_1_PWM_0 405U
|
||||
#define SC_R_CSI_1_I2C_0 406U
|
||||
#define SC_R_HDMI 407U
|
||||
#define SC_R_HDMI_I2S 408U
|
||||
#define SC_R_HDMI_I2C_0 409U
|
||||
#define SC_R_HDMI_PLL_0 410U
|
||||
#define SC_R_HDMI_RX 411U
|
||||
#define SC_R_HDMI_RX_BYPASS 412U
|
||||
#define SC_R_HDMI_RX_I2C_0 413U
|
||||
#define SC_R_ASRC_0 414U
|
||||
#define SC_R_ESAI_0 415U
|
||||
#define SC_R_SPDIF_0 416U
|
||||
#define SC_R_SPDIF_1 417U
|
||||
#define SC_R_SAI_3 418U
|
||||
#define SC_R_SAI_4 419U
|
||||
#define SC_R_SAI_5 420U
|
||||
#define SC_R_GPT_5 421U
|
||||
#define SC_R_GPT_6 422U
|
||||
#define SC_R_GPT_7 423U
|
||||
#define SC_R_GPT_8 424U
|
||||
#define SC_R_GPT_9 425U
|
||||
#define SC_R_GPT_10 426U
|
||||
#define SC_R_DMA_2_CH5 427U
|
||||
#define SC_R_DMA_2_CH6 428U
|
||||
#define SC_R_DMA_2_CH7 429U
|
||||
#define SC_R_DMA_2_CH8 430U
|
||||
#define SC_R_DMA_2_CH9 431U
|
||||
#define SC_R_DMA_2_CH10 432U
|
||||
#define SC_R_DMA_2_CH11 433U
|
||||
#define SC_R_DMA_2_CH12 434U
|
||||
#define SC_R_DMA_2_CH13 435U
|
||||
#define SC_R_DMA_2_CH14 436U
|
||||
#define SC_R_DMA_2_CH15 437U
|
||||
#define SC_R_DMA_2_CH16 438U
|
||||
#define SC_R_DMA_2_CH17 439U
|
||||
#define SC_R_DMA_2_CH18 440U
|
||||
#define SC_R_DMA_2_CH19 441U
|
||||
#define SC_R_DMA_2_CH20 442U
|
||||
#define SC_R_DMA_2_CH21 443U
|
||||
#define SC_R_DMA_2_CH22 444U
|
||||
#define SC_R_DMA_2_CH23 445U
|
||||
#define SC_R_DMA_2_CH24 446U
|
||||
#define SC_R_DMA_2_CH25 447U
|
||||
#define SC_R_DMA_2_CH26 448U
|
||||
#define SC_R_DMA_2_CH27 449U
|
||||
#define SC_R_DMA_2_CH28 450U
|
||||
#define SC_R_DMA_2_CH29 451U
|
||||
#define SC_R_DMA_2_CH30 452U
|
||||
#define SC_R_DMA_2_CH31 453U
|
||||
#define SC_R_ASRC_1 454U
|
||||
#define SC_R_ESAI_1 455U
|
||||
#define SC_R_SAI_6 456U
|
||||
#define SC_R_SAI_7 457U
|
||||
#define SC_R_AMIX 458U
|
||||
#define SC_R_MQS_0 459U
|
||||
#define SC_R_DMA_3_CH0 460U
|
||||
#define SC_R_DMA_3_CH1 461U
|
||||
#define SC_R_DMA_3_CH2 462U
|
||||
#define SC_R_DMA_3_CH3 463U
|
||||
#define SC_R_DMA_3_CH4 464U
|
||||
#define SC_R_DMA_3_CH5 465U
|
||||
#define SC_R_DMA_3_CH6 466U
|
||||
#define SC_R_DMA_3_CH7 467U
|
||||
#define SC_R_DMA_3_CH8 468U
|
||||
#define SC_R_DMA_3_CH9 469U
|
||||
#define SC_R_DMA_3_CH10 470U
|
||||
#define SC_R_DMA_3_CH11 471U
|
||||
#define SC_R_DMA_3_CH12 472U
|
||||
#define SC_R_DMA_3_CH13 473U
|
||||
#define SC_R_DMA_3_CH14 474U
|
||||
#define SC_R_DMA_3_CH15 475U
|
||||
#define SC_R_DMA_3_CH16 476U
|
||||
#define SC_R_DMA_3_CH17 477U
|
||||
#define SC_R_DMA_3_CH18 478U
|
||||
#define SC_R_DMA_3_CH19 479U
|
||||
#define SC_R_DMA_3_CH20 480U
|
||||
#define SC_R_DMA_3_CH21 481U
|
||||
#define SC_R_DMA_3_CH22 482U
|
||||
#define SC_R_DMA_3_CH23 483U
|
||||
#define SC_R_DMA_3_CH24 484U
|
||||
#define SC_R_DMA_3_CH25 485U
|
||||
#define SC_R_DMA_3_CH26 486U
|
||||
#define SC_R_DMA_3_CH27 487U
|
||||
#define SC_R_DMA_3_CH28 488U
|
||||
#define SC_R_DMA_3_CH29 489U
|
||||
#define SC_R_DMA_3_CH30 490U
|
||||
#define SC_R_DMA_3_CH31 491U
|
||||
#define SC_R_AUDIO_PLL_1 492U
|
||||
#define SC_R_AUDIO_CLK_0 493U
|
||||
#define SC_R_AUDIO_CLK_1 494U
|
||||
#define SC_R_MCLK_OUT_0 495U
|
||||
#define SC_R_MCLK_OUT_1 496U
|
||||
#define SC_R_PMIC_0 497U
|
||||
#define SC_R_PMIC_1 498U
|
||||
#define SC_R_SECO 499U
|
||||
#define SC_R_CAAM_JR1 500U
|
||||
#define SC_R_CAAM_JR2 501U
|
||||
#define SC_R_CAAM_JR3 502U
|
||||
#define SC_R_SECO_MU_2 503U
|
||||
#define SC_R_SECO_MU_3 504U
|
||||
#define SC_R_SECO_MU_4 505U
|
||||
#define SC_R_HDMI_RX_PWM_0 506U
|
||||
#define SC_R_A35 507U
|
||||
#define SC_R_A35_0 508U
|
||||
#define SC_R_A35_1 509U
|
||||
#define SC_R_A35_2 510U
|
||||
#define SC_R_A35_3 511U
|
||||
#define SC_R_DSP 512U
|
||||
#define SC_R_DSP_RAM 513U
|
||||
#define SC_R_CAAM_JR1_OUT 514U
|
||||
#define SC_R_CAAM_JR2_OUT 515U
|
||||
#define SC_R_CAAM_JR3_OUT 516U
|
||||
#define SC_R_VPU_DEC_0 517U
|
||||
#define SC_R_VPU_ENC_0 518U
|
||||
#define SC_R_CAAM_JR0 519U
|
||||
#define SC_R_CAAM_JR0_OUT 520U
|
||||
#define SC_R_PMIC_2 521U
|
||||
#define SC_R_DBLOGIC 522U
|
||||
#define SC_R_HDMI_PLL_1 523U
|
||||
#define SC_R_BOARD_R0 524U
|
||||
#define SC_R_BOARD_R1 525U
|
||||
#define SC_R_BOARD_R2 526U
|
||||
#define SC_R_BOARD_R3 527U
|
||||
#define SC_R_BOARD_R4 528U
|
||||
#define SC_R_BOARD_R5 529U
|
||||
#define SC_R_BOARD_R6 530U
|
||||
#define SC_R_BOARD_R7 531U
|
||||
#define SC_R_MJPEG_DEC_MP 532U
|
||||
#define SC_R_MJPEG_ENC_MP 533U
|
||||
#define SC_R_VPU_TS_0 534U
|
||||
#define SC_R_VPU_MU_0 535U
|
||||
#define SC_R_VPU_MU_1 536U
|
||||
#define SC_R_VPU_MU_2 537U
|
||||
#define SC_R_VPU_MU_3 538U
|
||||
#define SC_R_VPU_ENC_1 539U
|
||||
#define SC_R_VPU 540U
|
||||
#define SC_R_LAST 541U
|
||||
#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /* All resources */
|
||||
/*@}*/
|
||||
|
||||
/* NOTE - please add by replacing some of the UNUSED from above! */
|
||||
|
||||
/*!
|
||||
* Defnes for sc_ctrl_t.
|
||||
*/
|
||||
#define SC_C_TEMP 0U
|
||||
#define SC_C_TEMP_HI 1U
|
||||
#define SC_C_TEMP_LOW 2U
|
||||
#define SC_C_PXL_LINK_MST1_ADDR 3U
|
||||
#define SC_C_PXL_LINK_MST2_ADDR 4U
|
||||
#define SC_C_PXL_LINK_MST_ENB 5U
|
||||
#define SC_C_PXL_LINK_MST1_ENB 6U
|
||||
#define SC_C_PXL_LINK_MST2_ENB 7U
|
||||
#define SC_C_PXL_LINK_SLV1_ADDR 8U
|
||||
#define SC_C_PXL_LINK_SLV2_ADDR 9U
|
||||
#define SC_C_PXL_LINK_MST_VLD 10U
|
||||
#define SC_C_PXL_LINK_MST1_VLD 11U
|
||||
#define SC_C_PXL_LINK_MST2_VLD 12U
|
||||
#define SC_C_SINGLE_MODE 13U
|
||||
#define SC_C_ID 14U
|
||||
#define SC_C_PXL_CLK_POLARITY 15U
|
||||
#define SC_C_LINESTATE 16U
|
||||
#define SC_C_PCIE_G_RST 17U
|
||||
#define SC_C_PCIE_BUTTON_RST 18U
|
||||
#define SC_C_PCIE_PERST 19U
|
||||
#define SC_C_PHY_RESET 20U
|
||||
#define SC_C_PXL_LINK_RATE_CORRECTION 21U
|
||||
#define SC_C_PANIC 22U
|
||||
#define SC_C_PRIORITY_GROUP 23U
|
||||
#define SC_C_TXCLK 24U
|
||||
#define SC_C_CLKDIV 25U
|
||||
#define SC_C_DISABLE_50 26U
|
||||
#define SC_C_DISABLE_125 27U
|
||||
#define SC_C_SEL_125 28U
|
||||
#define SC_C_MODE 29U
|
||||
#define SC_C_SYNC_CTRL0 30U
|
||||
#define SC_C_KACHUNK_CNT 31U
|
||||
#define SC_C_KACHUNK_SEL 32U
|
||||
#define SC_C_SYNC_CTRL1 33U
|
||||
#define SC_C_DPI_RESET 34U
|
||||
#define SC_C_MIPI_RESET 35U
|
||||
#define SC_C_DUAL_MODE 36U
|
||||
#define SC_C_VOLTAGE 37U
|
||||
#define SC_C_PXL_LINK_SEL 38U
|
||||
#define SC_C_OFS_SEL 39U
|
||||
#define SC_C_OFS_AUDIO 40U
|
||||
#define SC_C_OFS_PERIPH 41U
|
||||
#define SC_C_OFS_IRQ 42U
|
||||
#define SC_C_RST0 43U
|
||||
#define SC_C_RST1 44U
|
||||
#define SC_C_SEL0 45U
|
||||
#define SC_C_LAST 46U
|
||||
|
||||
#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /* All pads */
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to store a boolean
|
||||
*/
|
||||
typedef uint8_t sc_bool_t;
|
||||
|
||||
/*!
|
||||
* This type is used to store a system (full-size) address.
|
||||
*/
|
||||
typedef uint64_t sc_faddr_t;
|
||||
|
||||
/*!
|
||||
* This type is used to indicate error response for most functions.
|
||||
*/
|
||||
typedef uint8_t sc_err_t;
|
||||
|
||||
/*!
|
||||
* This type is used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
typedef uint16_t sc_rsrc_t;
|
||||
|
||||
/*!
|
||||
* This type is used to indicate a control.
|
||||
*/
|
||||
typedef uint8_t sc_ctrl_t;
|
||||
|
||||
/*!
|
||||
* This type is used to indicate a pad. Valid values are SoC specific.
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
typedef uint16_t sc_pad_t;
|
||||
|
||||
/* Extra documentation of standard types */
|
||||
|
||||
#ifdef DOXYGEN
|
||||
/*!
|
||||
* Type used to declare an 8-bit integer.
|
||||
*/
|
||||
typedef __INT8_TYPE__ int8_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare a 16-bit integer.
|
||||
*/
|
||||
typedef __INT16_TYPE__ int16_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare a 32-bit integer.
|
||||
*/
|
||||
typedef __INT32_TYPE__ int32_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare a 64-bit integer.
|
||||
*/
|
||||
typedef __INT64_TYPE__ int64_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare an 8-bit unsigned integer.
|
||||
*/
|
||||
typedef __UINT8_TYPE__ uint8_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare a 16-bit unsigned integer.
|
||||
*/
|
||||
typedef __UINT16_TYPE__ uint16_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare a 32-bit unsigned integer.
|
||||
*/
|
||||
typedef __UINT32_TYPE__ uint32_t;
|
||||
|
||||
/*!
|
||||
* Type used to declare a 64-bit unsigned integer.
|
||||
*/
|
||||
typedef __UINT64_TYPE__ uint64_t;
|
||||
#endif
|
||||
|
||||
#endif /* SCI_TYPES_H */
|
||||
+539
@@ -0,0 +1,539 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Miscellaneous (MISC) function.
|
||||
*
|
||||
* @addtogroup MISC_SVC (SVC) Miscellaneous Service
|
||||
*
|
||||
* Module for the Miscellaneous (MISC) service.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SC_MISC_API_H
|
||||
#define SC_MISC_API_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/sci_types.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for type widths
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */
|
||||
/*@}*/
|
||||
|
||||
/*! Max DMA channel priority group */
|
||||
#define SC_MISC_DMA_GRP_MAX 31U
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_misc_boot_status_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */
|
||||
#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_misc_seco_auth_cmd_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */
|
||||
#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */
|
||||
#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_misc_temp_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_MISC_TEMP 0U /* Temp sensor */
|
||||
#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
|
||||
#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_misc_seco_auth_cmd_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */
|
||||
#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */
|
||||
#define SC_MISC_REL_CONTAINER 2U /* Release container */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to store a DMA channel priority group.
|
||||
*/
|
||||
typedef uint8_t sc_misc_dma_group_t;
|
||||
|
||||
/*!
|
||||
* This type is used report boot status.
|
||||
*/
|
||||
typedef uint8_t sc_misc_boot_status_t;
|
||||
|
||||
/*!
|
||||
* This type is used to issue SECO authenticate commands.
|
||||
*/
|
||||
typedef uint8_t sc_misc_seco_auth_cmd_t;
|
||||
|
||||
/*!
|
||||
* This type is used report boot status.
|
||||
*/
|
||||
typedef uint8_t sc_misc_temp_t;
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* @name Control Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function sets a miscellaneous control value.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource the control is associated with
|
||||
* @param[in] ctrl control to change
|
||||
* @param[in] val value to apply to the control
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
|
||||
* of the owner
|
||||
*
|
||||
* Refer to the [Control List](@ref CONTROLS) for valid control values.
|
||||
*/
|
||||
sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_ctrl_t ctrl, uint32_t val);
|
||||
|
||||
/*!
|
||||
* This function gets a miscellaneous control value.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource the control is associated with
|
||||
* @param[in] ctrl control to get
|
||||
* @param[out] val pointer to return the control value
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
|
||||
* of the owner
|
||||
*
|
||||
* Refer to the [Control List](@ref CONTROLS) for valid control values.
|
||||
*/
|
||||
sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_ctrl_t ctrl, uint32_t *val);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name DMA Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function configures the max DMA channel priority group for a
|
||||
* partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to assign \a max
|
||||
* @param[in] max max priority group (0-31)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent
|
||||
* of the affected partition
|
||||
*
|
||||
* Valid \a max range is 0-31 with 0 being the lowest and 31 the highest.
|
||||
* Default is the max priority group for the parent partition of \a pt.
|
||||
*/
|
||||
sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_misc_dma_group_t max);
|
||||
|
||||
/*!
|
||||
* This function configures the priority group for a DMA channel.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource DMA channel resource
|
||||
* @param[in] group priority group (0-31)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the owner or parent
|
||||
* of the owner of the DMA channel
|
||||
*
|
||||
* Valid \a group range is 0-31 with 0 being the lowest and 31 the highest.
|
||||
* The max value of \a group is limited by the partition max set using
|
||||
* sc_misc_set_max_dma_group().
|
||||
*/
|
||||
sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_misc_dma_group_t group);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Security Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function loads a SECO image.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] addr_src address of image source
|
||||
* @param[in] addr_dst address of image destination
|
||||
* @param[in] len length of image to load
|
||||
* @param[in] fw SC_TRUE = firmware load
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_PARM if word fuse index param out of range or invalid
|
||||
* - SC_ERR_UNAVAILABLE if SECO not available
|
||||
*
|
||||
* This is used to load images via the SECO. Examples include SECO
|
||||
* Firmware and IVT/CSF data used for authentication. These are usually
|
||||
* loaded into SECO TCM. \a addr_src is in secure memory.
|
||||
*
|
||||
* See the Security Reference Manual (SRM) for more info.
|
||||
*/
|
||||
sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
|
||||
sc_faddr_t addr_dst, uint32_t len,
|
||||
sc_bool_t fw);
|
||||
|
||||
/*!
|
||||
* This function is used to authenticate a SECO image or command.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] cmd authenticate command
|
||||
* @param[in] addr address of/or metadata
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_PARM if word fuse index param out of range or invalid
|
||||
* - SC_ERR_UNAVAILABLE if SECO not available
|
||||
*
|
||||
* This is used to authenticate a SECO image or issue a security
|
||||
* command. \a addr often points to an container. It is also
|
||||
* just data (or even unused) for some commands.
|
||||
*
|
||||
* See the Security Reference Manual (SRM) for more info.
|
||||
*/
|
||||
sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
|
||||
sc_misc_seco_auth_cmd_t cmd,
|
||||
sc_faddr_t addr);
|
||||
|
||||
/*!
|
||||
* This function securely writes a group of fuse words.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] addr address of message block
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_UNAVAILABLE if SECO not available
|
||||
*
|
||||
* Note \a addr must be a pointer to a signed message block.
|
||||
*
|
||||
* See the Security Reference Manual (SRM) for more info.
|
||||
*/
|
||||
sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr);
|
||||
|
||||
/*!
|
||||
* This function securely enables debug.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] addr address of message block
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_UNAVAILABLE if SECO not available
|
||||
*
|
||||
* Note \a addr must be a pointer to a signed message block.
|
||||
*
|
||||
* See the Security Reference Manual (SRM) for more info.
|
||||
*/
|
||||
sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr);
|
||||
|
||||
/*!
|
||||
* This function updates the lifecycle of the device.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] lifecycle new lifecycle
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_UNAVAILABLE if SECO not available
|
||||
*
|
||||
* This message is used for going from Open to NXP Closed to OEM Closed.
|
||||
*
|
||||
* See the Security Reference Manual (SRM) for more info.
|
||||
*/
|
||||
sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle);
|
||||
|
||||
/*!
|
||||
* This function updates the lifecycle to one of the return lifecycles.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] addr address of message block
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_UNAVAILABLE if SECO not available
|
||||
*
|
||||
* Note \a addr must be a pointer to a signed message block.
|
||||
*
|
||||
* To switch back to NXP states (Full Field Return), message must be signed
|
||||
* by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM
|
||||
* SRK.
|
||||
*
|
||||
* See the Security Reference Manual (SRM) for more info.
|
||||
*/
|
||||
sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr);
|
||||
|
||||
/*!
|
||||
* This function is used to return the SECO FW build info.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] version pointer to return build number
|
||||
* @param[out] commit pointer to return commit ID (git SHA-1)
|
||||
*/
|
||||
void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit);
|
||||
|
||||
/*!
|
||||
* This function is used to return SECO chip info.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] lc pointer to return lifecycle
|
||||
* @param[out] monotonic pointer to return monotonic counter
|
||||
* @param[out] uid_l pointer to return UID (lower 32 bits)
|
||||
* @param[out] uid_h pointer to return UID (upper 32 bits)
|
||||
*/
|
||||
sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
|
||||
uint16_t *monotonic, uint32_t *uid_l,
|
||||
uint32_t *uid_h);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Debug Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function is used output a debug character from the SCU UART.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] ch character to output
|
||||
*/
|
||||
void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch);
|
||||
|
||||
/*!
|
||||
* This function starts/stops emulation waveform capture.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] enable flag to enable/disable capture
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_UNAVAILABLE if not running on emulation
|
||||
*/
|
||||
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable);
|
||||
|
||||
/*!
|
||||
* This function is used to return the SCFW build info.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] build pointer to return build number
|
||||
* @param[out] commit pointer to return commit ID (git SHA-1)
|
||||
*/
|
||||
void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit);
|
||||
|
||||
/*!
|
||||
* This function is used to return the device's unique ID.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] id_l pointer to return lower 32-bit of ID [31:0]
|
||||
* @param[out] id_h pointer to return upper 32-bits of ID [63:32]
|
||||
*/
|
||||
void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Other Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function configures the ARI match value for PCIe/SATA resources.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource match resource
|
||||
* @param[in] resource_mst PCIe/SATA master to match
|
||||
* @param[in] ari ARI to match
|
||||
* @param[in] enable enable match or not
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the owner or parent
|
||||
* of the owner of the resource and translation
|
||||
*
|
||||
* For PCIe, the ARI is the 16-bit value that includes the bus number,
|
||||
* device number, and function number. For SATA, this value includes the
|
||||
* FISType and PM_Port.
|
||||
*/
|
||||
sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rsrc_t resource_mst, uint16_t ari,
|
||||
sc_bool_t enable);
|
||||
|
||||
/*!
|
||||
* This function reports boot status.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] status boot status
|
||||
*
|
||||
* This is used by SW partitions to report status of boot. This is
|
||||
* normally used to report a boot failure.
|
||||
*/
|
||||
void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
|
||||
|
||||
/*!
|
||||
* This function tells the SCFW that a CPU is done booting.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] cpu CPU that is done booting
|
||||
*
|
||||
* This is called by early booting CPUs to report they are done with
|
||||
* initialization. After starting early CPUs, the SCFW halts the
|
||||
* booting process until they are done. During this time, early
|
||||
* CPUs can call the SCFW with lower latency as the SCFW is idle.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the CPU owner
|
||||
*/
|
||||
sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu);
|
||||
|
||||
/*!
|
||||
* This function reads a given fuse word index.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] word fuse word index
|
||||
* @param[out] val fuse read value
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_PARM if word fuse index param out of range or invalid
|
||||
* - SC_ERR_NOACCESS if read operation failed
|
||||
* - SC_ERR_LOCKED if read operation is locked
|
||||
*/
|
||||
sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
|
||||
|
||||
/*!
|
||||
* This function writes a given fuse word index.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] word fuse word index
|
||||
* @param[in] val fuse write value
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_PARM if word fuse index param out of range or invalid
|
||||
* - SC_ERR_NOACCESS if write operation failed
|
||||
* - SC_ERR_LOCKED if write operation is locked
|
||||
*/
|
||||
sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val);
|
||||
|
||||
/*!
|
||||
* This function sets a temp sensor alarm.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource with sensor
|
||||
* @param[in] temp alarm to set
|
||||
* @param[in] celsius whole part of temp to set
|
||||
* @param[in] tenths fractional part of temp to set
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* This function will enable the alarm interrupt if the temp requested is
|
||||
* not the min/max temp. This enable automatically clears when the alarm
|
||||
* occurs and this function has to be called again to re-enable.
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_PARM if parameters invalid
|
||||
*/
|
||||
sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_misc_temp_t temp, int16_t celsius, int8_t tenths);
|
||||
|
||||
/*!
|
||||
* This function gets a temp sensor value.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource with sensor
|
||||
* @param[in] temp value to get (sensor or alarm)
|
||||
* @param[out] celsius whole part of temp to get
|
||||
* @param[out] tenths fractional part of temp to get
|
||||
*
|
||||
* @return Returns and error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors codes:
|
||||
* - SC_ERR_PARM if parameters invalid
|
||||
*/
|
||||
sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_misc_temp_t temp, int16_t *celsius,
|
||||
int8_t *tenths);
|
||||
|
||||
/*!
|
||||
* This function returns the boot device.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] dev pointer to return boot device
|
||||
*/
|
||||
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev);
|
||||
|
||||
/*!
|
||||
* This function returns the current status of the ON/OFF button.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] status pointer to return button status
|
||||
*/
|
||||
void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* SC_MISC_API_H */
|
||||
|
||||
/**@}*/
|
||||
+572
@@ -0,0 +1,572 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Pad Control (PAD) function.
|
||||
*
|
||||
* @addtogroup PAD_SVC (SVC) Pad Service
|
||||
*
|
||||
* Module for the Pad Control (PAD) service.
|
||||
*
|
||||
* @details
|
||||
*
|
||||
* Pad configuration is managed by SC firmware. The pad configuration
|
||||
* features supported by the SC firmware include:
|
||||
*
|
||||
* - Configuring the mux, input/output connection, and low-power isolation
|
||||
mode.
|
||||
* - Configuring the technology-specific pad setting such as drive strength,
|
||||
* pullup/pulldown, etc.
|
||||
* - Configuring compensation for pad groups with dual voltage capability.
|
||||
*
|
||||
* Pad functions fall into one of three categories. Generic functions are
|
||||
* common to all SoCs and all process technologies. SoC functions are raw
|
||||
* low-level functions. Technology-specific functions are specific to the
|
||||
* process technology.
|
||||
*
|
||||
* The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS)
|
||||
* for valid pad values. Note that all pads exist on a die but may or
|
||||
* may not be brought out by the specific package. Mapping of pads to
|
||||
* package pins/balls is documented in the associated Data Sheet. Some pads
|
||||
* may not be brought out because the part (die+package) is defeatured and
|
||||
* some pads may connect to the substrate in the package.
|
||||
*
|
||||
* Some pads (SC_P_COMP_*) that can be specified are not individual pads
|
||||
* but are in fact pad groups. These groups have additional configuration
|
||||
* that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More
|
||||
* info on these can be found in the associated Reference Manual.
|
||||
*
|
||||
* Pads are managed as a resource by the Resource Manager (RM). They have
|
||||
* assigned owners and only the owners can configure the pads. Some of the
|
||||
* pads are reserved for use by the SCFW itself and this can be overriden
|
||||
* with the implementation of board_config_sc(). Additionally, pads may
|
||||
* be assigned to various other partitions via the implementation of
|
||||
* board_system_config().
|
||||
*
|
||||
* Note muxing two input pads to the same IP functional signal will
|
||||
* result in undefined behavior.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SCI_PAD_API_H
|
||||
#define SCI_PAD_API_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for type widths
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_MUX_W 3 /* Width of mux parameter */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pad_config_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
|
||||
#define SC_PAD_CONFIG_OD 1U /* Open Drain */
|
||||
#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */
|
||||
#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pad_iso_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */
|
||||
#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */
|
||||
#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */
|
||||
#define SC_PAD_ISO_ON 3U /* ISO latched data is held */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pad_28fdsoi_dse_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */
|
||||
#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */
|
||||
#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pad_28fdsoi_ps_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
|
||||
#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */
|
||||
#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */
|
||||
#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pad_28fdsoi_pus_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */
|
||||
#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */
|
||||
#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */
|
||||
#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pad_wakeup_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PAD_WAKEUP_OFF 0U /* Off */
|
||||
#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */
|
||||
#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */
|
||||
#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */
|
||||
#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */
|
||||
#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to declare a pad config. It determines how the
|
||||
* output data is driven, pull-up is controlled, and input signal is
|
||||
* connected. Normal and OD are typical and only connect the input
|
||||
* when the output is not driven. The IN options are less common and
|
||||
* force an input connection even when driving the output.
|
||||
*/
|
||||
typedef uint8_t sc_pad_config_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a pad low-power isolation config.
|
||||
* ISO_LATE is the most common setting. ISO_EARLY is only used when
|
||||
* an output pad is directly determined by another input pad. The
|
||||
* other two are only used when SW wants to directly contol isolation.
|
||||
*/
|
||||
typedef uint8_t sc_pad_iso_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a drive strength. Note it is specific
|
||||
* to 28FDSOI. Also note that valid values depend on the pad type.
|
||||
*/
|
||||
typedef uint8_t sc_pad_28fdsoi_dse_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a pull select. Note it is specific
|
||||
* to 28FDSOI.
|
||||
*/
|
||||
typedef uint8_t sc_pad_28fdsoi_ps_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a pull-up select. Note it is specific
|
||||
* to 28FDSOI HSIC pads.
|
||||
*/
|
||||
typedef uint8_t sc_pad_28fdsoi_pus_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a wakeup mode of a pad.
|
||||
*/
|
||||
typedef uint8_t sc_pad_wakeup_t;
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* @name Generic Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function configures the mux settings for a pad. This includes
|
||||
* the signal mux, pad config, and low-power isolation mode.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] mux mux setting
|
||||
* @param[in] config pad config
|
||||
* @param[in] iso low-power isolation mode
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Note muxing two input pads to the same IP functional signal will
|
||||
* result in undefined behavior.
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
|
||||
|
||||
/*!
|
||||
* This function gets the mux settings for a pad. This includes
|
||||
* the signal mux, pad config, and low-power isolation mode.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] mux pointer to return mux setting
|
||||
* @param[out] config pointer to return pad config
|
||||
* @param[out] iso pointer to return low-power isolation mode
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t *mux, sc_pad_config_t *config,
|
||||
sc_pad_iso_t *iso);
|
||||
|
||||
/*!
|
||||
* This function configures the general purpose pad control. This
|
||||
* is technology dependent and includes things like drive strength,
|
||||
* slew rate, pull up/down, etc. Refer to the SoC Reference Manual
|
||||
* for bit field details.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] ctrl control value to set
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl);
|
||||
|
||||
/*!
|
||||
* This function gets the general purpose pad control. This
|
||||
* is technology dependent and includes things like drive strength,
|
||||
* slew rate, pull up/down, etc. Refer to the SoC Reference Manual
|
||||
* for bit field details.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] ctrl pointer to return control value
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
|
||||
|
||||
/*!
|
||||
* This function configures the wakeup mode of the pad.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] wakeup wakeup to set
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup);
|
||||
|
||||
/*!
|
||||
* This function gets the wakeup mode of a pad.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] wakeup pointer to return wakeup
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup);
|
||||
|
||||
/*!
|
||||
* This function configures a pad.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] mux mux setting
|
||||
* @param[in] config pad config
|
||||
* @param[in] iso low-power isolation mode
|
||||
* @param[in] ctrl control value
|
||||
* @param[in] wakeup wakeup to set
|
||||
*
|
||||
* @see sc_pad_set_mux().
|
||||
* @see sc_pad_set_gp().
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Note muxing two input pads to the same IP functional signal will
|
||||
* result in undefined behavior.
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
|
||||
sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
|
||||
sc_pad_wakeup_t wakeup);
|
||||
|
||||
/*!
|
||||
* This function gets a pad's config.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] mux pointer to return mux setting
|
||||
* @param[out] config pointer to return pad config
|
||||
* @param[out] iso pointer to return low-power isolation mode
|
||||
* @param[out] ctrl pointer to return control value
|
||||
* @param[out] wakeup pointer to return wakeup to set
|
||||
*
|
||||
* @see sc_pad_set_mux().
|
||||
* @see sc_pad_set_gp().
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
|
||||
sc_pad_config_t *config, sc_pad_iso_t *iso,
|
||||
uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SoC Specific Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function configures the settings for a pad. This setting is SoC
|
||||
* specific.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] val value to set
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val);
|
||||
|
||||
/*!
|
||||
* This function gets the settings for a pad. This setting is SoC
|
||||
* specific.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] val pointer to return setting
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Technology Specific Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function configures the pad control specific to 28FDSOI.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] dse drive strength
|
||||
* @param[in] ps pull select
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
|
||||
* - SC_ERR_UNAVAILABLE if process not applicable
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t dse,
|
||||
sc_pad_28fdsoi_ps_t ps);
|
||||
|
||||
/*!
|
||||
* This function gets the pad control specific to 28FDSOI.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] dse pointer to return drive strength
|
||||
* @param[out] ps pointer to return pull select
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
|
||||
* - SC_ERR_UNAVAILABLE if process not applicable
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t *dse,
|
||||
sc_pad_28fdsoi_ps_t *ps);
|
||||
|
||||
/*!
|
||||
* This function configures the pad control specific to 28FDSOI.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] dse drive strength
|
||||
* @param[in] hys hysteresis
|
||||
* @param[in] pus pull-up select
|
||||
* @param[in] pke pull keeper enable
|
||||
* @param[in] pue pull-up enable
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
|
||||
* - SC_ERR_UNAVAILABLE if process not applicable
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
|
||||
sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
|
||||
sc_bool_t pue);
|
||||
|
||||
/*!
|
||||
* This function gets the pad control specific to 28FDSOI.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] dse pointer to return drive strength
|
||||
* @param[out] hys pointer to return hysteresis
|
||||
* @param[out] pus pointer to return pull-up select
|
||||
* @param[out] pke pointer to return pull keeper enable
|
||||
* @param[out] pue pointer to return pull-up enable
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
|
||||
* - SC_ERR_UNAVAILABLE if process not applicable
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
|
||||
sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
|
||||
sc_bool_t *pue);
|
||||
|
||||
/*!
|
||||
* This function configures the compensation control specific to 28FDSOI.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to configure
|
||||
* @param[in] compen compensation/freeze mode
|
||||
* @param[in] fastfrz fast freeze
|
||||
* @param[in] rasrcp compensation code for PMOS
|
||||
* @param[in] rasrcn compensation code for NMOS
|
||||
* @param[in] nasrc_sel NASRC read select
|
||||
* @param[in] psw_ovr 2.5v override
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
|
||||
* - SC_ERR_UNAVAILABLE if process not applicable
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*
|
||||
* Note \a psw_ovr is only applicable to pads supporting 2.5 volt
|
||||
* operation (e.g. some Ethernet pads).
|
||||
*/
|
||||
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t compen, sc_bool_t fastfrz,
|
||||
uint8_t rasrcp, uint8_t rasrcn,
|
||||
sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
|
||||
|
||||
/*!
|
||||
* This function gets the compensation control specific to 28FDSOI.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to query
|
||||
* @param[out] compen pointer to return compensation/freeze mode
|
||||
* @param[out] fastfrz pointer to return fast freeze
|
||||
* @param[out] rasrcp pointer to return compensation code for PMOS
|
||||
* @param[out] rasrcn pointer to return compensation code for NMOS
|
||||
* @param[out] nasrc_sel pointer to return NASRC read select
|
||||
* @param[out] compok pointer to return compensation status
|
||||
* @param[out] nasrc pointer to return NASRCP/NASRCN
|
||||
* @param[out] psw_ovr pointer to return the 2.5v override
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner,
|
||||
* - SC_ERR_UNAVAILABLE if process not applicable
|
||||
*
|
||||
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
|
||||
*/
|
||||
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t *compen, sc_bool_t *fastfrz,
|
||||
uint8_t *rasrcp, uint8_t *rasrcn,
|
||||
sc_bool_t *nasrc_sel, sc_bool_t *compok,
|
||||
uint8_t *nasrc, sc_bool_t *psw_ovr);
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* SCI_PAD_API_H */
|
||||
|
||||
/**@}*/
|
||||
+684
@@ -0,0 +1,684 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Power Management (PM) function. This includes functions for power state
|
||||
* control, clock control, reset control, and wake-up event control.
|
||||
*
|
||||
* @addtogroup PM_SVC (SVC) Power Management Service
|
||||
*
|
||||
* Module for the Power Management (PM) service.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SCI_PM_API_H
|
||||
#define SCI_PM_API_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for type widths
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_POWER_MODE_W 2 /* Width of sc_pm_power_mode_t */
|
||||
#define SC_PM_CLOCK_MODE_W 3 /* Width of sc_pm_clock_mode_t */
|
||||
#define SC_PM_RESET_TYPE_W 2 /* Width of sc_pm_reset_type_t */
|
||||
#define SC_PM_RESET_REASON_W 3 /* Width of sc_pm_reset_reason_t */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for clock indexes (sc_pm_clk_t)
|
||||
*/
|
||||
/*@{*/
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for ALL parameters
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_CLK_ALL UINT8_MAX /* All clocks */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_power_mode_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_PW_MODE_OFF 0U /* Power off */
|
||||
#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
|
||||
#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
|
||||
#define SC_PM_PW_MODE_ON 3U /* Power on */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_clk_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
|
||||
#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
|
||||
#define SC_PM_CLK_PER 2U /* Peripheral clock */
|
||||
#define SC_PM_CLK_PHY 3U /* Phy clock */
|
||||
#define SC_PM_CLK_MISC 4U /* Misc clock */
|
||||
#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
|
||||
#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
|
||||
#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
|
||||
#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
|
||||
#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
|
||||
#define SC_PM_CLK_CPU 2U /* CPU clock */
|
||||
#define SC_PM_CLK_PLL 4U /* PLL */
|
||||
#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_clk_mode_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
|
||||
#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
|
||||
#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
|
||||
#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
|
||||
#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
|
||||
#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_clk_parent_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL. */
|
||||
#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */
|
||||
#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */
|
||||
#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */
|
||||
#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_reset_type_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
|
||||
#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
|
||||
#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_reset_cause_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_RESET_CAUSE_TEMP 0U /* Reset due to temp panic alarm */
|
||||
#define SC_PM_RESET_CAUSE_FAULT 1U /* Reset due to fault exception */
|
||||
#define SC_PM_RESET_CAUSE_IRQ 2U /* Reset due to SCU reset IRQ */
|
||||
#define SC_PM_RESET_CAUSE_WDOG 3U /* Reset due to SW WDOG */
|
||||
#define SC_PM_RESET_CAUSE_API 4U /* Reset due to pm_reset() or monitor */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_reset_reason_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
|
||||
#define SC_PM_RESET_REASON_WARM 1U /* Warm reset */
|
||||
#define SC_PM_RESET_REASON_SW 2U /* Software reset */
|
||||
#define SC_PM_RESET_REASON_WDOG 3U /* Watchdog reset */
|
||||
#define SC_PM_RESET_REASON_LOCKUP 4U /* Lockup reset */
|
||||
#define SC_PM_RESET_REASON_TAMPER 5U /* Tamper reset */
|
||||
#define SC_PM_RESET_REASON_TEMP 6U /* Temp reset */
|
||||
#define SC_PM_RESET_REASON_LOW_VOLT 7U /* Low voltage reset */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_sys_if_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
|
||||
#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
|
||||
#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
|
||||
#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_pm_wake_src_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */
|
||||
#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
|
||||
#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
|
||||
#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
|
||||
#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to declare a power mode. Note resources only use
|
||||
* SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
|
||||
* as system power modes.
|
||||
*/
|
||||
typedef uint8_t sc_pm_power_mode_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a clock.
|
||||
*/
|
||||
typedef uint8_t sc_pm_clk_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a clock mode.
|
||||
*/
|
||||
typedef uint8_t sc_pm_clk_mode_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare the clock parent.
|
||||
*/
|
||||
typedef uint8_t sc_pm_clk_parent_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare clock rates.
|
||||
*/
|
||||
typedef uint32_t sc_pm_clock_rate_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a desired reset type.
|
||||
*/
|
||||
typedef uint8_t sc_pm_reset_type_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a desired reset type.
|
||||
*/
|
||||
typedef uint8_t sc_pm_reset_cause;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a reason for a reset.
|
||||
*/
|
||||
typedef uint8_t sc_pm_reset_reason_t;
|
||||
|
||||
/*!
|
||||
* This type is used to specify a system-level interface to be power managed.
|
||||
*/
|
||||
typedef uint8_t sc_pm_sys_if_t;
|
||||
|
||||
/*!
|
||||
* This type is used to specify a wake source for CPU resources.
|
||||
*/
|
||||
typedef uint8_t sc_pm_wake_src_t;
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* @name Power Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function sets the system power mode. Only the owner of the
|
||||
* SC_R_SYSTEM resource can do this.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] mode power mode to apply
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid mode,
|
||||
* - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
|
||||
*
|
||||
* @see sc_pm_set_sys_power_mode().
|
||||
*/
|
||||
sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode);
|
||||
|
||||
/*!
|
||||
* This function sets the power mode of a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition
|
||||
* @param[in] mode power mode to apply
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid partition or mode,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the owner or
|
||||
* parent of \a pt
|
||||
*
|
||||
* The power mode of the partitions is a max power any resource will
|
||||
* be set to. Calling this will result in all resources owned
|
||||
* by \a pt to have their power changed to the lower of \a mode or the
|
||||
* individual resource mode set using sc_pm_set_resource_power_mode().
|
||||
*/
|
||||
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_pm_power_mode_t mode);
|
||||
|
||||
/*!
|
||||
* This function gets the power mode of a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition
|
||||
* @param[out] mode pointer to return power mode
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid partition
|
||||
*/
|
||||
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_pm_power_mode_t *mode);
|
||||
|
||||
/*!
|
||||
* This function sets the power mode of a resource.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] mode power mode to apply
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or mode,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
|
||||
* or parent of the owner
|
||||
*
|
||||
* This function will record the individual resource power mode
|
||||
* and change it if the requested mode is lower than or equal to the
|
||||
* partition power mode set with sc_pm_set_partition_power_mode().
|
||||
* In other words, the power mode of the resource will be the minimum
|
||||
* of the resource power mode and the partition power mode.
|
||||
*
|
||||
* Note some resources are still not accessible even when powered up if bus
|
||||
* transactions go through a fabric not powered up. Examples of this are
|
||||
* resources in display and capture subsystems which require the display
|
||||
* controller or the imaging subsytem to be powered up first.
|
||||
*
|
||||
* Not that resources are grouped into power domains by the underlying
|
||||
* hardware. If any resource in the domain is on, the entire power domain
|
||||
* will be on. Other power domains required to access the resource will
|
||||
* also be turned on. Clocks required to access the peripheral will be
|
||||
* turned on. Refer to the SoC RM for more info on power domains and access
|
||||
* infrastructure (bus fabrics, clock domains, etc.).
|
||||
*/
|
||||
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode);
|
||||
|
||||
/*!
|
||||
* This function gets the power mode of a resource.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[out] mode pointer to return power mode
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value
|
||||
* returned does not reflect the power mode of the partition..
|
||||
*/
|
||||
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t *mode);
|
||||
|
||||
/*!
|
||||
* This function requests the low power mode some of the resources
|
||||
* can enter based on their state. This API is only valid for the
|
||||
* following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2,
|
||||
* SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35,
|
||||
* SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3.
|
||||
* For all other resources it will return SC_ERR_PARAM.
|
||||
* This function will set the low power mode the cores, cluster
|
||||
* and cluster associated resources will enter when all the cores
|
||||
* in a given cluster execute WFI
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] mode power mode to apply
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
*/
|
||||
sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode);
|
||||
|
||||
/*!
|
||||
* This function requests low-power mode entry for CPU/cluster
|
||||
* resources. This API is only valid for the following resources:
|
||||
* SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x,
|
||||
* SC_R_CCI. For all other resources it will return SC_ERR_PARAM.
|
||||
* For individual core resources, the specified power mode
|
||||
* and wake source will be applied after the core has entered
|
||||
* WFI. For cluster resources, the specified power mode is
|
||||
* applied after all cores in the cluster have entered low-power mode.
|
||||
* For multicluster resources, the specified power mode is applied
|
||||
* after all clusters have reached low-power mode.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] mode power mode to apply
|
||||
* @param[in] wake_src wake source for low-power exit
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
*/
|
||||
sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode,
|
||||
sc_pm_wake_src_t wake_src);
|
||||
|
||||
/*!
|
||||
* This function is used to set the resume address of a CPU.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the CPU resource
|
||||
* @param[in] address 64-bit resume address
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or address,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
|
||||
* resource (CPU) owner
|
||||
*/
|
||||
sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_faddr_t address);
|
||||
|
||||
/*!
|
||||
* This function is used to set parameters for CPU resume from
|
||||
* low-power mode.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the CPU resource
|
||||
* @param[in] isPrimary set SC_TRUE if primary wake CPU
|
||||
* @param[in] address 64-bit resume address
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or address,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
|
||||
* resource (CPU) owner
|
||||
*/
|
||||
sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_bool_t isPrimary, sc_faddr_t address);
|
||||
|
||||
/*!
|
||||
* This function requests the power mode configuration for system-level
|
||||
* interfaces including messaging units, interconnect, and memories. This API
|
||||
* is only valid for the following resources : SC_R_A53, SC_R_A72, and
|
||||
* SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM.
|
||||
* The requested power mode will be captured and applied to system-level
|
||||
* resources as system conditions allow.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] sys_if system-level interface to be configured
|
||||
* @param[in] hpm high-power mode for the system interface
|
||||
* @param[in] lpm low-power mode for the system interface
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
*/
|
||||
sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_sys_if_t sys_if,
|
||||
sc_pm_power_mode_t hpm,
|
||||
sc_pm_power_mode_t lpm);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Clock/PLL Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function sets the rate of a resource's clock/PLL.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] clk clock/PLL to affect
|
||||
* @param[in,out] rate pointer to rate to set,
|
||||
* return actual rate
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or clock/PLL,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
|
||||
* or parent of the owner,
|
||||
* - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource,
|
||||
* - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL)
|
||||
*
|
||||
* Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
|
||||
*/
|
||||
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
|
||||
|
||||
/*!
|
||||
* This function gets the rate of a resource's clock/PLL.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] clk clock/PLL to affect
|
||||
* @param[out] rate pointer to return rate
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or clock/PLL,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
|
||||
* or parent of the owner,
|
||||
* - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource
|
||||
*
|
||||
* Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
|
||||
*/
|
||||
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
|
||||
|
||||
/*!
|
||||
* This function enables/disables a resource's clock.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] clk clock to affect
|
||||
* @param[in] enable enable if SC_TRUE; otherwise disabled
|
||||
* @param[in] autog HW auto clock gating
|
||||
*
|
||||
* If \a resource is SC_R_ALL then all resources owned will be affected.
|
||||
* No error will be returned.
|
||||
*
|
||||
* If \a clk is SC_PM_CLK_ALL, then an error will be returned if any
|
||||
* of the available clocks returns an error.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or clock,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
|
||||
* or parent of the owner,
|
||||
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
|
||||
*
|
||||
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
|
||||
*/
|
||||
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
|
||||
|
||||
/*!
|
||||
* This function sets the parent of a resource's clock.
|
||||
* This function should only be called when the clock is disabled.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] clk clock to affect
|
||||
* @param[in] parent New parent of the clock.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or clock,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
|
||||
* or parent of the owner,
|
||||
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
|
||||
* - SC_ERR_BUSY if clock is currently enabled.
|
||||
* - SC_ERR_NOPOWER if resource not powered
|
||||
*
|
||||
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
|
||||
*/
|
||||
sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
|
||||
|
||||
/*!
|
||||
* This function gets the parent of a resource's clock.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the resource
|
||||
* @param[in] clk clock to affect
|
||||
* @param[out] parent pointer to return parent of clock.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or clock,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
|
||||
* or parent of the owner,
|
||||
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
|
||||
*
|
||||
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
|
||||
*/
|
||||
sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Reset Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function is used to reset the system. Only the owner of the
|
||||
* SC_R_SYSTEM resource can do this.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] type reset type
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid type,
|
||||
* - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
|
||||
*
|
||||
* If this function returns, then the reset did not occur due to an
|
||||
* invalid parameter.
|
||||
*/
|
||||
sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
|
||||
|
||||
/*!
|
||||
* This function gets a caller's reset reason.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] reason pointer to return reset reason
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
|
||||
|
||||
/*!
|
||||
* This function is used to boot a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to boot
|
||||
* @param[in] resource_cpu ID of the CPU resource to start
|
||||
* @param[in] boot_addr 64-bit boot address
|
||||
* @param[in] resource_mu ID of the MU that must be powered
|
||||
* @param[in] resource_dev ID of the boot device that must be powered
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid partition, resource, or addr,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
|
||||
* partition to boot
|
||||
*/
|
||||
sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
|
||||
sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
|
||||
|
||||
/*!
|
||||
* This function is used to reboot the caller's partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] type reset type
|
||||
*
|
||||
* If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
|
||||
* the calling partition will be reset if possible. SC state (partitions,
|
||||
* power, clocks, etc.) is reset. The boot SW of the booting CPU must be
|
||||
* able to handle peripherals that that are not reset.
|
||||
*
|
||||
* If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
|
||||
* SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
|
||||
* of the booting CPU must be able to handle peripherals and SC state that
|
||||
* that are not reset.
|
||||
*
|
||||
* If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
|
||||
*
|
||||
* If this function returns, then the reset did not occur due to an
|
||||
* invalid parameter.
|
||||
*/
|
||||
void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
|
||||
|
||||
/*!
|
||||
* This function is used to reboot a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to reboot
|
||||
* @param[in] type reset type
|
||||
*
|
||||
* If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by
|
||||
* the calling partition will be reset if possible. SC state (partitions,
|
||||
* power, clocks, etc.) is reset. The boot SW of the booting CPU must be
|
||||
* able to handle peripherals that that are not reset.
|
||||
*
|
||||
* If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
|
||||
* SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
|
||||
* of the booting CPU must be able to handle peripherals and SC state that
|
||||
* that are not reset.
|
||||
*
|
||||
* If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid partition or type
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
|
||||
*
|
||||
* Most peripherals owned by the partition will be reset if
|
||||
* possible. SC state (partitions, power, clocks, etc.) is reset. The
|
||||
* boot SW of the booting CPU must be able to handle peripherals that
|
||||
* that are not reset.
|
||||
*/
|
||||
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_pm_reset_type_t type);
|
||||
|
||||
/*!
|
||||
* This function is used to start/stop a CPU.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource ID of the CPU resource
|
||||
* @param[in] enable start if SC_TRUE; otherwise stop
|
||||
* @param[in] address 64-bit boot address
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid resource or address,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
|
||||
* resource (CPU) owner
|
||||
*/
|
||||
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
|
||||
sc_faddr_t address);
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* SCI_PM_API_H */
|
||||
|
||||
/**@}*/
|
||||
+757
@@ -0,0 +1,757 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Resource Management (RM) function. This includes functions for
|
||||
* partitioning resources, pads, and memory regions.
|
||||
*
|
||||
* @addtogroup RM_SVC (SVC) Resource Management Service
|
||||
*
|
||||
* Module for the Resource Management (RM) service.
|
||||
*
|
||||
* @includedoc rm/details.dox
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SCI_RM_API_H
|
||||
#define SCI_RM_API_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for type widths
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_RM_PARTITION_W 5 /* Width of sc_rm_pt_t */
|
||||
#define SC_RM_MEMREG_W 6 /* Width of sc_rm_mr_t */
|
||||
#define SC_RM_DID_W 4 /* Width of sc_rm_did_t */
|
||||
#define SC_RM_SID_W 6 /* Width of sc_rm_sid_t */
|
||||
#define SC_RM_SPA_W 2 /* Width of sc_rm_spa_t */
|
||||
#define SC_RM_PERM_W 3 /* Width of sc_rm_perm_t */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for ALL parameters
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */
|
||||
#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_rm_spa_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
|
||||
#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
|
||||
#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
|
||||
#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_rm_perm_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_RM_PERM_NONE 0U /* No access */
|
||||
#define SC_RM_PERM_SEC_R 1U /* Secure RO */
|
||||
#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
|
||||
#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
|
||||
#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
|
||||
#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
|
||||
#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
|
||||
#define SC_RM_PERM_FULL 7U /* Full access */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to declare a resource partition.
|
||||
*/
|
||||
typedef uint8_t sc_rm_pt_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a memory region.
|
||||
*/
|
||||
typedef uint8_t sc_rm_mr_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a resource domain ID used by the
|
||||
* isolation HW.
|
||||
*/
|
||||
typedef uint8_t sc_rm_did_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare an SMMU StreamID.
|
||||
*/
|
||||
typedef uint16_t sc_rm_sid_t;
|
||||
|
||||
/*!
|
||||
* This type is a used to declare master transaction attributes.
|
||||
*/
|
||||
typedef uint8_t sc_rm_spa_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a resource/memory region access permission.
|
||||
* Refer to the XRDC2 Block Guide for more information.
|
||||
*/
|
||||
typedef uint8_t sc_rm_perm_t;
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* @name Partition Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function requests that the SC create a new resource partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] pt return handle for partition; used for subsequent function
|
||||
* calls associated with this partition
|
||||
* @param[in] secure boolean indicating if this partition should be secure; only
|
||||
* valid if caller is secure
|
||||
* @param[in] isolated boolean indicating if this partition should be HW isolated
|
||||
* via XRDC; set SC_TRUE if new DID is desired
|
||||
* @param[in] restricted boolean indicating if this partition should be restricted; set
|
||||
* SC_TRUE if masters in this partition cannot create new partitions
|
||||
* @param[in] grant boolean indicating if this partition should always grant
|
||||
* access and control to the parent
|
||||
* @param[in] coherent boolean indicating if this partition is coherent;
|
||||
* set SC_TRUE if only this partition will contain both AP clusters
|
||||
* and they will be coherent via the CCI
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested,
|
||||
* - SC_ERR_LOCKED if caller's partition is locked,
|
||||
* - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space)
|
||||
*
|
||||
* Marking as non-secure prevents subsequent functions from configuring masters in this
|
||||
* partition to assert the secure signal. If restricted then the new partition is limited
|
||||
* in what functions it can call, especially those associated with managing partitions.
|
||||
*
|
||||
* The grant option is usually used to isolate a bus master's traffic to specific
|
||||
* memory without isolating the peripheral interface of the master or the API
|
||||
* controls of that master.
|
||||
*/
|
||||
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
|
||||
sc_bool_t isolated, sc_bool_t restricted,
|
||||
sc_bool_t grant, sc_bool_t coherent);
|
||||
|
||||
/*!
|
||||
* This function makes a partition confidential.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition that is granting
|
||||
* @param[in] retro retroactive
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if \a pt out of range,
|
||||
* - SC_ERR_NOACCESS if caller's not allowed to change \a pt
|
||||
* - SC_ERR_LOCKED if partition \a pt is locked
|
||||
*
|
||||
* Call to make a partition confidential. Confidential means only this
|
||||
* partition should be able to grant access permissions to this partition.
|
||||
*
|
||||
* If retroactive, then all resources owned by other partitions will have
|
||||
* access rights for this partition removed, even if locked.
|
||||
*/
|
||||
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro);
|
||||
|
||||
/*!
|
||||
* This function frees a partition and assigns all resources to the caller.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to free
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if \a pt out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if \a pt is the SC partition,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
|
||||
* - SC_ERR_LOCKED if \a pt or caller's partition is locked
|
||||
*
|
||||
* All resources, memory regions, and pads are assigned to the caller/parent.
|
||||
* The partition watchdog is disabled (even if locked). DID is freed.
|
||||
*/
|
||||
sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
|
||||
|
||||
/*!
|
||||
* This function returns the DID of a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
*
|
||||
* @return Returns the domain ID (DID) of the caller's partition.
|
||||
*
|
||||
* The DID is a SoC-specific internal ID used by the HW resource
|
||||
* protection mechanism. It is only required by clients when using the
|
||||
* SEMA42 module as the DID is sometimes connected to the master ID.
|
||||
*/
|
||||
sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc);
|
||||
|
||||
/*!
|
||||
* This function forces a partition to use a specific static DID.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to assign \a did
|
||||
* @param[in] did static DID to assign
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if \a pt or \a did out of range,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
|
||||
* - SC_ERR_LOCKED if \a pt is locked
|
||||
*
|
||||
* Assumes no assigned resources or memory regions yet! The number of static
|
||||
* DID is fixed by the SC at boot.
|
||||
*/
|
||||
sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did);
|
||||
|
||||
/*!
|
||||
* This function locks a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to lock
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if \a pt out of range,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
|
||||
*
|
||||
* If a partition is locked it cannot be freed, have resources/pads assigned
|
||||
* to/from it, memory regions created/assigned, DID changed, or parent changed.
|
||||
*/
|
||||
sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt);
|
||||
|
||||
/*!
|
||||
* This function gets the partition handle of the caller.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] pt return handle for caller's partition
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
|
||||
|
||||
/*!
|
||||
* This function sets a new parent for a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition for which parent is to be
|
||||
* changed
|
||||
* @param[in] pt_parent handle of partition to set as parent
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
|
||||
* - SC_ERR_LOCKED if either partition is locked
|
||||
*/
|
||||
sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
|
||||
|
||||
/*!
|
||||
* This function moves all movable resources/pads owned by a source partition
|
||||
* to a destination partition. It can be used to more quickly set up a new
|
||||
* partition if a majority of the caller's resources are to be moved to a
|
||||
* new partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt_src handle of partition from which resources should
|
||||
* be moved from
|
||||
* @param[in] pt_dst handle of partition to which resources should be
|
||||
* moved to
|
||||
* @param[in] move_rsrc boolean to indicate if resources should be moved
|
||||
* @param[in] move_pads boolean to indicate if pads should be moved
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* By default, all resources are movable. This can be changed using the
|
||||
* sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU
|
||||
* bypass.
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the
|
||||
* parent of \a pt_src,
|
||||
* - SC_ERR_LOCKED if either partition is locked
|
||||
*/
|
||||
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
|
||||
sc_bool_t move_rsrc, sc_bool_t move_pads);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Resource Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function assigns ownership of a resource to a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to which resource should be
|
||||
* assigned
|
||||
* @param[in] resource resource to assign
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* This action resets the resource's master and peripheral attributes.
|
||||
* Privilege attribute will be PASSTHRU, security attribute will be
|
||||
* ASSERT if the partition si secure and NEGATE if it is not, and
|
||||
* masters will defaulted to SMMU bypass. Access permissions will reset
|
||||
* to SEC_RW for the owning partition only for secure partitions, FULL for
|
||||
* non-secure. DEfault is no access by other partitions.
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
|
||||
* of the owner,
|
||||
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
|
||||
*/
|
||||
sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
|
||||
|
||||
/*!
|
||||
* This function flags resources as movable or not.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource_fst first resource for which flag should be set
|
||||
* @param[in] resource_lst last resource for which flag should be set
|
||||
* @param[in] movable movable flag (SC_TRUE is movable)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if resources are out of range,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner,
|
||||
* - SC_ERR_LOCKED if the owning partition is locked
|
||||
*
|
||||
* This function is used to determine the set of resources that will be
|
||||
* moved using the sc_rm_move_all() function. All resources are movable
|
||||
* by default so this function is normally used to prevent a set of
|
||||
* resources from moving.
|
||||
*/
|
||||
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
|
||||
sc_rsrc_t resource_lst, sc_bool_t movable);
|
||||
|
||||
/*!
|
||||
* This function flags all of a subsystem's resources as movable
|
||||
* or not.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource to use to identify subsystem
|
||||
* @param[in] movable movable flag (SC_TRUE is movable)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if a function argument is out of range
|
||||
*
|
||||
* Note \a resource is used to find the associated subsystem. Only
|
||||
* resources owned by the caller are set.
|
||||
*/
|
||||
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_bool_t movable);
|
||||
|
||||
/*!
|
||||
* This function sets attributes for a resource which is a bus master (i.e.
|
||||
* capable of DMA).
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource master resource for which attributes should apply
|
||||
* @param[in] sa security attribute
|
||||
* @param[in] pa privilege attribute
|
||||
* @param[in] smmu_bypass SMMU bypass mode
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner,
|
||||
* - SC_ERR_LOCKED if the owning partition is locked
|
||||
*
|
||||
* This function configures how the HW isolation will see bus transactions
|
||||
* from the specified master. Note the security attribute will only be
|
||||
* changed if the caller's partition is secure.
|
||||
*/
|
||||
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_spa_t sa, sc_rm_spa_t pa,
|
||||
sc_bool_t smmu_bypass);
|
||||
|
||||
/*!
|
||||
* This function sets the StreamID for a resource which is a bus master (i.e.
|
||||
* capable of DMA).
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource master resource for which attributes should apply
|
||||
* @param[in] sid StreamID
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
|
||||
* of the owner,
|
||||
* - SC_ERR_LOCKED if the owning partition is locked
|
||||
*
|
||||
* This function configures the SID attribute associated with all bus transactions
|
||||
* from this master. Note 0 is not a valid SID as it is reserved to indicate
|
||||
* bypass.
|
||||
*/
|
||||
sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_sid_t sid);
|
||||
|
||||
/*!
|
||||
* This function sets access permissions for a peripheral resource.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource peripheral resource for which permissions should apply
|
||||
* @param[in] pt handle of partition \a perm should by applied for
|
||||
* @param[in] perm permissions to apply to \a resource for \a pt
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent
|
||||
* of the owner,
|
||||
* - SC_ERR_LOCKED if the owning partition is locked
|
||||
* - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
|
||||
*
|
||||
* This function configures how the HW isolation will restrict access to a
|
||||
* peripheral based on the attributes of a transaction from bus master.
|
||||
*/
|
||||
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_pt_t pt, sc_rm_perm_t perm);
|
||||
|
||||
/*!
|
||||
* This function gets ownership status of a resource.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource to check
|
||||
*
|
||||
* @return Returns a boolean (SC_TRUE if caller's partition owns the resource).
|
||||
*
|
||||
* If \a resource is out of range then SC_FALSE is returned.
|
||||
*/
|
||||
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
|
||||
|
||||
/*!
|
||||
* This function is used to test if a resource is a bus master.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource to check
|
||||
*
|
||||
* @return Returns a boolean (SC_TRUE if the resource is a bus master).
|
||||
*
|
||||
* If \a resource is out of range then SC_FALSE is returned.
|
||||
*/
|
||||
sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
|
||||
|
||||
/*!
|
||||
* This function is used to test if a resource is a peripheral.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource to check
|
||||
*
|
||||
* @return Returns a boolean (SC_TRUE if the resource is a peripheral).
|
||||
*
|
||||
* If \a resource is out of range then SC_FALSE is returned.
|
||||
*/
|
||||
sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
|
||||
|
||||
/*!
|
||||
* This function is used to obtain info about a resource.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] resource resource to inquire about
|
||||
* @param[out] sid pointer to return StreamID
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if \a resource is out of range
|
||||
*/
|
||||
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_sid_t *sid);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Memory Region Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function requests that the SC create a new memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] mr return handle for region; used for
|
||||
* subsequent function calls
|
||||
* associated with this region
|
||||
* @param[in] addr_start start address of region (physical)
|
||||
* @param[in] addr_end end address of region (physical)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if the new memory region is misaligned,
|
||||
* - SC_ERR_LOCKED if caller's partition is locked,
|
||||
* - SC_ERR_PARM if the new memory region spans multiple existing regions,
|
||||
* - SC_ERR_NOACCESS if caller's partition does not own the memory containing
|
||||
* the new region,
|
||||
* - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
|
||||
* space)
|
||||
*
|
||||
* The area covered by the memory region must currently be owned by the caller.
|
||||
* By default, the new region will have access permission set to allow the
|
||||
* caller to access.
|
||||
*/
|
||||
sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
|
||||
sc_faddr_t addr_start, sc_faddr_t addr_end);
|
||||
|
||||
/*!
|
||||
* This function requests that the SC split a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] mr handle of memory region to split
|
||||
* @param[out] mr_ret return handle for new region; used for
|
||||
* subsequent function calls
|
||||
* associated with this region
|
||||
* @param[in] addr_start start address of region (physical)
|
||||
* @param[in] addr_end end address of region (physical)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if the new memory region is not start/end part of mr,
|
||||
* - SC_ERR_LOCKED if caller's partition is locked,
|
||||
* - SC_ERR_PARM if the new memory region spans multiple existing regions,
|
||||
* - SC_ERR_NOACCESS if caller's partition does not own the memory containing
|
||||
* the new region,
|
||||
* - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
|
||||
* space)
|
||||
*
|
||||
* Note the new region must start or end on the split region.
|
||||
*/
|
||||
sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
|
||||
sc_faddr_t addr_end);
|
||||
|
||||
/*!
|
||||
* This function frees a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] mr handle of memory region to free
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if \a mr out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr,
|
||||
* - SC_ERR_LOCKED if the owning partition of \a mr is locked
|
||||
*/
|
||||
sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr);
|
||||
|
||||
/*!
|
||||
* Internal SC function to find a memory region.
|
||||
*
|
||||
* @see sc_rm_find_memreg().
|
||||
*/
|
||||
/*!
|
||||
* This function finds a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] mr return handle for region; used for
|
||||
* subsequent function calls
|
||||
* associated with this region
|
||||
* @param[in] addr_start start address of region to search for
|
||||
* @param[in] addr_end end address of region to search for
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOTFOUND if region not found,
|
||||
*
|
||||
* Searches only for regions owned by the caller. Finds first
|
||||
* region containing the range specified.
|
||||
*/
|
||||
sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
|
||||
sc_faddr_t addr_start, sc_faddr_t addr_end);
|
||||
|
||||
/*!
|
||||
* This function assigns ownership of a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to which memory region
|
||||
* should be assigned
|
||||
* @param[in] mr handle of memory region to assign
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent
|
||||
* of the owner,
|
||||
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
|
||||
*/
|
||||
sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr);
|
||||
|
||||
/*!
|
||||
* This function sets access permissions for a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] mr handle of memory region for which permissions
|
||||
* should apply
|
||||
* @param[in] pt handle of partition \a perm should by
|
||||
* applied for
|
||||
* @param[in] perm permissions to apply to \a mr for \a pt
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the region owner or parent
|
||||
* of the owner,
|
||||
* - SC_ERR_LOCKED if the owning partition is locked
|
||||
* - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
|
||||
*
|
||||
* This function configures how the HW isolation will restrict access to a
|
||||
* memory region based on the attributes of a transaction from bus master.
|
||||
*/
|
||||
sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_rm_pt_t pt, sc_rm_perm_t perm);
|
||||
|
||||
/*!
|
||||
* This function gets ownership status of a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] mr handle of memory region to check
|
||||
*
|
||||
* @return Returns a boolean (SC_TRUE if caller's partition owns the
|
||||
* memory region).
|
||||
*
|
||||
* If \a mr is out of range then SC_FALSE is returned.
|
||||
*/
|
||||
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
|
||||
|
||||
/*!
|
||||
* This function is used to obtain info about a memory region.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] mr handle of memory region to inquire about
|
||||
* @param[out] addr_start pointer to return start address
|
||||
* @param[out] addr_end pointer to return end address
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if \a mr is out of range
|
||||
*/
|
||||
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_faddr_t *addr_start, sc_faddr_t *addr_end);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Pad Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function assigns ownership of a pad to a partition.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt handle of partition to which pad should
|
||||
* be assigned
|
||||
* @param[in] pad pad to assign
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_NOACCESS if caller's partition is restricted,
|
||||
* - SC_PARM if arguments out of range or invalid,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent
|
||||
* of the owner,
|
||||
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
|
||||
*/
|
||||
sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
|
||||
|
||||
/*!
|
||||
* This function flags pads as movable or not.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad_fst first pad for which flag should be set
|
||||
* @param[in] pad_lst last pad for which flag should be set
|
||||
* @param[in] movable movable flag (SC_TRUE is movable)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_PARM if pads are out of range,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner,
|
||||
* - SC_ERR_LOCKED if the owning partition is locked
|
||||
*
|
||||
* This function is used to determine the set of pads that will be
|
||||
* moved using the sc_rm_move_all() function. All pads are movable
|
||||
* by default so this function is normally used to prevent a set of
|
||||
* pads from moving.
|
||||
*/
|
||||
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
|
||||
sc_pad_t pad_lst, sc_bool_t movable);
|
||||
|
||||
/*!
|
||||
* This function gets ownership status of a pad.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pad pad to check
|
||||
*
|
||||
* @return Returns a boolean (SC_TRUE if caller's partition owns the pad).
|
||||
*
|
||||
* If \a pad is out of range then SC_FALSE is returned.
|
||||
*/
|
||||
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Debug Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function dumps the RM state for debug.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
*/
|
||||
void sc_rm_dump(sc_ipc_t ipc);
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* SCI_RM_API_H */
|
||||
|
||||
/**@}*/
|
||||
+358
@@ -0,0 +1,358 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Timer function.
|
||||
*
|
||||
* @addtogroup TIMER_SVC (SVC) Timer Service
|
||||
*
|
||||
* Module for the Timer service. This includes support for the watchdog, RTC,
|
||||
* and system counter. Note every resource partition has a watchdog it can
|
||||
* use.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SC_TIMER_API_H
|
||||
#define SC_TIMER_API_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for type widths
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Defines for sc_timer_wdog_action_t
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */
|
||||
#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */
|
||||
#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */
|
||||
#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */
|
||||
#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/*!
|
||||
* This type is used to configure the watchdog action.
|
||||
*/
|
||||
typedef uint8_t sc_timer_wdog_action_t;
|
||||
|
||||
/*!
|
||||
* This type is used to declare a watchdog time value in milliseconds.
|
||||
*/
|
||||
typedef uint32_t sc_timer_wdog_time_t;
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* @name Watchdog Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function sets the watchdog timeout in milliseconds. If not
|
||||
* set then the timeout defaults to the max. Once locked this value
|
||||
* cannot be changed.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] timeout timeout period for the watchdog
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED
|
||||
* = locked).
|
||||
*/
|
||||
sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout);
|
||||
|
||||
/*!
|
||||
* This function sets the watchdog pre-timeout in milliseconds. If not
|
||||
* set then the pre-timeout defaults to the max. Once locked this value
|
||||
* cannot be changed.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pre_timeout pre-timeout period for the watchdog
|
||||
*
|
||||
* When the pre-timeout expires an IRQ will be generated. Note this timeout
|
||||
* clears when the IRQ is triggered. An IRQ is generated for the failing
|
||||
* partition and all of its child partitions.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
|
||||
sc_timer_wdog_time_t pre_timeout);
|
||||
|
||||
/*!
|
||||
* This function starts the watchdog.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] lock boolean indicating the lock status
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* If \a lock is set then the watchdog cannot be stopped or the timeout
|
||||
* period changed.
|
||||
*/
|
||||
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock);
|
||||
|
||||
/*!
|
||||
* This function stops the watchdog if it is not locked.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED
|
||||
* = locked).
|
||||
*/
|
||||
sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc);
|
||||
|
||||
/*!
|
||||
* This function pings (services, kicks) the watchdog resetting the time
|
||||
* before expiration back to the timeout.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc);
|
||||
|
||||
/*!
|
||||
* This function gets the status of the watchdog. All arguments are
|
||||
* in milliseconds.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] timeout pointer to return the timeout
|
||||
* @param[out] max_timeout pointer to return the max timeout
|
||||
* @param[out] remaining_time pointer to return the time remaining
|
||||
* until trigger
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
|
||||
sc_timer_wdog_time_t *timeout,
|
||||
sc_timer_wdog_time_t *max_timeout,
|
||||
sc_timer_wdog_time_t *remaining_time);
|
||||
|
||||
/*!
|
||||
* This function gets the status of the watchdog of a partition. All
|
||||
* arguments are in milliseconds.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt partition to query
|
||||
* @param[out] enb pointer to return enable status
|
||||
* @param[out] timeout pointer to return the timeout
|
||||
* @param[out] remaining_time pointer to return the time remaining
|
||||
* until trigger
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_bool_t *enb,
|
||||
sc_timer_wdog_time_t *timeout,
|
||||
sc_timer_wdog_time_t *remaining_time);
|
||||
|
||||
/*!
|
||||
* This function configures the action to be taken when a watchdog
|
||||
* expires.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] pt partition to affect
|
||||
* @param[in] action action to take
|
||||
*
|
||||
* Default action is inherited from the parent.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid parameters,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner,
|
||||
* - SC_ERR_LOCKED if the watchdog is locked
|
||||
*/
|
||||
sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
|
||||
sc_rm_pt_t pt, sc_timer_wdog_action_t action);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Real-Time Clock (RTC) Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function sets the RTC time. Only the owner of the SC_R_SYSTEM
|
||||
* resource can set the time.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] year year (min 1970)
|
||||
* @param[in] mon month (1-12)
|
||||
* @param[in] day day of the month (1-31)
|
||||
* @param[in] hour hour (0-23)
|
||||
* @param[in] min minute (0-59)
|
||||
* @param[in] sec second (0-59)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters,
|
||||
* - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner
|
||||
*/
|
||||
sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
|
||||
uint8_t day, uint8_t hour, uint8_t min,
|
||||
uint8_t sec);
|
||||
|
||||
/*!
|
||||
* This function gets the RTC time.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] year pointer to return year (min 1970)
|
||||
* @param[out] mon pointer to return month (1-12)
|
||||
* @param[out] day pointer to return day of the month (1-31)
|
||||
* @param[out] hour pointer to return hour (0-23)
|
||||
* @param[out] min pointer to return minute (0-59)
|
||||
* @param[out] sec pointer to return second (0-59)
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
|
||||
uint8_t *day, uint8_t *hour, uint8_t *min,
|
||||
uint8_t *sec);
|
||||
|
||||
/*!
|
||||
* This function gets the RTC time in seconds since 1/1/1970.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[out] sec pointer to return second
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
|
||||
|
||||
/*!
|
||||
* This function sets the RTC alarm.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] year year (min 1970)
|
||||
* @param[in] mon month (1-12)
|
||||
* @param[in] day day of the month (1-31)
|
||||
* @param[in] hour hour (0-23)
|
||||
* @param[in] min minute (0-59)
|
||||
* @param[in] sec second (0-59)
|
||||
*
|
||||
* Note this alarm setting clears when the alarm is triggered.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters
|
||||
*/
|
||||
sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
|
||||
uint8_t day, uint8_t hour, uint8_t min,
|
||||
uint8_t sec);
|
||||
|
||||
/*!
|
||||
* This function sets the RTC alarm (periodic mode).
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] sec period in seconds
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters
|
||||
*/
|
||||
sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec);
|
||||
|
||||
/*!
|
||||
* This function cancels the RTC alarm.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
*
|
||||
* Note this alarm setting clears when the alarm is triggered.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters
|
||||
*/
|
||||
sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc);
|
||||
|
||||
/*!
|
||||
* This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM
|
||||
* resource can set the calibration.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] count calbration count (-16 to 15)
|
||||
*
|
||||
* The calibration value is a 5-bit value including the sign bit, which is
|
||||
* implemented in 2's complement. It is added or subtracted from the RTC on
|
||||
* a perdiodic basis, once per 32768 cycles of the RTC clock.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*/
|
||||
sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name System Counter (SYSCTR) Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* This function sets the SYSCTR alarm.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] ticks number of 8MHz cycles
|
||||
*
|
||||
* Note this alarm setting clears when the alarm is triggered.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters
|
||||
*/
|
||||
sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks);
|
||||
|
||||
/*!
|
||||
* This function sets the SYSCTR alarm (periodic mode).
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] ticks number of 8MHz cycles
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters
|
||||
*/
|
||||
sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks);
|
||||
|
||||
/*!
|
||||
* This function cancels the SYSCTR alarm.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
*
|
||||
* Note this alarm setting clears when the alarm is triggered.
|
||||
*
|
||||
* @return Returns an error code (SC_ERR_NONE = success).
|
||||
*
|
||||
* Return errors:
|
||||
* - SC_ERR_PARM if invalid time/date parameters
|
||||
*/
|
||||
sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc);
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* SC_TIMER_API_H */
|
||||
|
||||
/**@}*/
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <console_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include "imx8_lpuart.h"
|
||||
|
||||
.globl console_lpuart_register
|
||||
.globl console_lpuart_init
|
||||
.globl console_lpuart_putc
|
||||
.globl console_lpuart_getc
|
||||
.globl console_lpuart_flush
|
||||
|
||||
func console_lpuart_register
|
||||
mov x7, x30
|
||||
mov x6, x3
|
||||
cbz x6, register_fail
|
||||
str x0, [x6, #CONSOLE_T_BASE]
|
||||
|
||||
bl console_lpuart_init
|
||||
cbz x0, register_fail
|
||||
|
||||
mov x0, x6
|
||||
mov x30, x7
|
||||
finish_console_register lpuart putc=1, getc=1, flush=1
|
||||
|
||||
register_fail:
|
||||
ret x7
|
||||
endfunc console_lpuart_register
|
||||
|
||||
func console_lpuart_init
|
||||
mov w0, #1
|
||||
ret
|
||||
endfunc console_lpuart_init
|
||||
|
||||
func console_lpuart_putc
|
||||
ldr x1, [x1, #CONSOLE_T_BASE]
|
||||
cbz x1, putc_error
|
||||
/* Prepare '\r' to '\n' */
|
||||
cmp w0, #0xA
|
||||
b.ne 2f
|
||||
1:
|
||||
/* Check if the transmit FIFO is full */
|
||||
ldr w2, [x1, #STAT]
|
||||
tbz w2, #23, 1b
|
||||
mov w2, #0xD
|
||||
str w2, [x1, #DATA]
|
||||
2:
|
||||
/* Check if the transmit FIFO is full */
|
||||
ldr w2, [x1, #STAT]
|
||||
tbz w2, #23, 2b
|
||||
str w0, [x1, #DATA]
|
||||
ret
|
||||
putc_error:
|
||||
mov w0, #-1
|
||||
ret
|
||||
endfunc console_lpuart_putc
|
||||
|
||||
func console_lpuart_getc
|
||||
ldr x0, [x0, #CONSOLE_T_BASE]
|
||||
cbz x0, getc_error
|
||||
/* Check if the receive FIFO state */
|
||||
ret
|
||||
getc_error:
|
||||
mov w0, #-1
|
||||
ret
|
||||
endfunc console_lpuart_getc
|
||||
|
||||
func console_lpuart_flush
|
||||
ret
|
||||
endfunc console_lpuart_flush
|
||||
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/interrupt_props.h>
|
||||
#include <drivers/arm/gicv3.h>
|
||||
#include <drivers/arm/arm_gicv3_common.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/utils.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <plat_imx8.h>
|
||||
|
||||
/* the GICv3 driver only needs to be initialized in EL3 */
|
||||
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
||||
|
||||
static const interrupt_prop_t g01s_interrupt_props[] = {
|
||||
INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY,
|
||||
INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
#if SDEI_SUPPORT
|
||||
INTR_PROP_DESC(PLAT_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI,
|
||||
INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
#endif
|
||||
};
|
||||
|
||||
static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
|
||||
{
|
||||
return (unsigned int)plat_core_pos_by_mpidr(mpidr);
|
||||
}
|
||||
|
||||
const gicv3_driver_data_t arm_gic_data = {
|
||||
.gicd_base = PLAT_GICD_BASE,
|
||||
.gicr_base = PLAT_GICR_BASE,
|
||||
.interrupt_props = g01s_interrupt_props,
|
||||
.interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
|
||||
.rdistif_num = PLATFORM_CORE_COUNT,
|
||||
.rdistif_base_addrs = rdistif_base_addrs,
|
||||
.mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
|
||||
};
|
||||
|
||||
void plat_gic_driver_init(void)
|
||||
{
|
||||
/*
|
||||
* the GICv3 driver is initialized in EL3 and does not need
|
||||
* to be initialized again in S-EL1. This is because the S-EL1
|
||||
* can use GIC system registers to manage interrupts and does
|
||||
* not need GIC interface base addresses to be configured.
|
||||
*/
|
||||
#if IMAGE_BL31
|
||||
gicv3_driver_init(&arm_gic_data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline void plat_gicr_exit_sleep(void)
|
||||
{
|
||||
unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER);
|
||||
|
||||
/*
|
||||
* ProcessorSleep bit can ONLY be set to zero when
|
||||
* Quiescent bit and Sleep bit are both zero, so
|
||||
* need to make sure Quiescent bit and Sleep bit
|
||||
* are zero before clearing ProcessorSleep bit.
|
||||
*/
|
||||
if (val & WAKER_QSC_BIT) {
|
||||
mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT);
|
||||
/* Wait till the WAKER_QSC_BIT changes to 0 */
|
||||
while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void plat_gic_init(void)
|
||||
{
|
||||
plat_gicr_exit_sleep();
|
||||
gicv3_distif_init();
|
||||
gicv3_rdistif_init(plat_my_core_pos());
|
||||
gicv3_cpuif_enable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void plat_gic_cpuif_enable(void)
|
||||
{
|
||||
gicv3_cpuif_enable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void plat_gic_cpuif_disable(void)
|
||||
{
|
||||
gicv3_cpuif_disable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void plat_gic_pcpu_init(void)
|
||||
{
|
||||
gicv3_rdistif_init(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx)
|
||||
{
|
||||
/* save the gic rdist/dist context */
|
||||
for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
|
||||
gicv3_rdistif_save(i, &ctx->rdist_ctx[i]);
|
||||
gicv3_distif_save(&ctx->dist_ctx);
|
||||
}
|
||||
|
||||
void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx)
|
||||
{
|
||||
/* restore the gic rdist/dist context */
|
||||
gicv3_distif_init_restore(&ctx->dist_ctx);
|
||||
for (int i = 0; i < PLATFORM_CORE_COUNT; i++)
|
||||
gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]);
|
||||
}
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include "imx8_mu.h"
|
||||
|
||||
void MU_Resume(uint32_t base)
|
||||
{
|
||||
uint32_t reg, i;
|
||||
|
||||
reg = mmio_read_32(base + MU_ACR_OFFSET1);
|
||||
/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
|
||||
reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
|
||||
| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
|
||||
mmio_write_32(base + MU_ACR_OFFSET1, reg);
|
||||
|
||||
/* Enable all RX interrupts */
|
||||
for (i = 0; i < MU_RR_COUNT; i++)
|
||||
MU_EnableRxFullInt(base, i);
|
||||
}
|
||||
|
||||
void MU_EnableRxFullInt(uint32_t base, uint32_t index)
|
||||
{
|
||||
uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
|
||||
|
||||
reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
|
||||
reg |= MU_CR_RIE0_MASK1 >> index;
|
||||
mmio_write_32(base + MU_ACR_OFFSET1, reg);
|
||||
}
|
||||
|
||||
void MU_EnableGeneralInt(uint32_t base, uint32_t index)
|
||||
{
|
||||
uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
|
||||
|
||||
reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
|
||||
reg |= MU_CR_GIE0_MASK1 >> index;
|
||||
mmio_write_32(base + MU_ACR_OFFSET1, reg);
|
||||
}
|
||||
|
||||
void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg)
|
||||
{
|
||||
uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
|
||||
|
||||
/* Wait TX register to be empty. */
|
||||
while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
|
||||
;
|
||||
mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg);
|
||||
}
|
||||
|
||||
void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg)
|
||||
{
|
||||
uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
|
||||
|
||||
/* Wait RX register to be full. */
|
||||
while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
|
||||
;
|
||||
*msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4));
|
||||
}
|
||||
|
||||
void MU_Init(uint32_t base)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = mmio_read_32(base + MU_ACR_OFFSET1);
|
||||
/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
|
||||
reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
|
||||
| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
|
||||
mmio_write_32(base + MU_ACR_OFFSET1, reg);
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define MU_ATR0_OFFSET1 0x0
|
||||
#define MU_ARR0_OFFSET1 0x10
|
||||
#define MU_ASR_OFFSET1 0x20
|
||||
#define MU_ACR_OFFSET1 0x24
|
||||
#define MU_TR_COUNT1 4
|
||||
#define MU_RR_COUNT1 4
|
||||
|
||||
#define MU_CR_GIEn_MASK1 (0xFu << 28)
|
||||
#define MU_CR_RIEn_MASK1 (0xF << 24)
|
||||
#define MU_CR_TIEn_MASK1 (0xF << 20)
|
||||
#define MU_CR_GIRn_MASK1 (0xF << 16)
|
||||
#define MU_CR_NMI_MASK1 (1 << 3)
|
||||
#define MU_CR_Fn_MASK1 0x7
|
||||
|
||||
#define MU_SR_TE0_MASK1 (1 << 23)
|
||||
#define MU_SR_RF0_MASK1 (1 << 27)
|
||||
#define MU_CR_RIE0_MASK1 (1 << 27)
|
||||
#define MU_CR_GIE0_MASK1 (1U << 31)
|
||||
|
||||
#define MU_TR_COUNT 4
|
||||
#define MU_RR_COUNT 4
|
||||
|
||||
void MU_Init(uint32_t base);
|
||||
void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg);
|
||||
void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg);
|
||||
void MU_EnableGeneralInt(uint32_t base, uint32_t index);
|
||||
void MU_EnableRxFullInt(uint32_t base, uint32_t index);
|
||||
void MU_Resume(uint32_t base);
|
||||
@@ -0,0 +1,120 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <lib/bakery_lock.h>
|
||||
|
||||
#include <sci/sci_scfw.h>
|
||||
#include <sci/sci_ipc.h>
|
||||
#include <sci/sci_rpc.h>
|
||||
#include "imx8_mu.h"
|
||||
|
||||
sc_ipc_t ipc_handle;
|
||||
|
||||
DEFINE_BAKERY_LOCK(sc_ipc_bakery_lock);
|
||||
#define sc_ipc_lock_init() bakery_lock_init(&sc_ipc_bakery_lock)
|
||||
#define sc_ipc_lock() bakery_lock_get(&sc_ipc_bakery_lock)
|
||||
#define sc_ipc_unlock() bakery_lock_release(&sc_ipc_bakery_lock)
|
||||
|
||||
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
|
||||
{
|
||||
sc_ipc_lock();
|
||||
|
||||
sc_ipc_write(ipc, msg);
|
||||
if (!no_resp)
|
||||
sc_ipc_read(ipc, msg);
|
||||
|
||||
sc_ipc_unlock();
|
||||
}
|
||||
|
||||
sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id)
|
||||
{
|
||||
uint32_t base = id;
|
||||
uint32_t i;
|
||||
|
||||
/* Get MU base associated with IPC channel */
|
||||
if ((ipc == NULL) || (base == 0))
|
||||
return SC_ERR_IPC;
|
||||
|
||||
sc_ipc_lock_init();
|
||||
|
||||
/* Init MU */
|
||||
MU_Init(base);
|
||||
|
||||
/* Enable all RX interrupts */
|
||||
for (i = 0; i < MU_RR_COUNT; i++) {
|
||||
MU_EnableRxFullInt(base, i);
|
||||
}
|
||||
|
||||
/* Return MU address as handle */
|
||||
*ipc = (sc_ipc_t) id;
|
||||
|
||||
return SC_ERR_NONE;
|
||||
}
|
||||
|
||||
void sc_ipc_close(sc_ipc_t ipc)
|
||||
{
|
||||
uint32_t base = ipc;
|
||||
|
||||
if (base != 0)
|
||||
MU_Init(base);
|
||||
}
|
||||
|
||||
void sc_ipc_read(sc_ipc_t ipc, void *data)
|
||||
{
|
||||
uint32_t base = ipc;
|
||||
sc_rpc_msg_t *msg = (sc_rpc_msg_t *) data;
|
||||
uint8_t count = 0;
|
||||
|
||||
/* Check parms */
|
||||
if ((base == 0) || (msg == NULL))
|
||||
return;
|
||||
|
||||
/* Read first word */
|
||||
MU_ReceiveMsg(base, 0, (uint32_t *) msg);
|
||||
count++;
|
||||
|
||||
/* Check size */
|
||||
if (msg->size > SC_RPC_MAX_MSG) {
|
||||
*((uint32_t *) msg) = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Read remaining words */
|
||||
while (count < msg->size) {
|
||||
MU_ReceiveMsg(base, count % MU_RR_COUNT,
|
||||
&(msg->DATA.u32[count - 1]));
|
||||
count++;
|
||||
}
|
||||
}
|
||||
|
||||
void sc_ipc_write(sc_ipc_t ipc, void *data)
|
||||
{
|
||||
sc_rpc_msg_t *msg = (sc_rpc_msg_t *) data;
|
||||
uint32_t base = ipc;
|
||||
uint8_t count = 0;
|
||||
|
||||
/* Check parms */
|
||||
if ((base == 0) || (msg == NULL))
|
||||
return;
|
||||
|
||||
/* Check size */
|
||||
if (msg->size > SC_RPC_MAX_MSG)
|
||||
return;
|
||||
|
||||
/* Write first word */
|
||||
MU_SendMessage(base, 0, *((uint32_t *) msg));
|
||||
count++;
|
||||
|
||||
/* Write remaining words */
|
||||
while (count < msg->size) {
|
||||
MU_SendMessage(base, count % MU_TR_COUNT,
|
||||
msg->DATA.u32[count - 1]);
|
||||
count++;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
#
|
||||
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
BL31_SOURCES += plat/imx/common/sci/ipc.c \
|
||||
plat/imx/common/sci/imx8_mu.c \
|
||||
plat/imx/common/sci/svc/pad/pad_rpc_clnt.c \
|
||||
plat/imx/common/sci/svc/pm/pm_rpc_clnt.c \
|
||||
plat/imx/common/sci/svc/rm/rm_rpc_clnt.c \
|
||||
plat/imx/common/sci/svc/timer/timer_rpc_clnt.c \
|
||||
plat/imx/common/sci/svc/misc/misc_rpc_clnt.c
|
||||
+506
@@ -0,0 +1,506 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* File containing client-side RPC functions for the MISC service. These
|
||||
* functions are ported to clients that communicate to the SC.
|
||||
*
|
||||
* @addtogroup MISC_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/svc/misc/sci_misc_api.h>
|
||||
#include <sci/sci_rpc.h>
|
||||
#include <stdlib.h>
|
||||
#include "sci_misc_rpc.h"
|
||||
|
||||
/* Local Defines */
|
||||
|
||||
/* Local Types */
|
||||
|
||||
/* Local Functions */
|
||||
|
||||
sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_ctrl_t ctrl, uint32_t val)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_CONTROL;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)ctrl;
|
||||
RPC_U32(&msg, 4U) = (uint32_t)val;
|
||||
RPC_U16(&msg, 8U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 4U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_ctrl_t ctrl, uint32_t *val)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_CONTROL;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)ctrl;
|
||||
RPC_U16(&msg, 4U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (val != NULL)
|
||||
*val = RPC_U32(&msg, 0U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_misc_dma_group_t max)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_MAX_DMA_GROUP;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)max;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_misc_dma_group_t group)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_DMA_GROUP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)group;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
|
||||
sc_faddr_t addr_dst, uint32_t len,
|
||||
sc_bool_t fw)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_IMAGE_LOAD;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr_src >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr_src;
|
||||
RPC_U32(&msg, 8U) = (uint32_t)(addr_dst >> 32U);
|
||||
RPC_U32(&msg, 12U) = (uint32_t)addr_dst;
|
||||
RPC_U32(&msg, 16U) = (uint32_t)len;
|
||||
RPC_U8(&msg, 20U) = (uint8_t)fw;
|
||||
RPC_SIZE(&msg) = 7U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
|
||||
sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_AUTHENTICATE;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr;
|
||||
RPC_U8(&msg, 8U) = (uint8_t)cmd;
|
||||
RPC_SIZE(&msg) = 4U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_FUSE_WRITE;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_ENABLE_DEBUG;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_FORWARD_LIFECYCLE;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)lifecycle;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_RETURN_LIFECYCLE;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_BUILD_INFO;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (version != NULL)
|
||||
*version = RPC_U32(&msg, 0U);
|
||||
|
||||
if (commit != NULL)
|
||||
*commit = RPC_U32(&msg, 4U);
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
|
||||
uint16_t *monotonic, uint32_t *uid_l,
|
||||
uint32_t *uid_h)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_CHIP_INFO;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (uid_l != NULL)
|
||||
*uid_l = RPC_U32(&msg, 0U);
|
||||
|
||||
if (uid_h != NULL)
|
||||
*uid_h = RPC_U32(&msg, 4U);
|
||||
|
||||
if (lc != NULL)
|
||||
*lc = RPC_U16(&msg, 8U);
|
||||
|
||||
if (monotonic != NULL)
|
||||
*monotonic = RPC_U16(&msg, 10U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_DEBUG_OUT;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)ch;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_WAVEFORM_CAPTURE;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)enable;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BUILD_INFO;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (build != NULL)
|
||||
*build = RPC_U32(&msg, 0U);
|
||||
|
||||
if (commit != NULL)
|
||||
*commit = RPC_U32(&msg, 4U);
|
||||
}
|
||||
|
||||
void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_UNIQUE_ID;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (id_l != NULL)
|
||||
*id_l = RPC_U32(&msg, 0U);
|
||||
|
||||
if (id_h != NULL)
|
||||
*id_h = RPC_U32(&msg, 4U);
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_ARI;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U16(&msg, 2U) = (uint16_t)resource_mst;
|
||||
RPC_U16(&msg, 4U) = (uint16_t)ari;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)enable;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BOOT_STATUS;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)status;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_TRUE);
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BOOT_DONE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)cpu;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_OTP_FUSE_READ;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)word;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (val != NULL)
|
||||
*val = RPC_U32(&msg, 0U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_OTP_FUSE_WRITE;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)word;
|
||||
RPC_U32(&msg, 4U) = (uint32_t)val;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_misc_temp_t temp, int16_t celsius, int8_t tenths)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_TEMP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_I16(&msg, 2U) = (int16_t) celsius;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)temp;
|
||||
RPC_I8(&msg, 5U) = (int8_t) tenths;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_misc_temp_t temp, int16_t *celsius,
|
||||
int8_t *tenths)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_TEMP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)temp;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (celsius != NULL)
|
||||
*celsius = RPC_I16(&msg, 0U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (tenths != NULL)
|
||||
*tenths = RPC_I8(&msg, 2U);
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_BOOT_DEV;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (dev != NULL)
|
||||
*dev = RPC_U16(&msg, 0U);
|
||||
}
|
||||
|
||||
void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
|
||||
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_BUTTON_STATUS;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (status != NULL)
|
||||
*status = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
+76
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the MISC RPC implementation.
|
||||
*
|
||||
* @addtogroup MISC_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SC_MISC_RPC_H
|
||||
#define SC_MISC_RPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for RPC MISC function calls
|
||||
*/
|
||||
/*@{*/
|
||||
#define MISC_FUNC_UNKNOWN 0 /* Unknown function */
|
||||
#define MISC_FUNC_SET_CONTROL 1U /* Index for misc_set_control() RPC call */
|
||||
#define MISC_FUNC_GET_CONTROL 2U /* Index for misc_get_control() RPC call */
|
||||
#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /* Index for misc_set_max_dma_group() RPC call */
|
||||
#define MISC_FUNC_SET_DMA_GROUP 5U /* Index for misc_set_dma_group() RPC call */
|
||||
#define MISC_FUNC_SECO_IMAGE_LOAD 8U /* Index for misc_seco_image_load() RPC call */
|
||||
#define MISC_FUNC_SECO_AUTHENTICATE 9U /* Index for misc_seco_authenticate() RPC call */
|
||||
#define MISC_FUNC_SECO_FUSE_WRITE 20U /* Index for misc_seco_fuse_write() RPC call */
|
||||
#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /* Index for misc_seco_enable_debug() RPC call */
|
||||
#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /* Index for misc_seco_forward_lifecycle() RPC call */
|
||||
#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /* Index for misc_seco_return_lifecycle() RPC call */
|
||||
#define MISC_FUNC_SECO_BUILD_INFO 24U /* Index for misc_seco_build_info() RPC call */
|
||||
#define MISC_FUNC_SECO_CHIP_INFO 25U /* Index for misc_seco_chip_info() RPC call */
|
||||
#define MISC_FUNC_DEBUG_OUT 10U /* Index for misc_debug_out() RPC call */
|
||||
#define MISC_FUNC_WAVEFORM_CAPTURE 6U /* Index for misc_waveform_capture() RPC call */
|
||||
#define MISC_FUNC_BUILD_INFO 15U /* Index for misc_build_info() RPC call */
|
||||
#define MISC_FUNC_UNIQUE_ID 19U /* Index for misc_unique_id() RPC call */
|
||||
#define MISC_FUNC_SET_ARI 3U /* Index for misc_set_ari() RPC call */
|
||||
#define MISC_FUNC_BOOT_STATUS 7U /* Index for misc_boot_status() RPC call */
|
||||
#define MISC_FUNC_BOOT_DONE 14U /* Index for misc_boot_done() RPC call */
|
||||
#define MISC_FUNC_OTP_FUSE_READ 11U /* Index for misc_otp_fuse_read() RPC call */
|
||||
#define MISC_FUNC_OTP_FUSE_WRITE 17U /* Index for misc_otp_fuse_write() RPC call */
|
||||
#define MISC_FUNC_SET_TEMP 12U /* Index for misc_set_temp() RPC call */
|
||||
#define MISC_FUNC_GET_TEMP 13U /* Index for misc_get_temp() RPC call */
|
||||
#define MISC_FUNC_GET_BOOT_DEV 16U /* Index for misc_get_boot_dev() RPC call */
|
||||
#define MISC_FUNC_GET_BUTTON_STATUS 18U /* Index for misc_get_button_status() RPC call */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This function dispatches an incoming MISC RPC request.
|
||||
*
|
||||
* @param[in] caller_pt caller partition
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void misc_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
|
||||
|
||||
/*!
|
||||
* This function translates and dispatches an MISC RPC request.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void misc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
|
||||
|
||||
#endif /* SC_MISC_RPC_H */
|
||||
|
||||
/**@}*/
|
||||
+454
@@ -0,0 +1,454 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* File containing client-side RPC functions for the PAD service. These
|
||||
* functions are ported to clients that communicate to the SC.
|
||||
*
|
||||
* @addtogroup PAD_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/svc/pad/sci_pad_api.h>
|
||||
#include <sci/sci_rpc.h>
|
||||
#include "sci_pad_rpc.h"
|
||||
|
||||
/* Local Defines */
|
||||
|
||||
/* Local Types */
|
||||
|
||||
/* Local Functions */
|
||||
|
||||
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_MUX;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)mux;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)config;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)iso;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t *mux, sc_pad_config_t *config,
|
||||
sc_pad_iso_t *iso)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_MUX;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mux != NULL) {
|
||||
*mux = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
if (config != NULL) {
|
||||
*config = RPC_U8(&msg, 1U);
|
||||
}
|
||||
|
||||
if (iso != NULL) {
|
||||
*iso = RPC_U8(&msg, 2U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)ctrl;
|
||||
RPC_U16(&msg, 4U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (ctrl != NULL) {
|
||||
*ctrl = RPC_U32(&msg, 0U);
|
||||
}
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_WAKEUP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)wakeup;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_WAKEUP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (wakeup != NULL) {
|
||||
*wakeup = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
|
||||
sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
|
||||
sc_pad_wakeup_t wakeup)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_ALL;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)ctrl;
|
||||
RPC_U16(&msg, 4U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)mux;
|
||||
RPC_U8(&msg, 7U) = (uint8_t)config;
|
||||
RPC_U8(&msg, 8U) = (uint8_t)iso;
|
||||
RPC_U8(&msg, 9U) = (uint8_t)wakeup;
|
||||
RPC_SIZE(&msg) = 4U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
|
||||
sc_pad_config_t *config, sc_pad_iso_t *iso,
|
||||
uint32_t *ctrl, sc_pad_wakeup_t *wakeup)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_ALL;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (ctrl != NULL) {
|
||||
*ctrl = RPC_U32(&msg, 0U);
|
||||
}
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mux != NULL) {
|
||||
*mux = RPC_U8(&msg, 4U);
|
||||
}
|
||||
|
||||
if (config != NULL) {
|
||||
*config = RPC_U8(&msg, 5U);
|
||||
}
|
||||
|
||||
if (iso != NULL) {
|
||||
*iso = RPC_U8(&msg, 6U);
|
||||
}
|
||||
|
||||
if (wakeup != NULL) {
|
||||
*wakeup = RPC_U8(&msg, 7U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)val;
|
||||
RPC_U16(&msg, 4U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (val != NULL) {
|
||||
*val = RPC_U32(&msg, 0U);
|
||||
}
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)dse;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)ps;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t *dse,
|
||||
sc_pad_28fdsoi_ps_t *ps)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (dse != NULL) {
|
||||
*dse = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
if (ps != NULL) {
|
||||
*ps = RPC_U8(&msg, 1U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
|
||||
sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
|
||||
sc_bool_t pue)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_HSIC;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)dse;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)pus;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)hys;
|
||||
RPC_U8(&msg, 5U) = (uint8_t)pke;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)pue;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
|
||||
sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
|
||||
sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
|
||||
sc_bool_t *pue)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_HSIC;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (dse != NULL) {
|
||||
*dse = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
if (pus != NULL) {
|
||||
*pus = RPC_U8(&msg, 1U);
|
||||
}
|
||||
|
||||
if (hys != NULL) {
|
||||
*hys = RPC_U8(&msg, 2U);
|
||||
}
|
||||
|
||||
if (pke != NULL) {
|
||||
*pke = RPC_U8(&msg, 3U);
|
||||
}
|
||||
|
||||
if (pue != NULL) {
|
||||
*pue = RPC_U8(&msg, 4U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t compen, sc_bool_t fastfrz,
|
||||
uint8_t rasrcp, uint8_t rasrcn,
|
||||
sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_COMP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)compen;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)rasrcp;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)rasrcn;
|
||||
RPC_U8(&msg, 5U) = (uint8_t)fastfrz;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)nasrc_sel;
|
||||
RPC_U8(&msg, 7U) = (uint8_t)psw_ovr;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
|
||||
uint8_t *compen, sc_bool_t *fastfrz,
|
||||
uint8_t *rasrcp, uint8_t *rasrcn,
|
||||
sc_bool_t *nasrc_sel, sc_bool_t *compok,
|
||||
uint8_t *nasrc, sc_bool_t *psw_ovr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
|
||||
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_COMP;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (compen != NULL) {
|
||||
*compen = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
if (rasrcp != NULL) {
|
||||
*rasrcp = RPC_U8(&msg, 1U);
|
||||
}
|
||||
|
||||
if (rasrcn != NULL) {
|
||||
*rasrcn = RPC_U8(&msg, 2U);
|
||||
}
|
||||
|
||||
if (nasrc != NULL) {
|
||||
*nasrc = RPC_U8(&msg, 3U);
|
||||
}
|
||||
|
||||
if (fastfrz != NULL) {
|
||||
*fastfrz = RPC_U8(&msg, 4U);
|
||||
}
|
||||
|
||||
if (nasrc_sel != NULL) {
|
||||
*nasrc_sel = RPC_U8(&msg, 5U);
|
||||
}
|
||||
|
||||
if (compok != NULL) {
|
||||
*compok = RPC_U8(&msg, 6U);
|
||||
}
|
||||
|
||||
if (psw_ovr != NULL) {
|
||||
*psw_ovr = RPC_U8(&msg, 7U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the PAD RPC implementation.
|
||||
*
|
||||
* @addtogroup PAD_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SCI_PAD_RPC_H
|
||||
#define SCI_PAD_RPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for RPC PAD function calls
|
||||
*/
|
||||
/*@{*/
|
||||
#define PAD_FUNC_UNKNOWN 0 /* Unknown function */
|
||||
#define PAD_FUNC_SET_MUX 1U /* Index for pad_set_mux() RPC call */
|
||||
#define PAD_FUNC_GET_MUX 6U /* Index for pad_get_mux() RPC call */
|
||||
#define PAD_FUNC_SET_GP 2U /* Index for pad_set_gp() RPC call */
|
||||
#define PAD_FUNC_GET_GP 7U /* Index for pad_get_gp() RPC call */
|
||||
#define PAD_FUNC_SET_WAKEUP 4U /* Index for pad_set_wakeup() RPC call */
|
||||
#define PAD_FUNC_GET_WAKEUP 9U /* Index for pad_get_wakeup() RPC call */
|
||||
#define PAD_FUNC_SET_ALL 5U /* Index for pad_set_all() RPC call */
|
||||
#define PAD_FUNC_GET_ALL 10U /* Index for pad_get_all() RPC call */
|
||||
#define PAD_FUNC_SET 15U /* Index for pad_set() RPC call */
|
||||
#define PAD_FUNC_GET 16U /* Index for pad_get() RPC call */
|
||||
#define PAD_FUNC_SET_GP_28FDSOI 11U /* Index for pad_set_gp_28fdsoi() RPC call */
|
||||
#define PAD_FUNC_GET_GP_28FDSOI 12U /* Index for pad_get_gp_28fdsoi() RPC call */
|
||||
#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /* Index for pad_set_gp_28fdsoi_hsic() RPC call */
|
||||
#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /* Index for pad_get_gp_28fdsoi_hsic() RPC call */
|
||||
#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /* Index for pad_set_gp_28fdsoi_comp() RPC call */
|
||||
#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /* Index for pad_get_gp_28fdsoi_comp() RPC call */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This function dispatches an incoming PAD RPC request.
|
||||
*
|
||||
* @param[in] caller_pt caller partition
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
|
||||
|
||||
/*!
|
||||
* This function translates and dispatches an PAD RPC request.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
|
||||
|
||||
#endif /* SCI_PAD_RPC_H */
|
||||
|
||||
/**@}*/
|
||||
+459
@@ -0,0 +1,459 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* File containing client-side RPC functions for the PM service. These
|
||||
* functions are ported to clients that communicate to the SC.
|
||||
*
|
||||
* @addtogroup PM_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/svc/pm/sci_pm_api.h>
|
||||
#include <sci/sci_rpc.h>
|
||||
|
||||
#include "sci_pm_rpc.h"
|
||||
|
||||
/* Local Defines */
|
||||
|
||||
/* Local Types */
|
||||
|
||||
/* Local Functions */
|
||||
|
||||
sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_SYS_POWER_MODE;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)mode;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_pm_power_mode_t mode)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_PARTITION_POWER_MODE;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)mode;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_pm_power_mode_t *mode)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_SYS_POWER_MODE;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mode != NULL) {
|
||||
*mode = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_RESOURCE_POWER_MODE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)mode;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t *mode)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_RESOURCE_POWER_MODE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mode != NULL) {
|
||||
*mode = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_LOW_POWER_MODE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)mode;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_power_mode_t mode,
|
||||
sc_pm_wake_src_t wake_src)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_CPU_LOW_POWER_MODE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)mode;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)wake_src;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_faddr_t address)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME_ADDR;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)address;
|
||||
RPC_U16(&msg, 8U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 4U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_bool_t isPrimary, sc_faddr_t address)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)address;
|
||||
RPC_U16(&msg, 8U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 10U) = (uint8_t)isPrimary;
|
||||
RPC_SIZE(&msg) = 4U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_sys_if_t sys_if,
|
||||
sc_pm_power_mode_t hpm,
|
||||
sc_pm_power_mode_t lpm)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_SYS_IF_POWER_MODE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)sys_if;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)hpm;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)lpm;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_RATE;
|
||||
RPC_U32(&msg, 0U) = *(uint32_t *)rate;
|
||||
RPC_U16(&msg, 4U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)clk;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
*rate = RPC_U32(&msg, 0U);
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_RATE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)clk;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (rate != NULL) {
|
||||
*rate = RPC_U32(&msg, 0U);
|
||||
}
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CLOCK_ENABLE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)clk;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)enable;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)autog;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_PARENT;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)clk;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)parent;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_pm_clk_t clk, sc_pm_clk_parent_t *parent)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_PARENT;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)clk;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (parent != NULL) {
|
||||
*parent = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)type;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET_REASON;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (reason != NULL) {
|
||||
*reason = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
|
||||
sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_BOOT;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(boot_addr >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)boot_addr;
|
||||
RPC_U16(&msg, 8U) = (uint16_t)resource_cpu;
|
||||
RPC_U16(&msg, 10U) = (uint16_t)resource_mu;
|
||||
RPC_U16(&msg, 12U) = (uint16_t)resource_dev;
|
||||
RPC_U8(&msg, 14U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 5U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)type;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_TRUE);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_pm_reset_type_t type)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT_PARTITION;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)type;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
|
||||
sc_faddr_t address)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
|
||||
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CPU_START;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)address;
|
||||
RPC_U16(&msg, 8U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 10U) = (uint8_t)enable;
|
||||
RPC_SIZE(&msg) = 4U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the PM RPC implementation.
|
||||
*
|
||||
* @addtogroup PM_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SCI_PM_RPC_H
|
||||
#define SCI_PM_RPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for RPC PM function calls
|
||||
*/
|
||||
/*@{*/
|
||||
#define PM_FUNC_UNKNOWN 0 /* Unknown function */
|
||||
#define PM_FUNC_SET_SYS_POWER_MODE 19U /* Index for pm_set_sys_power_mode() RPC call */
|
||||
#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /* Index for pm_set_partition_power_mode() RPC call */
|
||||
#define PM_FUNC_GET_SYS_POWER_MODE 2U /* Index for pm_get_sys_power_mode() RPC call */
|
||||
#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /* Index for pm_set_resource_power_mode() RPC call */
|
||||
#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /* Index for pm_get_resource_power_mode() RPC call */
|
||||
#define PM_FUNC_REQ_LOW_POWER_MODE 16U /* Index for pm_req_low_power_mode() RPC call */
|
||||
#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /* Index for pm_req_cpu_low_power_mode() RPC call */
|
||||
#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /* Index for pm_set_cpu_resume_addr() RPC call */
|
||||
#define PM_FUNC_SET_CPU_RESUME 21U /* Index for pm_set_cpu_resume() RPC call */
|
||||
#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /* Index for pm_req_sys_if_power_mode() RPC call */
|
||||
#define PM_FUNC_SET_CLOCK_RATE 5U /* Index for pm_set_clock_rate() RPC call */
|
||||
#define PM_FUNC_GET_CLOCK_RATE 6U /* Index for pm_get_clock_rate() RPC call */
|
||||
#define PM_FUNC_CLOCK_ENABLE 7U /* Index for pm_clock_enable() RPC call */
|
||||
#define PM_FUNC_SET_CLOCK_PARENT 14U /* Index for pm_set_clock_parent() RPC call */
|
||||
#define PM_FUNC_GET_CLOCK_PARENT 15U /* Index for pm_get_clock_parent() RPC call */
|
||||
#define PM_FUNC_RESET 13U /* Index for pm_reset() RPC call */
|
||||
#define PM_FUNC_RESET_REASON 10U /* Index for pm_reset_reason() RPC call */
|
||||
#define PM_FUNC_BOOT 8U /* Index for pm_boot() RPC call */
|
||||
#define PM_FUNC_REBOOT 9U /* Index for pm_reboot() RPC call */
|
||||
#define PM_FUNC_REBOOT_PARTITION 12U /* Index for pm_reboot_partition() RPC call */
|
||||
#define PM_FUNC_CPU_START 11U /* Index for pm_cpu_start() RPC call */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This function dispatches an incoming PM RPC request.
|
||||
*
|
||||
* @param[in] caller_pt caller partition
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
|
||||
|
||||
/*!
|
||||
* This function translates and dispatches an PM RPC request.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
|
||||
|
||||
#endif /* SCI_PM_RPC_H */
|
||||
|
||||
/**@}*/
|
||||
+639
@@ -0,0 +1,639 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* File containing client-side RPC functions for the RM service. These
|
||||
* functions are ported to clients that communicate to the SC.
|
||||
*
|
||||
* @addtogroup RM_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/sci_rpc.h>
|
||||
|
||||
#include "sci_rm_rpc.h"
|
||||
|
||||
/* Local Defines */
|
||||
|
||||
/* Local Types */
|
||||
|
||||
/* Local Functions */
|
||||
|
||||
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
|
||||
sc_bool_t isolated, sc_bool_t restricted,
|
||||
sc_bool_t grant, sc_bool_t coherent)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_ALLOC;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)secure;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)isolated;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)restricted;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)grant;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)coherent;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (pt != NULL) {
|
||||
*pt = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_CONFIDENTIAL;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)retro;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_FREE;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_DID;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_rm_did_t) result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_STATIC;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)did;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_LOCK;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_PARTITION;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (pt != NULL) {
|
||||
*pt = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PARENT;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)pt_parent;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
|
||||
sc_bool_t move_rsrc, sc_bool_t move_pads)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MOVE_ALL;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt_src;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)pt_dst;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)move_rsrc;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)move_pads;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_RESOURCE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
|
||||
sc_rsrc_t resource_lst, sc_bool_t movable)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_RESOURCE_MOVABLE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource_fst;
|
||||
RPC_U16(&msg, 2U) = (uint16_t)resource_lst;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)movable;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_bool_t movable)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)movable;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_spa_t sa, sc_rm_spa_t pa,
|
||||
sc_bool_t smmu_bypass)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_ATTRIBUTES;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)sa;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)pa;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)smmu_bypass;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_SID;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U16(&msg, 2U) = (uint16_t)sid;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_pt_t pt, sc_rm_perm_t perm)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)perm;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_OWNED;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_bool_t)result;
|
||||
}
|
||||
|
||||
sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_MASTER;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_bool_t)result;
|
||||
}
|
||||
|
||||
sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_PERIPHERAL;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_bool_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
|
||||
sc_rm_sid_t *sid)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_RESOURCE_INFO;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)resource;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (sid != NULL) {
|
||||
*sid = RPC_U16(&msg, 0U);
|
||||
}
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
|
||||
sc_faddr_t addr_start, sc_faddr_t addr_end)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_ALLOC;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr_start;
|
||||
RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
|
||||
RPC_U32(&msg, 12U) = (uint32_t)addr_end;
|
||||
RPC_SIZE(&msg) = 5U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mr != NULL) {
|
||||
*mr = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
|
||||
sc_faddr_t addr_end)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_SPLIT;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr_start;
|
||||
RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
|
||||
RPC_U32(&msg, 12U) = (uint32_t)addr_end;
|
||||
RPC_U8(&msg, 16U) = (uint8_t)mr;
|
||||
RPC_SIZE(&msg) = 6U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mr_ret != NULL) {
|
||||
*mr_ret = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_FREE;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)mr;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
|
||||
sc_faddr_t addr_start, sc_faddr_t addr_end)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_FIND_MEMREG;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)addr_start;
|
||||
RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
|
||||
RPC_U32(&msg, 12U) = (uint32_t)addr_end;
|
||||
RPC_SIZE(&msg) = 5U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mr != NULL) {
|
||||
*mr = RPC_U8(&msg, 0U);
|
||||
}
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_MEMREG;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)mr;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_rm_pt_t pt, sc_rm_perm_t perm)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MEMREG_PERMISSIONS;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)mr;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)perm;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_MEMREG_OWNED;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)mr;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_bool_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
|
||||
sc_faddr_t *addr_start, sc_faddr_t *addr_end)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_MEMREG_INFO;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)mr;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (addr_start != NULL) {
|
||||
*addr_start =
|
||||
((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
|
||||
}
|
||||
|
||||
if (addr_end != NULL) {
|
||||
*addr_end =
|
||||
((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
|
||||
}
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_PAD;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
|
||||
sc_pad_t pad_lst, sc_bool_t movable)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PAD_MOVABLE;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)pad_fst;
|
||||
RPC_U16(&msg, 2U) = (uint16_t)pad_lst;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)movable;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_PAD_OWNED;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pad;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_bool_t)result;
|
||||
}
|
||||
|
||||
void sc_rm_dump(sc_ipc_t ipc)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
|
||||
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_DUMP;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the RM RPC implementation.
|
||||
*
|
||||
* @addtogroup RM_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SCI_RM_RPC_H
|
||||
#define SCI_RM_RPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for RPC RM function calls
|
||||
*/
|
||||
/*@{*/
|
||||
#define RM_FUNC_UNKNOWN 0 /* Unknown function */
|
||||
#define RM_FUNC_PARTITION_ALLOC 1U /* Index for rm_partition_alloc() RPC call */
|
||||
#define RM_FUNC_SET_CONFIDENTIAL 31U /* Index for rm_set_confidential() RPC call */
|
||||
#define RM_FUNC_PARTITION_FREE 2U /* Index for rm_partition_free() RPC call */
|
||||
#define RM_FUNC_GET_DID 26U /* Index for rm_get_did() RPC call */
|
||||
#define RM_FUNC_PARTITION_STATIC 3U /* Index for rm_partition_static() RPC call */
|
||||
#define RM_FUNC_PARTITION_LOCK 4U /* Index for rm_partition_lock() RPC call */
|
||||
#define RM_FUNC_GET_PARTITION 5U /* Index for rm_get_partition() RPC call */
|
||||
#define RM_FUNC_SET_PARENT 6U /* Index for rm_set_parent() RPC call */
|
||||
#define RM_FUNC_MOVE_ALL 7U /* Index for rm_move_all() RPC call */
|
||||
#define RM_FUNC_ASSIGN_RESOURCE 8U /* Index for rm_assign_resource() RPC call */
|
||||
#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /* Index for rm_set_resource_movable() RPC call */
|
||||
#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /* Index for rm_set_subsys_rsrc_movable() RPC call */
|
||||
#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /* Index for rm_set_master_attributes() RPC call */
|
||||
#define RM_FUNC_SET_MASTER_SID 11U /* Index for rm_set_master_sid() RPC call */
|
||||
#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /* Index for rm_set_peripheral_permissions() RPC call */
|
||||
#define RM_FUNC_IS_RESOURCE_OWNED 13U /* Index for rm_is_resource_owned() RPC call */
|
||||
#define RM_FUNC_IS_RESOURCE_MASTER 14U /* Index for rm_is_resource_master() RPC call */
|
||||
#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /* Index for rm_is_resource_peripheral() RPC call */
|
||||
#define RM_FUNC_GET_RESOURCE_INFO 16U /* Index for rm_get_resource_info() RPC call */
|
||||
#define RM_FUNC_MEMREG_ALLOC 17U /* Index for rm_memreg_alloc() RPC call */
|
||||
#define RM_FUNC_MEMREG_SPLIT 29U /* Index for rm_memreg_split() RPC call */
|
||||
#define RM_FUNC_MEMREG_FREE 18U /* Index for rm_memreg_free() RPC call */
|
||||
#define RM_FUNC_FIND_MEMREG 30U /* Index for rm_find_memreg() RPC call */
|
||||
#define RM_FUNC_ASSIGN_MEMREG 19U /* Index for rm_assign_memreg() RPC call */
|
||||
#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /* Index for rm_set_memreg_permissions() RPC call */
|
||||
#define RM_FUNC_IS_MEMREG_OWNED 21U /* Index for rm_is_memreg_owned() RPC call */
|
||||
#define RM_FUNC_GET_MEMREG_INFO 22U /* Index for rm_get_memreg_info() RPC call */
|
||||
#define RM_FUNC_ASSIGN_PAD 23U /* Index for rm_assign_pad() RPC call */
|
||||
#define RM_FUNC_SET_PAD_MOVABLE 24U /* Index for rm_set_pad_movable() RPC call */
|
||||
#define RM_FUNC_IS_PAD_OWNED 25U /* Index for rm_is_pad_owned() RPC call */
|
||||
#define RM_FUNC_DUMP 27U /* Index for rm_dump() RPC call */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This function dispatches an incoming RM RPC request.
|
||||
*
|
||||
* @param[in] caller_pt caller partition
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
|
||||
|
||||
/*!
|
||||
* This function translates and dispatches an RM RPC request.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
|
||||
|
||||
#endif /* SCI_RM_RPC_H */
|
||||
|
||||
/**@}*/
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* Header file for the TIMER RPC implementation.
|
||||
*
|
||||
* @addtogroup TIMER_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SC_TIMER_RPC_H
|
||||
#define SC_TIMER_RPC_H
|
||||
|
||||
/* Includes */
|
||||
|
||||
/* Defines */
|
||||
|
||||
/*!
|
||||
* @name Defines for RPC TIMER function calls
|
||||
*/
|
||||
/*@{*/
|
||||
#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
|
||||
#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for timer_set_wdog_timeout() RPC call */
|
||||
#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for timer_set_wdog_pre_timeout() RPC call */
|
||||
#define TIMER_FUNC_START_WDOG 2U /* Index for timer_start_wdog() RPC call */
|
||||
#define TIMER_FUNC_STOP_WDOG 3U /* Index for timer_stop_wdog() RPC call */
|
||||
#define TIMER_FUNC_PING_WDOG 4U /* Index for timer_ping_wdog() RPC call */
|
||||
#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for timer_get_wdog_status() RPC call */
|
||||
#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for timer_pt_get_wdog_status() RPC call */
|
||||
#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for timer_set_wdog_action() RPC call */
|
||||
#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for timer_set_rtc_time() RPC call */
|
||||
#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for timer_get_rtc_time() RPC call */
|
||||
#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for timer_get_rtc_sec1970() RPC call */
|
||||
#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for timer_set_rtc_alarm() RPC call */
|
||||
#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for timer_set_rtc_periodic_alarm() RPC call */
|
||||
#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for timer_cancel_rtc_alarm() RPC call */
|
||||
#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for timer_set_rtc_calb() RPC call */
|
||||
#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for timer_set_sysctr_alarm() RPC call */
|
||||
#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for timer_set_sysctr_periodic_alarm() RPC call */
|
||||
#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for timer_cancel_sysctr_alarm() RPC call */
|
||||
/*@}*/
|
||||
|
||||
/* Types */
|
||||
|
||||
/* Functions */
|
||||
|
||||
/*!
|
||||
* This function dispatches an incoming TIMER RPC request.
|
||||
*
|
||||
* @param[in] caller_pt caller partition
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
|
||||
|
||||
/*!
|
||||
* This function translates and dispatches an TIMER RPC request.
|
||||
*
|
||||
* @param[in] ipc IPC handle
|
||||
* @param[in] msg pointer to RPC message
|
||||
*/
|
||||
void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
|
||||
|
||||
#endif /* SC_TIMER_RPC_H */
|
||||
|
||||
/**@}*/
|
||||
+396
@@ -0,0 +1,396 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*!
|
||||
* File containing client-side RPC functions for the TIMER service. These
|
||||
* functions are ported to clients that communicate to the SC.
|
||||
*
|
||||
* @addtogroup TIMER_SVC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
|
||||
#include <sci/sci_types.h>
|
||||
#include <sci/svc/rm/sci_rm_api.h>
|
||||
#include <sci/svc/timer/sci_timer_api.h>
|
||||
#include <sci/sci_rpc.h>
|
||||
#include <stdlib.h>
|
||||
#include "sci_timer_rpc.h"
|
||||
|
||||
/* Local Defines */
|
||||
|
||||
/* Local Types */
|
||||
|
||||
/* Local Functions */
|
||||
|
||||
sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_TIMEOUT;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)timeout;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
|
||||
sc_timer_wdog_time_t pre_timeout)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)pre_timeout;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_START_WDOG;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)lock;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_STOP_WDOG;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PING_WDOG;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
|
||||
sc_timer_wdog_time_t *timeout,
|
||||
sc_timer_wdog_time_t *max_timeout,
|
||||
sc_timer_wdog_time_t *remaining_time)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_WDOG_STATUS;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (timeout != NULL)
|
||||
*timeout = RPC_U32(&msg, 0U);
|
||||
|
||||
if (max_timeout != NULL)
|
||||
*max_timeout = RPC_U32(&msg, 4U);
|
||||
|
||||
if (remaining_time != NULL)
|
||||
*remaining_time = RPC_U32(&msg, 8U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
|
||||
sc_bool_t *enb,
|
||||
sc_timer_wdog_time_t *timeout,
|
||||
sc_timer_wdog_time_t *remaining_time)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PT_GET_WDOG_STATUS;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (timeout != NULL)
|
||||
*timeout = RPC_U32(&msg, 0U);
|
||||
|
||||
if (remaining_time != NULL)
|
||||
*remaining_time = RPC_U32(&msg, 4U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (enb != NULL)
|
||||
*enb = RPC_U8(&msg, 8U);
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
|
||||
sc_rm_pt_t pt, sc_timer_wdog_action_t action)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_ACTION;
|
||||
RPC_U8(&msg, 0U) = (uint8_t)pt;
|
||||
RPC_U8(&msg, 1U) = (uint8_t)action;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
|
||||
uint8_t day, uint8_t hour, uint8_t min,
|
||||
uint8_t sec)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_TIME;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)year;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)mon;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)day;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)hour;
|
||||
RPC_U8(&msg, 5U) = (uint8_t)min;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)sec;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
|
||||
uint8_t *day, uint8_t *hour, uint8_t *min,
|
||||
uint8_t *sec)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_TIME;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (year != NULL)
|
||||
*year = RPC_U16(&msg, 0U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
if (mon != NULL)
|
||||
*mon = RPC_U8(&msg, 2U);
|
||||
|
||||
if (day != NULL)
|
||||
*day = RPC_U8(&msg, 3U);
|
||||
|
||||
if (hour != NULL)
|
||||
*hour = RPC_U8(&msg, 4U);
|
||||
|
||||
if (min != NULL)
|
||||
*min = RPC_U8(&msg, 5U);
|
||||
|
||||
if (sec != NULL)
|
||||
*sec = RPC_U8(&msg, 6U);
|
||||
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_SEC1970;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
if (sec != NULL)
|
||||
*sec = RPC_U32(&msg, 0U);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
|
||||
uint8_t day, uint8_t hour, uint8_t min,
|
||||
uint8_t sec)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_ALARM;
|
||||
RPC_U16(&msg, 0U) = (uint16_t)year;
|
||||
RPC_U8(&msg, 2U) = (uint8_t)mon;
|
||||
RPC_U8(&msg, 3U) = (uint8_t)day;
|
||||
RPC_U8(&msg, 4U) = (uint8_t)hour;
|
||||
RPC_U8(&msg, 5U) = (uint8_t)min;
|
||||
RPC_U8(&msg, 6U) = (uint8_t)sec;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_PERIODIC_ALARM;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)sec;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_CANCEL_RTC_ALARM;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_CALB;
|
||||
RPC_I8(&msg, 0U) = (int8_t) count;
|
||||
RPC_SIZE(&msg) = 2U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_SYSCTR_ALARM;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(ticks >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)ticks;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM;
|
||||
RPC_U32(&msg, 0U) = (uint32_t)(ticks >> 32U);
|
||||
RPC_U32(&msg, 4U) = (uint32_t)ticks;
|
||||
RPC_SIZE(&msg) = 3U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc)
|
||||
{
|
||||
sc_rpc_msg_t msg;
|
||||
uint8_t result;
|
||||
|
||||
RPC_VER(&msg) = SC_RPC_VERSION;
|
||||
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
|
||||
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_CANCEL_SYSCTR_ALARM;
|
||||
RPC_SIZE(&msg) = 1U;
|
||||
|
||||
sc_call_rpc(ipc, &msg, SC_FALSE);
|
||||
|
||||
result = RPC_R8(&msg);
|
||||
return (sc_err_t)result;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
@@ -0,0 +1,112 @@
|
||||
#
|
||||
# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Architecture
|
||||
$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
|
||||
|
||||
TF_CFLAGS += -mfpu=neon
|
||||
ASFLAGS += -mfpu=neon
|
||||
|
||||
# Platform
|
||||
PLAT_INCLUDES := -Idrivers/imx/uart \
|
||||
-Iplat/imx/common/include \
|
||||
-Iplat/imx/imx7/include \
|
||||
-Idrivers/imx/timer \
|
||||
-Idrivers/imx/usdhc \
|
||||
-Iinclude/common/tbbr
|
||||
|
||||
# Translation tables library
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
BL2_SOURCES += common/desc_image_load.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/mmc/mmc.c \
|
||||
drivers/io/io_block.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/io/io_memmap.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/imx/timer/imx_gpt.c \
|
||||
drivers/imx/uart/imx_uart.c \
|
||||
drivers/imx/uart/imx_crash_uart.S \
|
||||
lib/aarch32/arm32_aeabi_divmod.c \
|
||||
lib/aarch32/arm32_aeabi_divmod_a32.S \
|
||||
lib/cpus/aarch32/cortex_a7.S \
|
||||
lib/optee/optee_utils.c \
|
||||
plat/imx/common/imx_aips.c \
|
||||
plat/imx/common/imx_caam.c \
|
||||
plat/imx/common/imx_clock.c \
|
||||
plat/imx/common/imx_csu.c \
|
||||
plat/imx/common/imx_io_mux.c \
|
||||
plat/imx/common/imx_snvs.c \
|
||||
plat/imx/common/imx_wdog.c \
|
||||
plat/imx/common/imx7_clock.c \
|
||||
plat/imx/imx7/common/imx7_bl2_mem_params_desc.c \
|
||||
plat/imx/imx7/common/imx7_bl2_el3_common.c \
|
||||
plat/imx/imx7/common/imx7_helpers.S \
|
||||
plat/imx/imx7/common/imx7_image_load.c \
|
||||
plat/imx/common/imx_io_storage.c \
|
||||
plat/imx/common/aarch32/imx_uart_console.S \
|
||||
${XLAT_TABLES_LIB_SRCS}
|
||||
|
||||
ifneq (${TRUSTED_BOARD_BOOT},0)
|
||||
|
||||
include drivers/auth/mbedtls/mbedtls_crypto.mk
|
||||
include drivers/auth/mbedtls/mbedtls_x509.mk
|
||||
|
||||
AUTH_SOURCES := drivers/auth/auth_mod.c \
|
||||
drivers/auth/crypto_mod.c \
|
||||
drivers/auth/img_parser_mod.c \
|
||||
drivers/auth/tbbr/tbbr_cot_common.c
|
||||
|
||||
BL2_SOURCES += ${AUTH_SOURCES} \
|
||||
plat/common/tbbr/plat_tbbr.c \
|
||||
plat/imx/imx7/common/imx7_trusted_boot.c \
|
||||
plat/imx/imx7/common/imx7_rotpk.S \
|
||||
drivers/auth/tbbr/tbbr_cot_bl2.c
|
||||
|
||||
ROT_KEY = $(BUILD_PLAT)/rot_key.pem
|
||||
ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
|
||||
|
||||
$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
|
||||
$(eval $(call MAKE_LIB_DIRS))
|
||||
|
||||
$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH)
|
||||
|
||||
certificates: $(ROT_KEY)
|
||||
|
||||
$(ROT_KEY): | $(BUILD_PLAT)
|
||||
@echo " OPENSSL $@"
|
||||
@if [ ! -f $(ROT_KEY) ]; then \
|
||||
${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
|
||||
fi
|
||||
|
||||
$(ROTPK_HASH): $(ROT_KEY)
|
||||
@echo " OPENSSL $@"
|
||||
$(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
|
||||
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
|
||||
endif
|
||||
|
||||
# Add the build options to pack BLx images and kernel device tree
|
||||
# in the FIP if the platform requires.
|
||||
ifneq ($(BL2),)
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
|
||||
endif
|
||||
ifneq ($(BL32_EXTRA1),)
|
||||
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
|
||||
endif
|
||||
ifneq ($(BL32_EXTRA2),)
|
||||
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
|
||||
endif
|
||||
ifneq ($(HW_CONFIG),)
|
||||
$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
|
||||
endif
|
||||
|
||||
# Verify build config
|
||||
# -------------------
|
||||
|
||||
ifeq (${ARCH},aarch64)
|
||||
$(error Error: AArch64 not supported on i.mx7)
|
||||
endif
|
||||
+198
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <lib/xlat_tables/xlat_mmu_helpers.h>
|
||||
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/optee_utils.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#include <imx_aips.h>
|
||||
#include <imx_caam.h>
|
||||
#include <imx_clock.h>
|
||||
#include <imx_csu.h>
|
||||
#include <imx_gpt.h>
|
||||
#include <imx_uart.h>
|
||||
#include <imx_snvs.h>
|
||||
#include <imx_wdog.h>
|
||||
#include <imx7_def.h>
|
||||
|
||||
#ifndef AARCH32_SP_OPTEE
|
||||
#error "Must build with OPTEE support included"
|
||||
#endif
|
||||
|
||||
uintptr_t plat_get_ns_image_entrypoint(void)
|
||||
{
|
||||
return IMX7_UBOOT_BASE;
|
||||
}
|
||||
|
||||
static uint32_t imx7_get_spsr_for_bl32_entry(void)
|
||||
{
|
||||
return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
|
||||
DISABLE_ALL_EXCEPTIONS);
|
||||
}
|
||||
|
||||
static uint32_t imx7_get_spsr_for_bl33_entry(void)
|
||||
{
|
||||
return SPSR_MODE32(MODE32_svc,
|
||||
plat_get_ns_image_entrypoint() & 0x1,
|
||||
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
|
||||
}
|
||||
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
int err = 0;
|
||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
bl_mem_params_node_t *hw_cfg_mem_params = NULL;
|
||||
|
||||
bl_mem_params_node_t *pager_mem_params = NULL;
|
||||
bl_mem_params_node_t *paged_mem_params = NULL;
|
||||
|
||||
assert(bl_mem_params);
|
||||
|
||||
switch (image_id) {
|
||||
case BL32_IMAGE_ID:
|
||||
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
|
||||
assert(pager_mem_params);
|
||||
|
||||
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
|
||||
assert(paged_mem_params);
|
||||
|
||||
err = parse_optee_header(&bl_mem_params->ep_info,
|
||||
&pager_mem_params->image_info,
|
||||
&paged_mem_params->image_info);
|
||||
if (err != 0)
|
||||
WARN("OPTEE header parse error.\n");
|
||||
|
||||
/*
|
||||
* When ATF loads the DTB the address of the DTB is passed in
|
||||
* arg2, if an hw config image is present use the base address
|
||||
* as DTB address an pass it as arg2
|
||||
*/
|
||||
hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
|
||||
|
||||
bl_mem_params->ep_info.args.arg0 =
|
||||
bl_mem_params->ep_info.args.arg1;
|
||||
bl_mem_params->ep_info.args.arg1 = 0;
|
||||
if (hw_cfg_mem_params)
|
||||
bl_mem_params->ep_info.args.arg2 =
|
||||
hw_cfg_mem_params->image_info.image_base;
|
||||
else
|
||||
bl_mem_params->ep_info.args.arg2 = 0;
|
||||
bl_mem_params->ep_info.args.arg3 = 0;
|
||||
bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry();
|
||||
break;
|
||||
|
||||
case BL33_IMAGE_ID:
|
||||
/* AArch32 only core: OP-TEE expects NSec EP in register LR */
|
||||
pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
|
||||
assert(pager_mem_params);
|
||||
pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
|
||||
|
||||
/* BL33 expects to receive the primary CPU MPID (through r0) */
|
||||
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
|
||||
bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry();
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Do nothing in default case */
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void bl2_el3_plat_arch_setup(void)
|
||||
{
|
||||
/* Setup the MMU here */
|
||||
}
|
||||
|
||||
static void imx7_setup_system_counter(void)
|
||||
{
|
||||
unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
|
||||
|
||||
/* Set the frequency table index to our target frequency */
|
||||
write_cntfrq(freq);
|
||||
|
||||
/* Enable system counter @ frequency table index 0, halt on debug */
|
||||
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
|
||||
CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
|
||||
}
|
||||
|
||||
static void imx7_setup_wdog_clocks(void)
|
||||
{
|
||||
uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT;
|
||||
|
||||
imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
|
||||
imx_clock_enable_wdog(0);
|
||||
imx_clock_enable_wdog(1);
|
||||
imx_clock_enable_wdog(2);
|
||||
imx_clock_enable_wdog(3);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* bl2_el3_early_platform_setup()
|
||||
* MMU off
|
||||
*/
|
||||
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4)
|
||||
{
|
||||
static console_t console;
|
||||
int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
|
||||
|
||||
/* Initialize common components */
|
||||
imx_aips_init();
|
||||
imx_csu_init();
|
||||
imx_snvs_init();
|
||||
imx_gpt_ops_init(GPT1_BASE_ADDR);
|
||||
imx_clock_init();
|
||||
imx7_setup_system_counter();
|
||||
imx7_setup_wdog_clocks();
|
||||
|
||||
/* Platform specific setup */
|
||||
imx7_platform_setup(arg1, arg2, arg3, arg4);
|
||||
|
||||
/* Init UART, clock should be enabled in imx7_platform_setup() */
|
||||
console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE,
|
||||
PLAT_IMX7_BOOT_UART_CLK_IN_HZ,
|
||||
PLAT_IMX7_CONSOLE_BAUDRATE,
|
||||
&console);
|
||||
console_set_scope(&console, console_scope);
|
||||
|
||||
/* Open handles to persistent storage */
|
||||
plat_imx_io_setup();
|
||||
|
||||
/* Setup higher-level functionality CAAM, RTC etc */
|
||||
imx_caam_init();
|
||||
imx_wdog_init();
|
||||
|
||||
/* Print out the expected memory map */
|
||||
VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT);
|
||||
VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
|
||||
VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
|
||||
VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX_FIP_BASE, IMX_FIP_LIMIT);
|
||||
VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT);
|
||||
VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT);
|
||||
VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT);
|
||||
}
|
||||
|
||||
/*
|
||||
* bl2_platform_setup()
|
||||
* MMU on - enabled by bl2_el3_plat_arch_setup()
|
||||
*/
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
}
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
||||
{
|
||||
.image_id = BL32_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
SECURE | EXECUTABLE | EP_FIRST_EXE),
|
||||
.ep_info.pc = BL32_BASE,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
|
||||
image_info_t, 0),
|
||||
|
||||
.image_info.image_base = IMX7_OPTEE_BASE,
|
||||
.image_info.image_max_size = IMX7_OPTEE_SIZE,
|
||||
|
||||
.next_handoff_image_id = BL33_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
.image_id = BL32_EXTRA1_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
|
||||
image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
|
||||
.image_info.image_base = IMX7_OPTEE_BASE,
|
||||
.image_info.image_max_size = IMX7_OPTEE_SIZE,
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
/* This is a zero sized image so we don't set base or size */
|
||||
.image_id = BL32_EXTRA2_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||
VERSION_2, entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_SKIP_LOADING),
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
.image_id = BL33_IMAGE_ID,
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
NON_SECURE | EXECUTABLE),
|
||||
# ifdef PRELOADED_BL33_BASE
|
||||
.ep_info.pc = PRELOADED_BL33_BASE,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_SKIP_LOADING),
|
||||
# else
|
||||
.ep_info.pc = BL33_BASE,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t, 0),
|
||||
.image_info.image_base = IMX7_UBOOT_BASE,
|
||||
.image_info.image_max_size = IMX7_UBOOT_SIZE,
|
||||
# endif /* PRELOADED_BL33_BASE */
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
}
|
||||
};
|
||||
|
||||
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include <platform_def.h>
|
||||
#include <imx_hab.h>
|
||||
|
||||
.globl platform_mem_init
|
||||
.globl plat_get_my_entrypoint
|
||||
.globl plat_crash_console_init
|
||||
.globl plat_crash_console_putc
|
||||
.globl plat_crash_console_flush
|
||||
.globl plat_panic_handler
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_mem_init(void)
|
||||
* Function to initialize memory.
|
||||
* The HAB hands off the DDR controller already
|
||||
* setup and ready to use.
|
||||
* Implement the mandatory function as a NOP
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func platform_mem_init
|
||||
bx lr
|
||||
endfunc platform_mem_init
|
||||
|
||||
func plat_get_my_entrypoint
|
||||
mov r0, #0
|
||||
bx lr
|
||||
endfunc plat_get_my_entrypoint
|
||||
|
||||
func plat_crash_console_init
|
||||
mov_imm r0, PLAT_IMX7_BOOT_UART_BASE
|
||||
mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ
|
||||
mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE
|
||||
b imx_crash_uart_init
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
func plat_crash_console_putc
|
||||
mov_imm r1, PLAT_IMX7_BOOT_UART_BASE
|
||||
b imx_crash_uart_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
||||
func plat_crash_console_flush
|
||||
/* Placeholder */
|
||||
mov r0, #0
|
||||
bx lr
|
||||
endfunc plat_crash_console_flush
|
||||
|
||||
func plat_panic_handler
|
||||
mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE
|
||||
ldr r3, [r3, #0]
|
||||
blx r3
|
||||
endfunc plat_panic_handler
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
void plat_flush_next_bl_params(void)
|
||||
{
|
||||
flush_bl_params_desc();
|
||||
}
|
||||
|
||||
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||
{
|
||||
return get_bl_load_info_from_mem_params_desc();
|
||||
}
|
||||
|
||||
bl_params_t *plat_get_next_bl_params(void)
|
||||
{
|
||||
return get_next_bl_params_from_mem_params_desc();
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
.global imx7_rotpk_hash
|
||||
.global imx7_rotpk_hash_end
|
||||
imx7_rotpk_hash:
|
||||
/* DER header */
|
||||
.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
|
||||
.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
|
||||
/* SHA256 */
|
||||
.incbin ROTPK_HASH
|
||||
imx7_rotpk_hash_end:
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[];
|
||||
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
*key_ptr = imx7_rotpk_hash;
|
||||
*key_len = imx7_rotpk_hash_end - imx7_rotpk_hash;
|
||||
*flags = ROTPK_IS_HASH;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
|
||||
{
|
||||
*nv_ctr = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
|
||||
{
|
||||
return get_mbedtls_heap_helper(heap_addr, heap_size);
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX7_DEF_H
|
||||
#define IMX7_DEF_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void plat_imx_io_setup(void);
|
||||
void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4);
|
||||
|
||||
#endif /*IMX7_DEF_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef IMX_HAB_ARCH_H
|
||||
#define IMX_HAB_ARCH_H
|
||||
|
||||
/* Define the offset the High Assurance Boot callback table is at */
|
||||
#define HAB_CALLBACK_OFFSET 0x100
|
||||
|
||||
#endif /* IMX_HAB_ARCH_H */
|
||||
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_REGS_H
|
||||
#define IMX_REGS_H
|
||||
|
||||
/* Define the processor memory map */
|
||||
|
||||
#define OCRAM_S_ALIAS_BASE 0x00000000 /* CM4 Alias Code */
|
||||
#define ROM_HIGH_BASE 0x00008000 /* ROM high 64k */
|
||||
#define ROM_HIGH_PROT_BASE 0x00017000 /* ROM high 64k protected */
|
||||
#define CAAM_BASE 0x00020000 /* CAAM block base address */
|
||||
#define OCRAM_S_BASE 0x00180000 /* OCRAM_S */
|
||||
#define ROM_LOW_BASE 0x007f8000 /* ROM low 64k */
|
||||
#define OCRAM_BASE 0x00900000 /* OCRAM base */
|
||||
#define CM4_ALIAS_CODE_BASE 0x04000000 /* CM4 alias code */
|
||||
#define TCM_BASE 0x1fff0000 /* TCM */
|
||||
#define BOOTROM_CP_BASE 0x20020000 /* Boot ROM (all 96KB) */
|
||||
#define CM4_ALIAS_SYSTEM_BASE 0x20100000 /* CM4 Alias system */
|
||||
#define EIM_BASE 0x28000000 /* EIM */
|
||||
|
||||
/* BootROM absolute base address */
|
||||
#define BOOTROM_BASE 0x00000000 /* BootROM */
|
||||
|
||||
/* Peripherals like GPIO live in the AIPS range */
|
||||
#define AIPS1_BASE 0x30000000 /* AIPS1 */
|
||||
#define AIPS2_BASE 0x30400000 /* AIPS2 */
|
||||
#define AIPS3_BASE 0x30800000 /* AIPS3 */
|
||||
#define AIPS4_BASE 0x30c00000 /* AIPS4 */
|
||||
|
||||
/* ARM peripherals like GIC */
|
||||
#define ARM_PERIPHERAL_GIC_BASE 0x31000000 /* GIC */
|
||||
|
||||
/* Configuration ports */
|
||||
#define GPV0_BASE 0x32000000 /* Main config port */
|
||||
#define GPV1_BASE 0x32100000 /* Wakeup config port */
|
||||
#define GPV2_BASE 0x32200000 /* Per_s config port */
|
||||
#define GPV3_BASE 0x32300000 /* Per_m config port */
|
||||
#define GPV4_BASE 0x32400000 /* Enet config port */
|
||||
#define GPV5_BASE 0x32500000 /* Display config port */
|
||||
#define GPV6_BASE 0x32600000 /* M4 conig port */
|
||||
|
||||
/* MMAP peripherals - like APBH DMA */
|
||||
#define APBH_DMA_BASE 0x33000000 /* APBH DMA block */
|
||||
|
||||
/* QSPI RX BUFFERS */
|
||||
#define QSPI_RX_BUFFER_BASE 0x34000000 /* QSPI RX buffers */
|
||||
|
||||
/* QSPI1 FLASH */
|
||||
#define QSPI_FLASH_BASE 0x60000000 /* QSPI1 flash */
|
||||
|
||||
/* AIPS1 block addresses */
|
||||
#define AIPSTZ_CONFIG_OFFSET 0x001f0000
|
||||
#define CCM_BASE (AIPS1_BASE + 0x380000)
|
||||
|
||||
/* Define the maximum number of UART blocks on this SoC */
|
||||
#define MXC_UART1_BASE (AIPS3_BASE + 0x060000)
|
||||
#define MXC_UART2_BASE (AIPS3_BASE + 0x070000)
|
||||
#define MXC_UART3_BASE (AIPS3_BASE + 0x080000)
|
||||
#define MXC_UART4_BASE (AIPS3_BASE + 0x260000)
|
||||
#define MXC_UART5_BASE (AIPS3_BASE + 0x270000)
|
||||
#define MXC_UART6_BASE (AIPS3_BASE + 0x280000)
|
||||
#define MXC_UART7_BASE (AIPS3_BASE + 0x290000)
|
||||
#define MXC_MAX_UART_NUM 0x07
|
||||
|
||||
/* Define the maximum number of USDHCI blocks on this SoC */
|
||||
#define MXC_MAX_USDHC_NUM 3
|
||||
|
||||
/* Define the number of CSU registers for this SoC */
|
||||
#define MXC_MAX_CSU_REGS 0x40
|
||||
#define CSU_BASE (AIPS1_BASE + 0x3E0000)
|
||||
|
||||
/* IO Mux block base */
|
||||
#define MXC_IO_MUXC_BASE (AIPS1_BASE + 0x330000)
|
||||
|
||||
/* SNVS base */
|
||||
#define SNVS_BASE (AIPS1_BASE + 0x370000)
|
||||
|
||||
/* GP Timer base */
|
||||
#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000)
|
||||
|
||||
/* MMC base */
|
||||
#define USDHC1_BASE (AIPS1_BASE + 0xb40000)
|
||||
#define USDHC2_BASE (AIPS1_BASE + 0xb50000)
|
||||
#define USDHC3_BASE (AIPS1_BASE + 0xb60000)
|
||||
|
||||
/* Arm optional memory mapped counter module base address */
|
||||
#define SYS_CNTCTL_BASE (AIPS2_BASE + 0x2c0000)
|
||||
|
||||
/* Define CAAM AIPS offset */
|
||||
#define CAAM_AIPS_BASE (AIPS3_BASE + 0x100000)
|
||||
#define CAAM_NUM_JOB_RINGS 0x03
|
||||
#define CAAM_NUM_RTIC 0x04
|
||||
#define CAAM_NUM_DECO 0x01
|
||||
|
||||
/* Define watchdog base addresses */
|
||||
#define WDOG1_BASE (AIPS1_BASE + 0x280000)
|
||||
#define WDOG2_BASE (AIPS1_BASE + 0x290000)
|
||||
#define WDOG3_BASE (AIPS1_BASE + 0x2A0000)
|
||||
#define WDOG4_BASE (AIPS1_BASE + 0x280000)
|
||||
|
||||
/* Define the maximum number of WDOG blocks on this SoC */
|
||||
#define MXC_MAX_WDOG_NUM 0x04
|
||||
|
||||
#endif /* IMX_REGS_H */
|
||||
+204
@@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
|
||||
|
||||
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
|
||||
|
||||
#define PICOPI_PRIMARY_CPU U(0)
|
||||
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
|
||||
#define PLAT_MAX_RET_STATE 1
|
||||
#define PLAT_MAX_OFF_STATE 2
|
||||
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define PLAT_LOCAL_STATE_RUN 0
|
||||
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define PLAT_LOCAL_STATE_RET 1
|
||||
|
||||
/*
|
||||
* Local power state for OFF/power-down. Valid for CPU and cluster power
|
||||
* domains.
|
||||
*/
|
||||
#define PLAT_LOCAL_STATE_OFF 2
|
||||
|
||||
/*
|
||||
* Macros used to parse state information from State-ID if it is using the
|
||||
* recommended encoding for State-ID.
|
||||
*/
|
||||
#define PLAT_LOCAL_PSTATE_WIDTH 4
|
||||
#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
* i.MX7 has a 32 byte cacheline size
|
||||
* i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT 4
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/*
|
||||
* Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
|
||||
*/
|
||||
#define BOOT_ROM_BASE 0x00000000
|
||||
#define BOOT_ROM_SIZE 0x00020000
|
||||
|
||||
#define OCRAM_S_BASE 0x00180000
|
||||
#define OCRAM_S_SIZE 0x00008000
|
||||
|
||||
/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
|
||||
#define DRAM_BASE 0x80000000
|
||||
#define DRAM_SIZE 0x20000000
|
||||
#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
|
||||
|
||||
/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
|
||||
#define IMX7_OPTEE_SIZE 0x02000000
|
||||
#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
|
||||
#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
|
||||
|
||||
/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
|
||||
#define BL2_RAM_SIZE 0x00100000
|
||||
#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
|
||||
#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
|
||||
|
||||
/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
|
||||
#define SHARED_RAM_SIZE 0x00001000
|
||||
#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
|
||||
#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
|
||||
|
||||
/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
|
||||
#define IMX7_UBOOT_SIZE 0x00100000
|
||||
#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
|
||||
#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
|
||||
|
||||
/* Define FIP image absolute location 0x80000000 - 0x80100000 */
|
||||
#define IMX_FIP_SIZE 0x00100000
|
||||
#define IMX_FIP_BASE (DRAM_BASE)
|
||||
#define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE)
|
||||
|
||||
/* Define FIP image location at 1MB offset */
|
||||
#define IMX_FIP_MMC_BASE (1024 * 1024)
|
||||
|
||||
/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
|
||||
#define IMX7_DTB_SIZE 0x00100000
|
||||
#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
|
||||
#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
|
||||
|
||||
/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
|
||||
#define IMX7_DTB_OVERLAY_SIZE 0x00001000
|
||||
#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
|
||||
#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
|
||||
IMX7_DTB_OVERLAY_SIZE)
|
||||
/*
|
||||
* BL2 specific defines.
|
||||
*
|
||||
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
|
||||
* size plus a little space for growth.
|
||||
*/
|
||||
#define BL2_BASE BL2_RAM_BASE
|
||||
#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
|
||||
|
||||
/*
|
||||
* BL3-2/OPTEE
|
||||
*/
|
||||
# define BL32_BASE IMX7_OPTEE_BASE
|
||||
# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
|
||||
|
||||
/*
|
||||
* BL3-3/U-BOOT
|
||||
*/
|
||||
#define BL33_BASE IMX7_UBOOT_BASE
|
||||
#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
|
||||
|
||||
/*
|
||||
* ATF's view of memory
|
||||
*
|
||||
* 0xa0000000 +-----------------+
|
||||
* | DDR | BL32/OPTEE
|
||||
* 0x9e000000 +-----------------+
|
||||
* | DDR | BL23 ATF
|
||||
* 0x9df00000 +-----------------+
|
||||
* | DDR | Shared MBOX RAM
|
||||
* 0x9de00000 +-----------------+
|
||||
* | DDR | Unallocated
|
||||
* 0x87900000 +-----------------+
|
||||
* | DDR | BL33/U-BOOT
|
||||
* 0x87800000 +-----------------+
|
||||
* | DDR | Unallocated
|
||||
* 0x83100000 +-----------------+
|
||||
* | DDR | DTB
|
||||
* 0x83000000 +-----------------+
|
||||
* | DDR | Unallocated
|
||||
* 0x80100000 +-----------------+
|
||||
* | DDR | FIP
|
||||
* 0x80000000 +-----------------+
|
||||
* | SOC I/0 |
|
||||
* 0x00a00000 +-----------------+
|
||||
* | OCRAM | Not used
|
||||
* 0x00900000 +-----------------+
|
||||
* | SOC I/0 |
|
||||
* 0x00188000 +-----------------+
|
||||
* | OCRAM_S | Not used
|
||||
* 0x00180000 +-----------------+
|
||||
* | SOC I/0 |
|
||||
* 0x00020000 +-----------------+
|
||||
* | BootROM | BL1
|
||||
* 0x00000000 +-----------------+
|
||||
*/
|
||||
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define MAX_MMAP_REGIONS 10
|
||||
#define MAX_XLAT_TABLES 6
|
||||
#define MAX_IO_DEVICES 2
|
||||
#define MAX_IO_HANDLES 3
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
|
||||
/* UART defines */
|
||||
#define PLAT_IMX7_BOOT_UART_BASE MXC_UART5_BASE
|
||||
#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
|
||||
#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
|
||||
|
||||
/* MMC defines */
|
||||
#ifndef PLAT_PICOPI_SD
|
||||
#define PLAT_PICOPI_SD 3
|
||||
#endif
|
||||
|
||||
#if PLAT_PICOPI_SD == 1
|
||||
#define PLAT_PICOPI_BOOT_MMC_BASE USDHC1_BASE
|
||||
#endif /* PLAT_PICOPI_SD == 1 */
|
||||
|
||||
#if PLAT_PICOPI_SD == 2
|
||||
#define PLAT_PICOPI_BOOT_MMC_BASE USDHC2_BASE
|
||||
#endif /* PLAT_PICOPI_SD == 2 */
|
||||
|
||||
#if PLAT_PICOPI_SD == 3
|
||||
#define PLAT_PICOPI_BOOT_MMC_BASE USDHC3_BASE
|
||||
#endif /* PLAT_PICOPI_SD == 3 */
|
||||
|
||||
/*
|
||||
* System counter
|
||||
*/
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
+134
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#include <imx_caam.h>
|
||||
#include <imx_clock.h>
|
||||
#include <imx_io_mux.h>
|
||||
#include <imx_uart.h>
|
||||
#include <imx_usdhc.h>
|
||||
#include <imx7_def.h>
|
||||
|
||||
#define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M)
|
||||
|
||||
#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
|
||||
CCM_TARGET_POST_PODF(2))
|
||||
|
||||
#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
|
||||
|
||||
#define PICOPI_UART5_RX_MUX \
|
||||
IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA
|
||||
|
||||
#define PICOPI_UART5_TX_MUX \
|
||||
IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA
|
||||
|
||||
#define PICOPI_SD3_FEATURES \
|
||||
(IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_SD3_PE | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_SD3_HYS | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
|
||||
|
||||
static struct mmc_device_info mmc_info;
|
||||
|
||||
static void picopi_setup_pinmux(void)
|
||||
{
|
||||
/* Configure UART5 TX */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET,
|
||||
PICOPI_UART5_TX_MUX);
|
||||
/* Configure UART5 RX */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET,
|
||||
PICOPI_UART5_RX_MUX);
|
||||
|
||||
/* Configure USDHC3 */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0);
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET,
|
||||
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B);
|
||||
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET,
|
||||
PICOPI_SD3_FEATURES);
|
||||
}
|
||||
|
||||
static void picopi_usdhc_setup(void)
|
||||
{
|
||||
imx_usdhc_params_t params;
|
||||
|
||||
zeromem(¶ms, sizeof(imx_usdhc_params_t));
|
||||
params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
|
||||
params.clk_rate = 25000000;
|
||||
params.bus_width = MMC_BUS_WIDTH_8;
|
||||
mmc_info.mmc_dev_type = MMC_IS_EMMC;
|
||||
imx_usdhc_init(¶ms, &mmc_info);
|
||||
}
|
||||
|
||||
static void picopi_setup_usb_clocks(void)
|
||||
{
|
||||
uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
|
||||
|
||||
imx_clock_set_usb_clk_root_bits(usb_en_bits);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
|
||||
}
|
||||
|
||||
void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4)
|
||||
{
|
||||
uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT;
|
||||
uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1;
|
||||
|
||||
/* Initialize clocks etc */
|
||||
imx_clock_enable_uart(4, uart5_en_bits);
|
||||
imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
|
||||
|
||||
picopi_setup_usb_clocks();
|
||||
|
||||
/* Setup pin-muxes */
|
||||
picopi_setup_pinmux();
|
||||
|
||||
picopi_usdhc_setup();
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
#
|
||||
# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Include imx7 common
|
||||
include plat/imx/imx7/common/imx7.mk
|
||||
|
||||
# Platform
|
||||
PLAT_INCLUDES += -Iplat/imx/imx7/picopi/include \
|
||||
|
||||
BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \
|
||||
plat/imx/imx7/picopi/picopi_bl2_el3_setup.c \
|
||||
|
||||
# Build config flags
|
||||
# ------------------
|
||||
|
||||
ARM_CORTEX_A7 := yes
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
|
||||
RESET_TO_BL31 := 0
|
||||
|
||||
# Non-TF Boot ROM
|
||||
BL2_AT_EL3 := 1
|
||||
|
||||
# Indicate single-core
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
|
||||
# Have different sections for code and rodata
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# Use Coherent memory
|
||||
USE_COHERENT_MEM := 1
|
||||
|
||||
# Use multi console API
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
PLAT_PICOPI_UART :=5
|
||||
$(eval $(call add_define,PLAT_PICOPI_UART))
|
||||
+218
@@ -0,0 +1,218 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
|
||||
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER1_CORE_COUNT)
|
||||
|
||||
#define WARP7_PRIMARY_CPU U(0)
|
||||
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
|
||||
#define PLAT_MAX_RET_STATE 1
|
||||
#define PLAT_MAX_OFF_STATE 2
|
||||
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define PLAT_LOCAL_STATE_RUN 0
|
||||
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define PLAT_LOCAL_STATE_RET 1
|
||||
|
||||
/*
|
||||
* Local power state for OFF/power-down. Valid for CPU and cluster power
|
||||
* domains.
|
||||
*/
|
||||
#define PLAT_LOCAL_STATE_OFF 2
|
||||
|
||||
/*
|
||||
* Macros used to parse state information from State-ID if it is using the
|
||||
* recommended encoding for State-ID.
|
||||
*/
|
||||
#define PLAT_LOCAL_PSTATE_WIDTH 4
|
||||
#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
* i.MX7 has a 32 byte cacheline size
|
||||
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 pg 244
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT 4
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/*
|
||||
* Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
|
||||
*/
|
||||
#define BOOT_ROM_BASE 0x00000000
|
||||
#define BOOT_ROM_SIZE 0x00020000
|
||||
|
||||
#define OCRAM_S_BASE 0x00180000
|
||||
#define OCRAM_S_SIZE 0x00008000
|
||||
|
||||
/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
|
||||
#define DRAM_BASE 0x80000000
|
||||
#define DRAM_SIZE 0x20000000
|
||||
#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
|
||||
|
||||
/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
|
||||
#define IMX7_OPTEE_SIZE 0x02000000
|
||||
#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
|
||||
#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
|
||||
|
||||
/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
|
||||
#define BL2_RAM_SIZE 0x00100000
|
||||
#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
|
||||
#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
|
||||
|
||||
/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
|
||||
#define SHARED_RAM_SIZE 0x00001000
|
||||
#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
|
||||
#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
|
||||
|
||||
/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
|
||||
#define IMX7_UBOOT_SIZE 0x00100000
|
||||
#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
|
||||
#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
|
||||
|
||||
/* Define FIP image absolute location 0x80000000 - 0x80100000 */
|
||||
#define IMX_FIP_SIZE 0x00100000
|
||||
#define IMX_FIP_BASE (DRAM_BASE)
|
||||
#define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE)
|
||||
|
||||
/* Define FIP image location at 1MB offset */
|
||||
#define IMX_FIP_MMC_BASE (1024 * 1024)
|
||||
|
||||
/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
|
||||
#define IMX7_DTB_SIZE 0x00100000
|
||||
#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
|
||||
#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
|
||||
|
||||
/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
|
||||
#define IMX7_DTB_OVERLAY_SIZE 0x00001000
|
||||
#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
|
||||
#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
|
||||
IMX7_DTB_OVERLAY_SIZE)
|
||||
|
||||
/*
|
||||
* BL2 specific defines.
|
||||
*
|
||||
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
|
||||
* size plus a little space for growth.
|
||||
*/
|
||||
#define BL2_BASE BL2_RAM_BASE
|
||||
#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
|
||||
|
||||
/*
|
||||
* BL3-2/OPTEE
|
||||
*/
|
||||
# define BL32_BASE IMX7_OPTEE_BASE
|
||||
# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
|
||||
|
||||
/*
|
||||
* BL3-3/U-BOOT
|
||||
*/
|
||||
#define BL33_BASE IMX7_UBOOT_BASE
|
||||
#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
|
||||
|
||||
/*
|
||||
* ATF's view of memory
|
||||
*
|
||||
* 0xa0000000 +-----------------+
|
||||
* | DDR | BL32/OPTEE
|
||||
* 0x9e000000 +-----------------+
|
||||
* | DDR | BL23 ATF
|
||||
* 0x9df00000 +-----------------+
|
||||
* | DDR | Shared MBOX RAM
|
||||
* 0x9de00000 +-----------------+
|
||||
* | DDR | Unallocated
|
||||
* 0x87900000 +-----------------+
|
||||
* | DDR | BL33/U-BOOT
|
||||
* 0x87800000 +-----------------+
|
||||
* | DDR | Unallocated
|
||||
* 0x83101000 +-----------------+
|
||||
* | DDR | DTB Overlay
|
||||
* 0x83100000 +-----------------+
|
||||
* | DDR | DTB
|
||||
* 0x83000000 +-----------------+
|
||||
* | DDR | Unallocated
|
||||
* 0x80100000 +-----------------+
|
||||
* | DDR | FIP
|
||||
* 0x80000000 +-----------------+
|
||||
* | SOC I/0 |
|
||||
* 0x00a00000 +-----------------+
|
||||
* | OCRAM | Not used
|
||||
* 0x00900000 +-----------------+
|
||||
* | SOC I/0 |
|
||||
* 0x00188000 +-----------------+
|
||||
* | OCRAM_S | Not used
|
||||
* 0x00180000 +-----------------+
|
||||
* | SOC I/0 |
|
||||
* 0x00020000 +-----------------+
|
||||
* | BootROM | BL1
|
||||
* 0x00000000 +-----------------+
|
||||
*/
|
||||
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define MAX_MMAP_REGIONS 10
|
||||
#define MAX_XLAT_TABLES 6
|
||||
#define MAX_IO_DEVICES 2
|
||||
#define MAX_IO_HANDLES 3
|
||||
#define MAX_IO_BLOCK_DEVICES 1U
|
||||
|
||||
/* UART defines */
|
||||
#if PLAT_WARP7_UART == 1
|
||||
#define PLAT_WARP7_UART_BASE MXC_UART1_BASE
|
||||
#elif PLAT_WARP7_UART == 6
|
||||
#define IMX_UART_DTE
|
||||
#define PLAT_WARP7_UART_BASE MXC_UART6_BASE
|
||||
#else
|
||||
#error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
|
||||
#endif
|
||||
|
||||
#define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE
|
||||
#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
|
||||
#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
|
||||
|
||||
/* MMC defines */
|
||||
#ifndef PLAT_WARP7_SD
|
||||
#define PLAT_WARP7_SD 3
|
||||
#endif
|
||||
|
||||
#if PLAT_WARP7_SD == 1
|
||||
#define PLAT_WARP7_BOOT_MMC_BASE USDHC1_BASE
|
||||
#endif /* PLAT_WARP7_SD == 1 */
|
||||
|
||||
#if PLAT_WARP7_SD == 2
|
||||
#define PLAT_WARP7_BOOT_MMC_BASE USDHC2_BASE
|
||||
#endif /* PLAT_WARP7_SD == 2 */
|
||||
|
||||
#if PLAT_WARP7_SD == 3
|
||||
#define PLAT_WARP7_BOOT_MMC_BASE USDHC3_BASE
|
||||
#endif /* PLAT_WARP7_SD == 3 */
|
||||
|
||||
/*
|
||||
* System counter
|
||||
*/
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
@@ -0,0 +1,37 @@
|
||||
#
|
||||
# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Include imx7 common
|
||||
include plat/imx/imx7/common/imx7.mk
|
||||
|
||||
# Platform
|
||||
PLAT_INCLUDES += -Iplat/imx/imx7/warp7/include
|
||||
|
||||
BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \
|
||||
plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
|
||||
|
||||
# Build config flags
|
||||
# ------------------
|
||||
|
||||
ARM_CORTEX_A7 := yes
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
|
||||
RESET_TO_BL31 := 0
|
||||
|
||||
# Non-TF Boot ROM
|
||||
BL2_AT_EL3 := 1
|
||||
|
||||
# Indicate single-core
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
|
||||
# Have different sections for code and rodata
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# Use Coherent memory
|
||||
USE_COHERENT_MEM := 1
|
||||
|
||||
PLAT_WARP7_UART :=1
|
||||
$(eval $(call add_define,PLAT_WARP7_UART))
|
||||
+143
@@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#include <imx_caam.h>
|
||||
#include <imx_clock.h>
|
||||
#include <imx_io_mux.h>
|
||||
#include <imx_uart.h>
|
||||
#include <imx_usdhc.h>
|
||||
#include <imx7_def.h>
|
||||
|
||||
#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
|
||||
|
||||
#define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M)
|
||||
|
||||
#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
|
||||
CCM_TARGET_POST_PODF(2))
|
||||
|
||||
#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
|
||||
CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
|
||||
|
||||
#define WARP7_UART1_TX_MUX \
|
||||
IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
|
||||
|
||||
#define WARP7_UART1_TX_FEATURES \
|
||||
(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4)
|
||||
|
||||
#define WARP7_UART1_RX_MUX \
|
||||
IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA
|
||||
|
||||
#define WARP7_UART1_RX_FEATURES \
|
||||
(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4)
|
||||
|
||||
#define WARP7_UART6_TX_MUX \
|
||||
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA
|
||||
|
||||
#define WARP7_UART6_TX_FEATURES \
|
||||
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4)
|
||||
|
||||
#define WARP7_UART6_RX_MUX \
|
||||
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA
|
||||
|
||||
#define WARP7_UART6_RX_FEATURES \
|
||||
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
|
||||
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
|
||||
|
||||
static struct mmc_device_info mmc_info;
|
||||
|
||||
static void warp7_setup_pinmux(void)
|
||||
{
|
||||
/* Configure UART1 TX */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET,
|
||||
WARP7_UART1_TX_MUX);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET,
|
||||
WARP7_UART1_TX_FEATURES);
|
||||
|
||||
/* Configure UART1 RX */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET,
|
||||
WARP7_UART1_RX_MUX);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET,
|
||||
WARP7_UART1_RX_FEATURES);
|
||||
|
||||
/* Configure UART6 TX */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET,
|
||||
WARP7_UART6_TX_MUX);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET,
|
||||
WARP7_UART6_TX_FEATURES);
|
||||
|
||||
/* Configure UART6 RX */
|
||||
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET,
|
||||
WARP7_UART6_RX_MUX);
|
||||
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET,
|
||||
WARP7_UART6_RX_FEATURES);
|
||||
}
|
||||
|
||||
static void warp7_usdhc_setup(void)
|
||||
{
|
||||
imx_usdhc_params_t params;
|
||||
|
||||
zeromem(¶ms, sizeof(imx_usdhc_params_t));
|
||||
params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
|
||||
params.clk_rate = 25000000;
|
||||
params.bus_width = MMC_BUS_WIDTH_8;
|
||||
mmc_info.mmc_dev_type = MMC_IS_EMMC;
|
||||
imx_usdhc_init(¶ms, &mmc_info);
|
||||
}
|
||||
|
||||
static void warp7_setup_usb_clocks(void)
|
||||
{
|
||||
uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
|
||||
|
||||
imx_clock_set_usb_clk_root_bits(usb_en_bits);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
|
||||
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
|
||||
}
|
||||
|
||||
void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4)
|
||||
{
|
||||
uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
|
||||
uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
|
||||
uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
|
||||
|
||||
/* Initialize clocks etc */
|
||||
imx_clock_enable_uart(0, uart1_en_bits);
|
||||
imx_clock_enable_uart(5, uart6_en_bits);
|
||||
|
||||
imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
|
||||
|
||||
warp7_setup_usb_clocks();
|
||||
|
||||
/* Setup pin-muxes */
|
||||
warp7_setup_pinmux();
|
||||
|
||||
warp7_usdhc_setup();
|
||||
}
|
||||
@@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright 2018-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define IMX_CCM_IP_BASE (IMX_CCM_BASE + 0xa000)
|
||||
#define DRAM_SEL_CFG (IMX_CCM_BASE + 0x9800)
|
||||
#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x00)
|
||||
#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x04)
|
||||
#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x08)
|
||||
#define PLL_FREQ_800M U(0x00ece580)
|
||||
#define PLL_FREQ_400M U(0x00ec6984)
|
||||
#define PLL_FREQ_167M U(0x00f5a406)
|
||||
|
||||
void ddr_pll_bypass_100mts(void)
|
||||
{
|
||||
/* change the clock source of dram_alt_clk_root to source 2 --100MHz */
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16));
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x2 << 24));
|
||||
|
||||
/* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x2 << 24) | (0x1 << 16));
|
||||
|
||||
/* configure pll bypass mode */
|
||||
mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24));
|
||||
}
|
||||
|
||||
void ddr_pll_bypass_400mts(void)
|
||||
{
|
||||
/* change the clock source of dram_alt_clk_root to source 1 --400MHz */
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16));
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x1 << 24) | (0x1 << 16));
|
||||
|
||||
/* change the clock source of dram_apb_clk_root to source 3 --160MHz/2 */
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x3 << 24) | (0x1 << 16));
|
||||
|
||||
/* configure pll bypass mode */
|
||||
mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24));
|
||||
}
|
||||
|
||||
void ddr_pll_unbypass(void)
|
||||
{
|
||||
mmio_write_32(DRAM_SEL_CFG + 0x8, BIT(24));
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
|
||||
/* to source 4 --800MHz/5 */
|
||||
mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x4 << 16));
|
||||
}
|
||||
|
||||
#if defined(PLAT_imx8mq)
|
||||
void dram_pll_init(unsigned int drate)
|
||||
{
|
||||
/* bypass the PLL */
|
||||
mmio_setbits_32(HW_DRAM_PLL_CFG0, 0x30);
|
||||
|
||||
switch (drate) {
|
||||
case 3200:
|
||||
mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_800M);
|
||||
break;
|
||||
case 1600:
|
||||
mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_400M);
|
||||
break;
|
||||
case 667:
|
||||
mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_167M);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* unbypass the PLL */
|
||||
mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30);
|
||||
while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & (1 << 31))) {
|
||||
;
|
||||
}
|
||||
}
|
||||
#else
|
||||
void dram_pll_init(unsigned int drate)
|
||||
{
|
||||
/* bypass the PLL */
|
||||
mmio_setbits_32(DRAM_PLL_CTRL, (1 << 16));
|
||||
mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9));
|
||||
|
||||
switch (drate) {
|
||||
case 2400:
|
||||
mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2);
|
||||
break;
|
||||
case 1600:
|
||||
mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3);
|
||||
break;
|
||||
case 1066:
|
||||
mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3);
|
||||
break;
|
||||
case 667:
|
||||
mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 4);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
mmio_setbits_32(DRAM_PLL_CTRL, BIT(9));
|
||||
/* wait for PLL locked */
|
||||
while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) {
|
||||
;
|
||||
}
|
||||
|
||||
/* unbypass the PLL */
|
||||
mmio_clrbits_32(DRAM_PLL_CTRL, BIT(16));
|
||||
}
|
||||
#endif
|
||||
|
||||
/* change the dram clock frequency */
|
||||
void dram_clock_switch(unsigned int target_drate, bool bypass_mode)
|
||||
{
|
||||
if (bypass_mode) {
|
||||
switch (target_drate) {
|
||||
case 400:
|
||||
ddr_pll_bypass_400mts();
|
||||
break;
|
||||
case 100:
|
||||
ddr_pll_bypass_100mts();
|
||||
break;
|
||||
default:
|
||||
ddr_pll_unbypass();
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
dram_pll_init(target_drate);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* Copyright 2018-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <dram.h>
|
||||
|
||||
void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, uint32_t rank)
|
||||
{
|
||||
uint32_t val, mr_mirror, data_mirror;
|
||||
|
||||
/*
|
||||
* 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure
|
||||
* that there is no outstanding MR transAction.
|
||||
*/
|
||||
while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) {
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank
|
||||
* and (for MRWs) MRCTRL1.mr_data to define the MR transaction.
|
||||
*/
|
||||
val = mmio_read_32(DDRC_DIMMCTL(0));
|
||||
if ((val & 0x2) && (rank == 0x2)) {
|
||||
mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1); /* BA0, BA1 swap */
|
||||
data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) |
|
||||
((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) |
|
||||
((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ;
|
||||
} else {
|
||||
mr_mirror = mr;
|
||||
data_mirror = data;
|
||||
}
|
||||
|
||||
mmio_write_32(DDRC_MRCTRL0(0), mr_type | (mr_mirror << 12) | (rank << 4));
|
||||
mmio_write_32(DDRC_MRCTRL1(0), data_mirror);
|
||||
|
||||
/*
|
||||
* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1.
|
||||
* This bit is self-clearing, and triggers the MR transaction.
|
||||
* The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs
|
||||
* the MR transaction to SDRAM, and no further accesses can be
|
||||
* initiated until it is deasserted.
|
||||
*/
|
||||
mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31));
|
||||
|
||||
while (mmio_read_32(DDRC_MRSTAT(0))) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate)
|
||||
{
|
||||
uint32_t num_rank = info->num_rank;
|
||||
/*
|
||||
* 15. Perform MRS commands as required to re-program
|
||||
* timing registers in the SDRAM for the new frequency
|
||||
* (in particular, CL, CWL and WR may need to be changed).
|
||||
*/
|
||||
|
||||
for (int i = 1; i <= num_rank; i++) {
|
||||
for (int j = 0; j < 6; j++) {
|
||||
ddr4_mr_write(j, info->mr_table[pstate][j], 0, i);
|
||||
}
|
||||
ddr4_mr_write(6, info->mr_table[pstate][7], 0, i);
|
||||
}
|
||||
}
|
||||
|
||||
void sw_pstate(uint32_t pstate, uint32_t drate)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x0);
|
||||
|
||||
/*
|
||||
* Update any registers which may be required to
|
||||
* change for the new frequency.
|
||||
*/
|
||||
mmio_write_32(DDRC_MSTR2(0), pstate);
|
||||
mmio_setbits_32(DDRC_MSTR(0), (0x1 << 29));
|
||||
|
||||
/*
|
||||
* Toggle RFSHCTL3.refresh_update_level to allow the
|
||||
* new refresh-related register values to propagate
|
||||
* to the refresh logic.
|
||||
*/
|
||||
val = mmio_read_32(DDRC_RFSHCTL3(0));
|
||||
if (val & 0x2) {
|
||||
mmio_write_32(DDRC_RFSHCTL3(0), val & 0xFFFFFFFD);
|
||||
} else {
|
||||
mmio_write_32(DDRC_RFSHCTL3(0), val | 0x2);
|
||||
}
|
||||
|
||||
/*
|
||||
* 19. If required, trigger the initialization in the PHY.
|
||||
* If using the gen2 multiPHY, PLL initialization should
|
||||
* be triggered at this point. See the PHY databook for
|
||||
* details about the frequency change procedure.
|
||||
*/
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8));
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x00000020 | (pstate << 8));
|
||||
|
||||
/* wait DFISTAT.dfi_init_complete to 0 */
|
||||
while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) {
|
||||
;
|
||||
}
|
||||
|
||||
/* change the clock to the target frequency */
|
||||
dram_clock_switch(drate, false);
|
||||
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8));
|
||||
|
||||
/* wait DFISTAT.dfi_init_complete to 1 */
|
||||
while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) {
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* When changing frequencies the controller may violate the JEDEC
|
||||
* requirement that no more than 16 refreshes should be issued within
|
||||
* 2*tREFI. These extra refreshes are not expected to cause a problem
|
||||
* in the SDRAM. This issue can be avoided by waiting for at least 2*tREFI
|
||||
* before exiting self-refresh in step 19.
|
||||
*/
|
||||
udelay(14);
|
||||
|
||||
/* 14. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */
|
||||
mmio_clrbits_32(DDRC_PWRCTL(0), (1 << 5));
|
||||
|
||||
while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void ddr4_swffc(struct dram_info *info, unsigned int pstate)
|
||||
{
|
||||
uint32_t drate = info->timing_info->fsp_table[pstate];
|
||||
|
||||
/*
|
||||
* 1. set SWCTL.sw_done to disable quasi-dynamic register
|
||||
* programming outside reset.
|
||||
*/
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x0);
|
||||
|
||||
/*
|
||||
* 2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s)
|
||||
* from taking any transaction (blocks traffic on AXI ports).
|
||||
*/
|
||||
mmio_write_32(DDRC_PCTRL_0(0), 0x0);
|
||||
|
||||
/*
|
||||
* 3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0.
|
||||
* Wait until all AXI ports are idle (the uMCTL2 core has to
|
||||
* be idle).
|
||||
*/
|
||||
while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) {
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* 4. Write 0 to SBRCTL.scrub_en. Disable SBR, required only if
|
||||
* SBR instantiated.
|
||||
* 5. Poll SBRSTAT.scrub_busy=0.
|
||||
* 6. Set DERATEEN.derate_enable = 0, if DERATEEN.derate_eanble = 1
|
||||
* and the read latency (RL) value needs to change after the frequency
|
||||
* change (LPDDR2/3/4 only).
|
||||
* 7. Set DBG1.dis_hif=1 so that no new commands will be accepted by the uMCTL2.
|
||||
*/
|
||||
mmio_setbits_32(DDRC_DBG1(0), (0x1 << 1));
|
||||
|
||||
/*
|
||||
* 8. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure
|
||||
* that write and read data buffers are empty.
|
||||
*/
|
||||
while ((mmio_read_32(DDRC_DBGCAM(0)) & 0x06000000) != 0x06000000) {
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* 9. For DDR4, update MR6 with the new tDLLK value via the Mode
|
||||
* Register Write signals
|
||||
* 10. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1,
|
||||
* and wait until DFISTAT.dfi_lp_ack
|
||||
* 11. If DFI PHY Master interface is active in uMCTL2, then disable it
|
||||
* 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the
|
||||
* controller is not in self-refresh mode.
|
||||
*/
|
||||
while ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) {
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter
|
||||
* the self-refresh mode.
|
||||
*/
|
||||
mmio_setbits_32(DDRC_PWRCTL(0), (1 << 5));
|
||||
|
||||
/*
|
||||
* 14. Wait until STAT.operating_mode[1:0]==11 indicating that the
|
||||
* controller core is in self-refresh mode.
|
||||
*/
|
||||
while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) != 0x23) {
|
||||
;
|
||||
}
|
||||
|
||||
sw_pstate(pstate, drate);
|
||||
dram_cfg_all_mr(info, pstate);
|
||||
|
||||
/* 23. Enable HIF commands by setting DBG1.dis_hif=0. */
|
||||
mmio_clrbits_32(DDRC_DBG1(0), (0x1 << 1));
|
||||
|
||||
/*
|
||||
* 24. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable
|
||||
* has been set to 0 in step 6.
|
||||
* 25. If DFI PHY Master interface was active before step 11 then
|
||||
* enable it back by programming DFIPHYMSTR.phymstr_en = 1'b1.
|
||||
* 26. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked
|
||||
* from taking transactions (Re-enable traffic on AXI ports)
|
||||
*/
|
||||
mmio_write_32(DDRC_PCTRL_0(0), 0x1);
|
||||
|
||||
/*
|
||||
* 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only
|
||||
* required if SBR instantiated.
|
||||
*/
|
||||
|
||||
/*
|
||||
* set SWCTL.sw_done to enable quasi-dynamic register programming
|
||||
* outside reset.
|
||||
*/
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x1);
|
||||
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,263 @@
|
||||
/*
|
||||
* Copyright 2019-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <bl31/interrupt_mgmt.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/spinlock.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <dram.h>
|
||||
|
||||
#define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10
|
||||
#define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11
|
||||
|
||||
struct dram_info dram_info;
|
||||
|
||||
/* lock used for DDR DVFS */
|
||||
spinlock_t dfs_lock;
|
||||
|
||||
static volatile uint32_t wfe_done;
|
||||
static volatile bool wait_ddrc_hwffc_done = true;
|
||||
static unsigned int dev_fsp = 0x1;
|
||||
|
||||
static uint32_t fsp_init_reg[3][4] = {
|
||||
{ DDRC_INIT3(0), DDRC_INIT4(0), DDRC_INIT6(0), DDRC_INIT7(0) },
|
||||
{ DDRC_FREQ1_INIT3(0), DDRC_FREQ1_INIT4(0), DDRC_FREQ1_INIT6(0), DDRC_FREQ1_INIT7(0) },
|
||||
{ DDRC_FREQ2_INIT3(0), DDRC_FREQ2_INIT4(0), DDRC_FREQ2_INIT6(0), DDRC_FREQ2_INIT7(0) },
|
||||
};
|
||||
|
||||
static void get_mr_values(uint32_t (*mr_value)[8])
|
||||
{
|
||||
uint32_t init_val;
|
||||
unsigned int i, fsp_index;
|
||||
|
||||
for (fsp_index = 0U; fsp_index < 3U; fsp_index++) {
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
init_val = mmio_read_32(fsp_init_reg[fsp_index][i]);
|
||||
mr_value[fsp_index][2*i] = init_val >> 16;
|
||||
mr_value[fsp_index][2*i + 1] = init_val & 0xFFFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore the ddrc configs */
|
||||
void dram_umctl2_init(struct dram_timing_info *timing)
|
||||
{
|
||||
struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0U; i < timing->ddrc_cfg_num; i++) {
|
||||
mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val);
|
||||
ddrc_cfg++;
|
||||
}
|
||||
|
||||
/* set the default fsp to P0 */
|
||||
mmio_write_32(DDRC_MSTR2(0), 0x0);
|
||||
}
|
||||
|
||||
/* Restore the dram PHY config */
|
||||
void dram_phy_init(struct dram_timing_info *timing)
|
||||
{
|
||||
struct dram_cfg_param *cfg = timing->ddrphy_cfg;
|
||||
unsigned int i;
|
||||
|
||||
/* Restore the PHY init config */
|
||||
cfg = timing->ddrphy_cfg;
|
||||
for (i = 0U; i < timing->ddrphy_cfg_num; i++) {
|
||||
dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
|
||||
cfg++;
|
||||
}
|
||||
|
||||
/* Restore the DDR PHY CSRs */
|
||||
cfg = timing->ddrphy_trained_csr;
|
||||
for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) {
|
||||
dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
|
||||
cfg++;
|
||||
}
|
||||
|
||||
/* Load the PIE image */
|
||||
cfg = timing->ddrphy_pie;
|
||||
for (i = 0U; i < timing->ddrphy_pie_num; i++) {
|
||||
dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
|
||||
cfg++;
|
||||
}
|
||||
}
|
||||
|
||||
/* EL3 SGI-8 IPI handler for DDR Dynamic frequency scaling */
|
||||
static uint64_t waiting_dvfs(uint32_t id, uint32_t flags,
|
||||
void *handle, void *cookie)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr_el1();
|
||||
unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
uint32_t irq;
|
||||
|
||||
irq = plat_ic_acknowledge_interrupt();
|
||||
if (irq < 1022U) {
|
||||
plat_ic_end_of_interrupt(irq);
|
||||
}
|
||||
|
||||
/* set the WFE done status */
|
||||
spin_lock(&dfs_lock);
|
||||
wfe_done |= (1 << cpu_id * 8);
|
||||
dsb();
|
||||
spin_unlock(&dfs_lock);
|
||||
|
||||
while (1) {
|
||||
/* ddr frequency change done */
|
||||
if (!wait_ddrc_hwffc_done)
|
||||
break;
|
||||
|
||||
wfe();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_info_init(unsigned long dram_timing_base)
|
||||
{
|
||||
uint32_t ddrc_mstr, current_fsp;
|
||||
unsigned int idx = 0;
|
||||
uint32_t flags = 0;
|
||||
uint32_t rc;
|
||||
unsigned int i;
|
||||
|
||||
/* Get the dram type & rank */
|
||||
ddrc_mstr = mmio_read_32(DDRC_MSTR(0));
|
||||
|
||||
dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK;
|
||||
dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK;
|
||||
|
||||
/* Get current fsp info */
|
||||
current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf;
|
||||
dram_info.boot_fsp = current_fsp;
|
||||
dram_info.current_fsp = current_fsp;
|
||||
|
||||
get_mr_values(dram_info.mr_table);
|
||||
|
||||
dram_info.timing_info = (struct dram_timing_info *)dram_timing_base;
|
||||
|
||||
/* get the num of supported fsp */
|
||||
for (i = 0U; i < 4U; ++i) {
|
||||
if (!dram_info.timing_info->fsp_table[i]) {
|
||||
break;
|
||||
}
|
||||
idx = i;
|
||||
}
|
||||
dram_info.num_fsp = i;
|
||||
|
||||
/* check if has bypass mode support */
|
||||
if (dram_info.timing_info->fsp_table[idx] < 666) {
|
||||
dram_info.bypass_mode = true;
|
||||
} else {
|
||||
dram_info.bypass_mode = false;
|
||||
}
|
||||
|
||||
/* Register the EL3 handler for DDR DVFS */
|
||||
set_interrupt_rm_flag(flags, NON_SECURE);
|
||||
rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags);
|
||||
if (rc != 0) {
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* For each freq return the following info:
|
||||
*
|
||||
* r1: data rate
|
||||
* r2: 1 + dram_core parent
|
||||
* r3: 1 + dram_alt parent index
|
||||
* r4: 1 + dram_apb parent index
|
||||
*
|
||||
* The parent indices can be used by an OS who manages source clocks to enabled
|
||||
* them ahead of the switch.
|
||||
*
|
||||
* A parent value of "0" means "don't care".
|
||||
*
|
||||
* Current implementation of freq switch is hardcoded in
|
||||
* plat/imx/common/imx8m/clock.c but in theory this can be enhanced to support
|
||||
* a wide variety of rates.
|
||||
*/
|
||||
int dram_dvfs_get_freq_info(void *handle, u_register_t index)
|
||||
{
|
||||
switch (index) {
|
||||
case 0:
|
||||
SMC_RET4(handle, dram_info.timing_info->fsp_table[0],
|
||||
1, 0, 5);
|
||||
case 1:
|
||||
if (!dram_info.bypass_mode) {
|
||||
SMC_RET4(handle, dram_info.timing_info->fsp_table[1],
|
||||
1, 0, 0);
|
||||
}
|
||||
SMC_RET4(handle, dram_info.timing_info->fsp_table[1],
|
||||
2, 2, 4);
|
||||
case 2:
|
||||
if (!dram_info.bypass_mode) {
|
||||
SMC_RET4(handle, dram_info.timing_info->fsp_table[2],
|
||||
1, 0, 0);
|
||||
}
|
||||
SMC_RET4(handle, dram_info.timing_info->fsp_table[2],
|
||||
2, 3, 3);
|
||||
case 3:
|
||||
SMC_RET4(handle, dram_info.timing_info->fsp_table[3],
|
||||
1, 0, 0);
|
||||
default:
|
||||
SMC_RET1(handle, -3);
|
||||
}
|
||||
}
|
||||
|
||||
int dram_dvfs_handler(uint32_t smc_fid, void *handle,
|
||||
u_register_t x1, u_register_t x2, u_register_t x3)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr_el1();
|
||||
unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
unsigned int fsp_index = x1;
|
||||
uint32_t online_cores = x2;
|
||||
|
||||
if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_COUNT) {
|
||||
SMC_RET1(handle, dram_info.num_fsp);
|
||||
} else if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_INFO) {
|
||||
return dram_dvfs_get_freq_info(handle, x2);
|
||||
} else if (x1 < 4) {
|
||||
wait_ddrc_hwffc_done = true;
|
||||
dsb();
|
||||
|
||||
/* trigger the SGI IPI to info other cores */
|
||||
for (int i = 0; i < PLATFORM_CORE_COUNT; i++) {
|
||||
if (cpu_id != i && (online_cores & (0x1 << (i * 8)))) {
|
||||
plat_ic_raise_el3_sgi(0x8, i);
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure all the core in WFE */
|
||||
online_cores &= ~(0x1 << (cpu_id * 8));
|
||||
while (1) {
|
||||
if (online_cores == wfe_done) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* flush the L1/L2 cache */
|
||||
dcsw_op_all(DCCSW);
|
||||
|
||||
if (dram_info.dram_type == DDRC_LPDDR4) {
|
||||
lpddr4_swffc(&dram_info, dev_fsp, fsp_index);
|
||||
dev_fsp = (~dev_fsp) & 0x1;
|
||||
} else if (dram_info.dram_type == DDRC_DDR4) {
|
||||
ddr4_swffc(&dram_info, fsp_index);
|
||||
}
|
||||
|
||||
dram_info.current_fsp = fsp_index;
|
||||
wait_ddrc_hwffc_done = false;
|
||||
wfe_done = 0;
|
||||
dsb();
|
||||
sev();
|
||||
isb();
|
||||
}
|
||||
|
||||
SMC_RET1(handle, 0);
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright 2018-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <dram.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000)
|
||||
#define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004)
|
||||
|
||||
#define PU_PGC_UP_TRG 0xf8
|
||||
#define PU_PGC_DN_TRG 0x104
|
||||
#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC)
|
||||
#define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800)
|
||||
#define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000)
|
||||
#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n))
|
||||
#define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n))
|
||||
|
||||
#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50)
|
||||
|
||||
#define DBGCAM_EMPTY 0x36000000
|
||||
|
||||
void dram_enter_retention(void)
|
||||
{
|
||||
/* Wait DBGCAM to be empty */
|
||||
while (mmio_read_32(DDRC_DBGCAM(0)) != DBGCAM_EMPTY) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Block AXI ports from taking anymore transactions */
|
||||
mmio_write_32(DDRC_PCTRL_0(0), 0x0);
|
||||
/* Wait until all AXI ports are idle */
|
||||
while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Enter self refresh */
|
||||
mmio_write_32(DDRC_PWRCTL(0), 0xaa);
|
||||
|
||||
/* LPDDR4 & DDR4/DDR3L need to check different status */
|
||||
if (dram_info.dram_type == DDRC_LPDDR4) {
|
||||
while (0x223 != (mmio_read_32(DDRC_STAT(0)) & 0x33f)) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
while (0x23 != (mmio_read_32(DDRC_STAT(0)) & 0x3f)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x0);
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x0);
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x1f00);
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x1f20);
|
||||
|
||||
while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) {
|
||||
;
|
||||
}
|
||||
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x1f00);
|
||||
/* wait DFISTAT.dfi_init_complete to 1 */
|
||||
while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) {
|
||||
;
|
||||
}
|
||||
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x1);
|
||||
|
||||
/* should check PhyInLP3 pub reg */
|
||||
dwc_ddrphy_apb_wr(0xd0000, 0x0);
|
||||
if (!(dwc_ddrphy_apb_rd(0x90028) & 0x1)) {
|
||||
INFO("PhyInLP3 = 1\n");
|
||||
}
|
||||
dwc_ddrphy_apb_wr(0xd0000, 0x1);
|
||||
|
||||
#if defined(PLAT_imx8mq)
|
||||
/* pwrdnreqn_async adbm/adbs of ddr */
|
||||
mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1));
|
||||
while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) {
|
||||
;
|
||||
}
|
||||
mmio_setbits_32(GPC_PU_PWRHSK, BIT(1));
|
||||
#else
|
||||
/* pwrdnreqn_async adbm/adbs of ddr */
|
||||
mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2));
|
||||
while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) {
|
||||
;
|
||||
}
|
||||
mmio_setbits_32(GPC_PU_PWRHSK, BIT(2));
|
||||
#endif
|
||||
/* remove PowerOk */
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F000008);
|
||||
|
||||
mmio_write_32(CCM_CCGR(5), 0);
|
||||
mmio_write_32(CCM_SRC_CTRL(15), 2);
|
||||
|
||||
/* enable the phy iso */
|
||||
mmio_setbits_32(IMX_GPC_BASE + 0xd40, 1);
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5));
|
||||
|
||||
VERBOSE("dram enter retention\n");
|
||||
}
|
||||
|
||||
void dram_exit_retention(void)
|
||||
{
|
||||
VERBOSE("dram exit retention\n");
|
||||
/* assert all reset */
|
||||
#if defined(PLAT_imx8mq)
|
||||
mmio_write_32(SRC_DDR2_RCR, 0x8F000003);
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F00000F);
|
||||
mmio_write_32(SRC_DDR2_RCR, 0x8F000000);
|
||||
#else
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F00001F);
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F00000F);
|
||||
#endif
|
||||
mmio_write_32(CCM_CCGR(5), 2);
|
||||
mmio_write_32(CCM_SRC_CTRL(15), 2);
|
||||
|
||||
/* disable iso */
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5));
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F000006);
|
||||
|
||||
/* wait dram pll locked */
|
||||
while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) {
|
||||
;
|
||||
}
|
||||
|
||||
/* ddrc re-init */
|
||||
dram_umctl2_init(dram_info.timing_info);
|
||||
|
||||
/*
|
||||
* Skips the DRAM init routine and starts up in selfrefresh mode
|
||||
* Program INIT0.skip_dram_init = 2'b11
|
||||
*/
|
||||
mmio_setbits_32(DDRC_INIT0(0), 0xc0000000);
|
||||
/* Keeps the controller in self-refresh mode */
|
||||
mmio_write_32(DDRC_PWRCTL(0), 0xaa);
|
||||
mmio_write_32(DDRC_DBG1(0), 0x0);
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F000004);
|
||||
mmio_write_32(SRC_DDR1_RCR, 0x8F000000);
|
||||
|
||||
/* before write Dynamic reg, sw_done should be 0 */
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x0);
|
||||
|
||||
#if !PLAT_imx8mn
|
||||
if (dram_info.dram_type == DDRC_LPDDR4) {
|
||||
mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */
|
||||
}
|
||||
#endif /* !PLAT_imx8mn */
|
||||
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x0);
|
||||
|
||||
/* dram phy re-init */
|
||||
dram_phy_init(dram_info.timing_info);
|
||||
|
||||
/* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
|
||||
dwc_ddrphy_apb_wr(0xd0000, 0x0);
|
||||
while (dwc_ddrphy_apb_rd(0x20097)) {
|
||||
;
|
||||
}
|
||||
dwc_ddrphy_apb_wr(0xd0000, 0x1);
|
||||
|
||||
/* before write Dynamic reg, sw_done should be 0 */
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x0);
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x20);
|
||||
/* wait DFISTAT.dfi_init_complete to 1 */
|
||||
while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* clear DFIMISC.dfi_init_start */
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x0);
|
||||
/* set DFIMISC.dfi_init_complete_en */
|
||||
mmio_write_32(DDRC_DFIMISC(0), 0x1);
|
||||
|
||||
/* set SWCTL.sw_done to enable quasi-dynamic register programming */
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x1);
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) {
|
||||
;
|
||||
}
|
||||
|
||||
mmio_write_32(DDRC_PWRCTL(0), 0x88);
|
||||
/* wait STAT to normal state */
|
||||
while (0x1 != (mmio_read_32(DDRC_STAT(0)) & 0x7)) {
|
||||
;
|
||||
}
|
||||
|
||||
mmio_write_32(DDRC_PCTRL_0(0), 0x1);
|
||||
/* dis_auto-refresh is set to 0 */
|
||||
mmio_write_32(DDRC_RFSHCTL3(0), 0x0);
|
||||
|
||||
/* should check PhyInLP3 pub reg */
|
||||
dwc_ddrphy_apb_wr(0xd0000, 0x0);
|
||||
if (!(dwc_ddrphy_apb_rd(0x90028) & 0x1)) {
|
||||
VERBOSE("PHYInLP3 = 0\n");
|
||||
}
|
||||
dwc_ddrphy_apb_wr(0xd0000, 0x1);
|
||||
}
|
||||
@@ -0,0 +1,292 @@
|
||||
/*
|
||||
* Copyright 2018-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <dram.h>
|
||||
|
||||
static void lpddr4_mr_write(uint32_t mr_rank, uint32_t mr_addr, uint32_t mr_data)
|
||||
{
|
||||
/*
|
||||
* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there
|
||||
* is no outstanding MR transaction. No
|
||||
* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1.
|
||||
*/
|
||||
while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1)
|
||||
;
|
||||
|
||||
/*
|
||||
* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr,
|
||||
* MRCTRL0.mr_rank and (for MRWs)
|
||||
* MRCTRL1.mr_data to define the MR transaction.
|
||||
*/
|
||||
mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4));
|
||||
mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
|
||||
mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31));
|
||||
}
|
||||
|
||||
void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp,
|
||||
unsigned int fsp_index)
|
||||
|
||||
{
|
||||
uint32_t mr, emr, emr2, emr3;
|
||||
uint32_t mr11, mr12, mr22, mr14;
|
||||
uint32_t val;
|
||||
uint32_t derate_backup[3];
|
||||
uint32_t (*mr_data)[8];
|
||||
|
||||
/* 1. program targetd UMCTL2_REGS_FREQ1/2/3,already done, skip it. */
|
||||
|
||||
/* 2. MR13.FSP-WR=1, MRW to update MR registers */
|
||||
mr_data = info->mr_table;
|
||||
mr = mr_data[fsp_index][0];
|
||||
emr = mr_data[fsp_index][1];
|
||||
emr2 = mr_data[fsp_index][2];
|
||||
emr3 = mr_data[fsp_index][3];
|
||||
mr11 = mr_data[fsp_index][4];
|
||||
mr12 = mr_data[fsp_index][5];
|
||||
mr22 = mr_data[fsp_index][6];
|
||||
mr14 = mr_data[fsp_index][7];
|
||||
|
||||
val = (init_fsp == 1) ? 0x2 << 6 : 0x1 << 6;
|
||||
emr3 = (emr3 & 0x003f) | val | 0x0d00;
|
||||
|
||||
/* 12. set PWRCTL.selfref_en=0 */
|
||||
mmio_clrbits_32(DDRC_PWRCTL(0), 0xf);
|
||||
|
||||
/* It is more safe to config it here */
|
||||
mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1);
|
||||
|
||||
lpddr4_mr_write(3, 13, emr3);
|
||||
lpddr4_mr_write(3, 1, mr);
|
||||
lpddr4_mr_write(3, 2, emr);
|
||||
lpddr4_mr_write(3, 3, emr2);
|
||||
lpddr4_mr_write(3, 11, mr11);
|
||||
lpddr4_mr_write(3, 12, mr12);
|
||||
lpddr4_mr_write(3, 14, mr14);
|
||||
lpddr4_mr_write(3, 22, mr22);
|
||||
|
||||
do {
|
||||
val = mmio_read_32(DDRC_MRSTAT(0));
|
||||
} while (val & 0x1);
|
||||
|
||||
/* 3. disable AXI ports */
|
||||
mmio_write_32(DDRC_PCTRL_0(0), 0x0);
|
||||
|
||||
/* 4.Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_PSTAT(0));
|
||||
} while (val != 0);
|
||||
|
||||
/* 6.disable SBRCTL.scrub_en, skip if never enable it */
|
||||
/* 7.poll SBRSTAT.scrub_busy Q2: should skip phy master if never enable it */
|
||||
/* Disable phy master */
|
||||
#ifdef DFILP_SPT
|
||||
/* 8. disable DFI LP */
|
||||
/* DFILPCFG0.dfi_lp_en_sr */
|
||||
val = mmio_read_32(DDRC_DFILPCFG0(0));
|
||||
if (val & 0x100) {
|
||||
mmio_write_32(DDRC_DFILPCFG0(0), 0x0);
|
||||
do {
|
||||
val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack
|
||||
val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode
|
||||
} while (((val & 0x2) == 0x2) && ((val2 & 0x7) == 3));
|
||||
}
|
||||
#endif
|
||||
/* 9. wait until in normal or power down states */
|
||||
do {
|
||||
/* operating_mode */
|
||||
val = mmio_read_32(DDRC_STAT(0));
|
||||
} while (((val & 0x7) != 1) && ((val & 0x7) != 2));
|
||||
|
||||
/* 10. Disable automatic derating: derate_enable */
|
||||
val = mmio_read_32(DDRC_DERATEEN(0));
|
||||
derate_backup[0] = val;
|
||||
mmio_clrbits_32(DDRC_DERATEEN(0), 0x1);
|
||||
|
||||
val = mmio_read_32(DDRC_FREQ1_DERATEEN(0));
|
||||
derate_backup[1] = val;
|
||||
mmio_clrbits_32(DDRC_FREQ1_DERATEEN(0), 0x1);
|
||||
|
||||
val = mmio_read_32(DDRC_FREQ2_DERATEEN(0));
|
||||
derate_backup[2] = val;
|
||||
mmio_clrbits_32(DDRC_FREQ2_DERATEEN(0), 0x1);
|
||||
|
||||
/* 11. disable automatic ZQ calibration */
|
||||
mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31));
|
||||
mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31));
|
||||
mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31));
|
||||
|
||||
/* 12. set PWRCTL.selfref_en=0 */
|
||||
mmio_clrbits_32(DDRC_PWRCTL(0), 0x1);
|
||||
|
||||
/* 13.Poll STAT.operating_mode is in "Normal" (001) or "Power-down" (010) */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_STAT(0));
|
||||
} while (((val & 0x7) != 1) && ((val & 0x7) != 2));
|
||||
|
||||
/* 14-15. trigger SW SR */
|
||||
/* bit 5: selfref_sw, bit 6: stay_in_selfref */
|
||||
mmio_setbits_32(DDRC_PWRCTL(0), 0x60);
|
||||
|
||||
/* 16. Poll STAT.selfref_state in "Self Refresh 1" */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_STAT(0));
|
||||
} while ((val & 0x300) != 0x100);
|
||||
|
||||
/* 17. disable dq */
|
||||
mmio_setbits_32(DDRC_DBG1(0), 0x1);
|
||||
|
||||
/* 18. Poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_DBGCAM(0));
|
||||
val &= 0x30000000;
|
||||
} while (val != 0x30000000);
|
||||
|
||||
/* 19. change MR13.FSP-OP to new FSP and MR13.VRCG to high current */
|
||||
emr3 = (((~init_fsp) & 0x1) << 7) | (0x1 << 3) | (emr3 & 0x0077) | 0x0d00;
|
||||
lpddr4_mr_write(3, 13, emr3);
|
||||
|
||||
/* 20. enter SR Power Down */
|
||||
mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x20);
|
||||
|
||||
/* 21. Poll STAT.selfref_state is in "SR Power down" */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_STAT(0));
|
||||
} while ((val & 0x300) != 0x200);
|
||||
|
||||
/* 22. set dfi_init_complete_en = 0 */
|
||||
|
||||
/* 23. switch clock */
|
||||
/* set SWCTL.dw_done to 0 */
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x0000);
|
||||
|
||||
/* 24. program frequency mode=1(bit 29), target_frequency=target_freq (bit 29) */
|
||||
mmio_write_32(DDRC_MSTR2(0), fsp_index);
|
||||
|
||||
/* 25. DBICTL for FSP-OP[1], skip it if never enable it */
|
||||
|
||||
/* 26.trigger initialization in the PHY */
|
||||
|
||||
/* Q3: if refresh level is updated, then should program */
|
||||
/* as updating refresh, need to toggle refresh_update_level signal */
|
||||
val = mmio_read_32(DDRC_RFSHCTL3(0));
|
||||
val = val ^ 0x2;
|
||||
mmio_write_32(DDRC_RFSHCTL3(0), val);
|
||||
|
||||
/* Q4: only for legacy PHY, so here can skipped */
|
||||
|
||||
/* dfi_frequency -> 0x1x */
|
||||
val = mmio_read_32(DDRC_DFIMISC(0));
|
||||
val &= 0xFE;
|
||||
val |= (fsp_index << 8);
|
||||
mmio_write_32(DDRC_DFIMISC(0), val);
|
||||
/* dfi_init_start */
|
||||
val |= 0x20;
|
||||
mmio_write_32(DDRC_DFIMISC(0), val);
|
||||
|
||||
/* polling dfi_init_complete de-assert */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_DFISTAT(0));
|
||||
} while ((val & 0x1) == 0x1);
|
||||
|
||||
/* change the clock frequency */
|
||||
dram_clock_switch(info->timing_info->fsp_table[fsp_index], info->bypass_mode);
|
||||
|
||||
/* dfi_init_start de-assert */
|
||||
mmio_clrbits_32(DDRC_DFIMISC(0), 0x20);
|
||||
|
||||
/* polling dfi_init_complete re-assert */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_DFISTAT(0));
|
||||
} while ((val & 0x1) == 0x0);
|
||||
|
||||
/* 27. set ZQCTL0.dis_srx_zqcl = 1 */
|
||||
if (fsp_index == 0) {
|
||||
mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30));
|
||||
} else if (fsp_index == 1) {
|
||||
mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30));
|
||||
} else {
|
||||
mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30));
|
||||
}
|
||||
|
||||
/* 28,29. exit "self refresh power down" to stay "self refresh 2" */
|
||||
/* exit SR power down */
|
||||
mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x40);
|
||||
/* 30. Poll STAT.selfref_state in "Self refresh 2" */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_STAT(0));
|
||||
} while ((val & 0x300) != 0x300);
|
||||
|
||||
/* 31. change MR13.VRCG to normal */
|
||||
emr3 = (emr3 & 0x00f7) | 0x0d00;
|
||||
lpddr4_mr_write(3, 13, emr3);
|
||||
|
||||
/* enable PHY master */
|
||||
mmio_write_32(DDRC_DFIPHYMSTR(0), 0x1);
|
||||
|
||||
/* 32. issue ZQ if required: zq_calib_short, bit 4 */
|
||||
/* polling zq_calib_short_busy */
|
||||
mmio_setbits_32(DDRC_DBGCMD(0), 0x10);
|
||||
|
||||
do {
|
||||
val = mmio_read_32(DDRC_DBGSTAT(0));
|
||||
} while ((val & 0x10) != 0x0);
|
||||
|
||||
/* 33. Reset ZQCTL0.dis_srx_zqcl=0 */
|
||||
if (fsp_index == 1)
|
||||
mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30));
|
||||
else if (fsp_index == 2)
|
||||
mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30));
|
||||
else
|
||||
mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(30));
|
||||
|
||||
/* set SWCTL.dw_done to 1 and poll SWSTAT.sw_done_ack=1 */
|
||||
mmio_write_32(DDRC_SWCTL(0), 0x1);
|
||||
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_SWSTAT(0));
|
||||
} while ((val & 0x1) == 0x0);
|
||||
|
||||
/* 34. set PWRCTL.stay_in_selfreh=0, exit SR */
|
||||
mmio_clrbits_32(DDRC_PWRCTL(0), 0x40);
|
||||
/* wait tXSR */
|
||||
|
||||
/* 35. Poll STAT.selfref_state in "Idle" */
|
||||
do {
|
||||
val = mmio_read_32(DDRC_STAT(0));
|
||||
} while ((val & 0x300) != 0x0);
|
||||
|
||||
#ifdef DFILP_SPT
|
||||
/* 36. restore dfi_lp.dfi_lp_en_sr */
|
||||
mmio_setbits_32(DDRC_DFILPCFG0(0), BIT(8));
|
||||
#endif
|
||||
|
||||
/* 37. re-enable CAM: dis_dq */
|
||||
mmio_clrbits_32(DDRC_DBG1(0), 0x1);
|
||||
|
||||
/* 38. re-enable automatic SR: selfref_en */
|
||||
mmio_setbits_32(DDRC_PWRCTL(0), 0x1);
|
||||
|
||||
/* 39. re-enable automatic ZQ: dis_auto_zq=0 */
|
||||
/* disable automatic ZQ calibration */
|
||||
if (fsp_index == 1)
|
||||
mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31));
|
||||
else if (fsp_index == 2)
|
||||
mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31));
|
||||
else
|
||||
mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(31));
|
||||
/* 40. re-emable automatic derating: derate_enable */
|
||||
mmio_write_32(DDRC_DERATEEN(0), derate_backup[0]);
|
||||
mmio_write_32(DDRC_FREQ1_DERATEEN(0), derate_backup[1]);
|
||||
mmio_write_32(DDRC_FREQ2_DERATEEN(0), derate_backup[2]);
|
||||
|
||||
/* 41. write 1 to PCTRL.port_en */
|
||||
mmio_write_32(DDRC_PCTRL_0(0), 0x1);
|
||||
|
||||
/* 42. enable SBRCTL.scrub_en, skip if never enable it */
|
||||
}
|
||||
@@ -0,0 +1,308 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
#include <gpc.h>
|
||||
#include <imx8m_psci.h>
|
||||
#include <plat_imx8.h>
|
||||
|
||||
#define MAX_PLL_NUM U(10)
|
||||
|
||||
static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, };
|
||||
|
||||
DEFINE_BAKERY_LOCK(gpc_lock);
|
||||
|
||||
#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
|
||||
|
||||
#pragma weak imx_set_cpu_pwr_off
|
||||
#pragma weak imx_set_cpu_pwr_on
|
||||
#pragma weak imx_set_cpu_lpm
|
||||
#pragma weak imx_set_cluster_powerdown
|
||||
|
||||
void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint)
|
||||
{
|
||||
uint64_t temp_base;
|
||||
|
||||
temp_base = (uint64_t) sec_entrypoint;
|
||||
temp_base >>= 2;
|
||||
|
||||
mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3),
|
||||
((uint32_t)(temp_base >> 22) & 0xffff));
|
||||
mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4,
|
||||
((uint32_t)temp_base & 0x003fffff));
|
||||
}
|
||||
|
||||
void imx_set_cpu_pwr_off(unsigned int core_id)
|
||||
{
|
||||
|
||||
bakery_lock_get(&gpc_lock);
|
||||
|
||||
/* enable the wfi power down of the core */
|
||||
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));
|
||||
|
||||
bakery_lock_release(&gpc_lock);
|
||||
|
||||
/* assert the pcg pcr bit of the core */
|
||||
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
|
||||
}
|
||||
|
||||
void imx_set_cpu_pwr_on(unsigned int core_id)
|
||||
{
|
||||
bakery_lock_get(&gpc_lock);
|
||||
|
||||
/* clear the wfi power down bit of the core */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));
|
||||
|
||||
bakery_lock_release(&gpc_lock);
|
||||
|
||||
/* assert the ncpuporeset */
|
||||
mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));
|
||||
/* assert the pcg pcr bit of the core */
|
||||
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
|
||||
/* sw power up the core */
|
||||
mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id));
|
||||
|
||||
/* wait for the power up finished */
|
||||
while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0)
|
||||
;
|
||||
|
||||
/* deassert the pcg pcr bit of the core */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
|
||||
/* deassert the ncpuporeset */
|
||||
mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));
|
||||
}
|
||||
|
||||
void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
|
||||
{
|
||||
bakery_lock_get(&gpc_lock);
|
||||
|
||||
if (pdn) {
|
||||
/* enable the core WFI PDN & IRQ PUP */
|
||||
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
|
||||
COREx_IRQ_WUP(core_id));
|
||||
/* assert the pcg pcr bit of the core */
|
||||
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
|
||||
} else {
|
||||
/* disbale CORE WFI PDN & IRQ PUP */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
|
||||
COREx_IRQ_WUP(core_id));
|
||||
/* deassert the pcg pcr bit of the core */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
|
||||
}
|
||||
|
||||
bakery_lock_release(&gpc_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* the plat and noc can only be power up & down by slot method,
|
||||
* slot0: plat power down; slot1: noc power down; slot2: noc power up;
|
||||
* slot3: plat power up. plat's pup&pdn ack is used by default. if
|
||||
* noc is config to power down, then noc's pdn ack should be used.
|
||||
*/
|
||||
static void imx_a53_plat_slot_config(bool pdn)
|
||||
{
|
||||
if (pdn) {
|
||||
mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL);
|
||||
mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL);
|
||||
mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK |
|
||||
A53_PLAT_PUP_ACK);
|
||||
mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1);
|
||||
} else {
|
||||
mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL);
|
||||
mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL);
|
||||
mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |
|
||||
A53_DUMMY_PDN_ACK);
|
||||
mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
void imx_set_cluster_standby(bool enter)
|
||||
{
|
||||
/*
|
||||
* Enable BIT 6 of A53 AD register to make sure system
|
||||
* don't enter LPM mode.
|
||||
*/
|
||||
if (enter)
|
||||
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6));
|
||||
else
|
||||
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6));
|
||||
}
|
||||
|
||||
/* i.mx8mq need to override it */
|
||||
void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
if (!is_local_state_run(power_state)) {
|
||||
/* config C0~1's LPM, enable a53 clock off in LPM */
|
||||
mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM,
|
||||
LPM_MODE(power_state));
|
||||
/* config C2-3's LPM */
|
||||
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state));
|
||||
|
||||
/* enable PLAT/SCU power down */
|
||||
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
|
||||
val &= ~EN_L2_WFI_PDN;
|
||||
/* L2 cache memory is on in WAIT mode */
|
||||
if (is_local_state_off(power_state)) {
|
||||
val |= (L2PGE | EN_PLAT_PDN);
|
||||
imx_a53_plat_slot_config(true);
|
||||
}
|
||||
|
||||
mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
|
||||
} else {
|
||||
/* clear the slot and ack for cluster power down */
|
||||
imx_a53_plat_slot_config(false);
|
||||
/* reverse the cluster level setting */
|
||||
mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM);
|
||||
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf);
|
||||
|
||||
/* clear PLAT/SCU power down */
|
||||
mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN),
|
||||
EN_L2_WFI_PDN);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned int n = id >> ISENABLER_SHIFT;
|
||||
|
||||
return mmio_read_32(base + GICD_ISENABLER + (n << 2));
|
||||
}
|
||||
|
||||
/*
|
||||
* gic's clock will be gated in system suspend, so gic has no ability to
|
||||
* to wakeup the system, we need to config the imr based on the irq
|
||||
* enable status in gic, then gpc will monitor the wakeup irq
|
||||
*/
|
||||
void imx_set_sys_wakeup(unsigned int last_core, bool pdn)
|
||||
{
|
||||
uint32_t irq_mask;
|
||||
uintptr_t gicd_base = PLAT_GICD_BASE;
|
||||
|
||||
if (pdn)
|
||||
mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core),
|
||||
IRQ_SRC_A53_WUP);
|
||||
else
|
||||
mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP,
|
||||
A53_CORE_WUP_SRC(last_core));
|
||||
|
||||
/* clear last core's IMR based on GIC's mask setting */
|
||||
for (int i = 0; i < IRQ_IMR_NUM; i++) {
|
||||
if (pdn)
|
||||
/* set the wakeup irq base GIC */
|
||||
irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1));
|
||||
else
|
||||
irq_mask = IMR_MASK_ALL;
|
||||
|
||||
mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4,
|
||||
irq_mask);
|
||||
}
|
||||
}
|
||||
|
||||
#pragma weak imx_noc_slot_config
|
||||
/*
|
||||
* this function only need to be override by platform
|
||||
* that support noc power down, for example: imx8mm.
|
||||
* otherwize, keep it empty.
|
||||
*/
|
||||
void imx_noc_slot_config(bool pdn)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/* this is common for all imx8m soc */
|
||||
void imx_set_sys_lpm(unsigned int last_core, bool retention)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = mmio_read_32(IMX_GPC_BASE + SLPCR);
|
||||
val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
|
||||
SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE);
|
||||
|
||||
if (retention)
|
||||
val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
|
||||
SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE);
|
||||
|
||||
mmio_write_32(IMX_GPC_BASE + SLPCR, val);
|
||||
|
||||
/* config the noc power down */
|
||||
imx_noc_slot_config(retention);
|
||||
|
||||
/* config wakeup irqs' mask in gpc */
|
||||
imx_set_sys_wakeup(last_core, retention);
|
||||
}
|
||||
|
||||
void imx_set_rbc_count(void)
|
||||
{
|
||||
mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN |
|
||||
(0x8 << SLPCR_RBC_COUNT_SHIFT));
|
||||
}
|
||||
|
||||
void imx_clear_rbc_count(void)
|
||||
{
|
||||
mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN |
|
||||
(0x3f << SLPCR_RBC_COUNT_SHIFT));
|
||||
}
|
||||
|
||||
struct pll_override {
|
||||
uint32_t reg;
|
||||
uint32_t override_mask;
|
||||
};
|
||||
|
||||
struct pll_override pll[MAX_PLL_NUM] = {
|
||||
{.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), },
|
||||
{.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), },
|
||||
{.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), },
|
||||
{.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), },
|
||||
{.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), },
|
||||
{.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), },
|
||||
{.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), },
|
||||
{.reg = 0x94, .override_mask = 0x5555500, },
|
||||
{.reg = 0x104, .override_mask = 0x5555500, },
|
||||
{.reg = 0x114, .override_mask = 0x500, },
|
||||
};
|
||||
|
||||
#define PLL_BYPASS BIT(4)
|
||||
void imx_anamix_override(bool enter)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/*
|
||||
* bypass all the plls & enable the override bit before
|
||||
* entering DSM mode.
|
||||
*/
|
||||
for (i = 0U; i < MAX_PLL_NUM; i++) {
|
||||
if (enter) {
|
||||
mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS);
|
||||
mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask);
|
||||
} else {
|
||||
mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS);
|
||||
mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3)
|
||||
{
|
||||
switch (x1) {
|
||||
case FSL_SIP_CONFIG_GPC_PM_DOMAIN:
|
||||
imx_gpc_pm_domain_enable(x2, x3);
|
||||
break;
|
||||
default:
|
||||
return SMC_UNK;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022 NXP. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <imx8m_caam.h>
|
||||
|
||||
#define HAB_JR0_DID U(0x8011)
|
||||
|
||||
void imx8m_caam_init(void)
|
||||
{
|
||||
uint32_t sm_cmd;
|
||||
|
||||
/* Dealloc part 0 and 2 with current DID */
|
||||
sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
|
||||
mmio_write_32(SM_CMD, sm_cmd);
|
||||
|
||||
sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
|
||||
mmio_write_32(SM_CMD, sm_cmd);
|
||||
|
||||
/* config CAAM JRaMID set MID to Cortex A */
|
||||
if (mmio_read_32(CAAM_JR0MID) == HAB_JR0_DID) {
|
||||
NOTICE("Do not release JR0 to NS as it can be used by HAB\n");
|
||||
} else {
|
||||
mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
|
||||
}
|
||||
|
||||
mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
|
||||
mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
|
||||
|
||||
/* Alloc partition 0 writing SMPO and SMAGs */
|
||||
mmio_write_32(SM_P0_PERM, 0xff);
|
||||
mmio_write_32(SM_P0_SMAG2, 0xffffffff);
|
||||
mmio_write_32(SM_P0_SMAG1, 0xffffffff);
|
||||
|
||||
/* Allocate page 0 and 1 to partition 0 with DID set */
|
||||
sm_cmd = (0 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
|
||||
SMC_CMD_ALLOC_PAGE);
|
||||
mmio_write_32(SM_CMD, sm_cmd);
|
||||
|
||||
sm_cmd = (1 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
|
||||
SMC_CMD_ALLOC_PAGE);
|
||||
mmio_write_32(SM_CMD, sm_cmd);
|
||||
}
|
||||
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright 2020-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <imx8m_csu.h>
|
||||
|
||||
void imx_csu_init(const struct imx_csu_cfg *csu_cfg)
|
||||
{
|
||||
const struct imx_csu_cfg *csu = csu_cfg;
|
||||
uint32_t val;
|
||||
|
||||
while (csu->type != CSU_INVALID) {
|
||||
switch (csu->type) {
|
||||
case CSU_CSL:
|
||||
val = mmio_read_32(CSLx_REG(csu->idx));
|
||||
if (val & CSLx_LOCK(csu->idx)) {
|
||||
break;
|
||||
}
|
||||
mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx),
|
||||
CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx));
|
||||
break;
|
||||
case CSU_HP:
|
||||
val = mmio_read_32(CSU_HP_REG(csu->idx));
|
||||
if (val & CSU_HP_LOCK(csu->idx)) {
|
||||
break;
|
||||
}
|
||||
mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx),
|
||||
CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx));
|
||||
break;
|
||||
case CSU_SA:
|
||||
val = mmio_read_32(CSU_SA_REG(csu->idx));
|
||||
if (val & CSU_SA_LOCK(csu->idx)) {
|
||||
break;
|
||||
}
|
||||
mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx),
|
||||
CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx));
|
||||
break;
|
||||
case CSU_HPCONTROL:
|
||||
val = mmio_read_32(CSU_HPCONTROL_REG(csu->idx));
|
||||
if (val & CSU_HPCONTROL_LOCK(csu->idx)) {
|
||||
break;
|
||||
}
|
||||
mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx),
|
||||
CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
csu++;
|
||||
}
|
||||
}
|
||||
+201
@@ -0,0 +1,201 @@
|
||||
/*
|
||||
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#if MEASURED_BOOT
|
||||
#include <common/desc_image_load.h>
|
||||
#endif
|
||||
#include <common/fdt_wrappers.h>
|
||||
#include <libfdt.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define DTB_PROP_HW_LOG_ADDR "tpm_event_log_addr"
|
||||
#define DTB_PROP_HW_LOG_SIZE "tpm_event_log_size"
|
||||
|
||||
#if MEASURED_BOOT
|
||||
|
||||
static int imx8m_event_log_fdt_init_overlay(uintptr_t dt_base, int dt_size)
|
||||
{
|
||||
int ret;
|
||||
int offset;
|
||||
void *dtb = (void *)dt_base;
|
||||
|
||||
ret = fdt_create_empty_tree(dtb, dt_size);
|
||||
if (ret < 0) {
|
||||
ERROR("cannot create empty dtb tree: %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
offset = fdt_path_offset(dtb, "/");
|
||||
if (offset < 0) {
|
||||
ERROR("cannot find root of the tree: %s\n",
|
||||
fdt_strerror(offset));
|
||||
return offset;
|
||||
}
|
||||
|
||||
offset = fdt_add_subnode(dtb, offset, "fragment@0");
|
||||
if (offset < 0) {
|
||||
ERROR("cannot add fragment node: %s\n",
|
||||
fdt_strerror(offset));
|
||||
return offset;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_string(dtb, offset, "target-path", "/");
|
||||
if (ret < 0) {
|
||||
ERROR("cannot set target-path property: %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
offset = fdt_add_subnode(dtb, offset, "__overlay__");
|
||||
if (offset < 0) {
|
||||
ERROR("cannot add __overlay__ node: %s\n",
|
||||
fdt_strerror(offset));
|
||||
return ret;
|
||||
}
|
||||
|
||||
offset = fdt_add_subnode(dtb, offset, "tpm_event_log");
|
||||
if (offset < 0) {
|
||||
ERROR("cannot add tpm_event_log node: %s\n",
|
||||
fdt_strerror(offset));
|
||||
return offset;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_string(dtb, offset, "compatible",
|
||||
"arm,tpm_event_log");
|
||||
if (ret < 0) {
|
||||
ERROR("cannot set compatible property: %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_u64(dtb, offset, "tpm_event_log_addr", 0);
|
||||
if (ret < 0) {
|
||||
ERROR("cannot set tpm_event_log_addr property: %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_u32(dtb, offset, "tpm_event_log_size", 0);
|
||||
if (ret < 0) {
|
||||
ERROR("cannot set tpm_event_log_size property: %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write the Event Log address and its size in the DTB.
|
||||
*
|
||||
* This function is supposed to be called only by BL2.
|
||||
*
|
||||
* Returns:
|
||||
* 0 = success
|
||||
* < 0 = error
|
||||
*/
|
||||
static int imx8m_set_event_log_info(uintptr_t config_base,
|
||||
uintptr_t log_addr, size_t log_size)
|
||||
{
|
||||
/* As libfdt uses void *, we can't avoid this cast */
|
||||
void *dtb = (void *)config_base;
|
||||
const char *compatible_tpm = "arm,tpm_event_log";
|
||||
uint64_t base = cpu_to_fdt64(log_addr);
|
||||
uint32_t sz = cpu_to_fdt32(log_size);
|
||||
int err, node;
|
||||
|
||||
err = fdt_open_into(dtb, dtb, PLAT_IMX8M_DTO_MAX_SIZE);
|
||||
if (err < 0) {
|
||||
ERROR("Invalid Device Tree at %p: error %d\n", dtb, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Verify that the DTB is valid, before attempting to write to it,
|
||||
* and get the DTB root node.
|
||||
*/
|
||||
|
||||
/* Check if the pointer to DT is correct */
|
||||
err = fdt_check_header(dtb);
|
||||
if (err < 0) {
|
||||
WARN("Invalid DTB file passed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find the TPM node in device tree.
|
||||
*/
|
||||
node = fdt_node_offset_by_compatible(dtb, -1, compatible_tpm);
|
||||
if (node < 0) {
|
||||
ERROR("The compatible property '%s' not%s", compatible_tpm,
|
||||
" found in the config\n");
|
||||
return node;
|
||||
}
|
||||
|
||||
err = fdt_setprop(dtb, node, DTB_PROP_HW_LOG_ADDR, &base, 8);
|
||||
if (err < 0) {
|
||||
ERROR("Failed to add log addr err %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = fdt_setprop(dtb, node, DTB_PROP_HW_LOG_SIZE, &sz, 4);
|
||||
if (err < 0) {
|
||||
ERROR("Failed to add log addr err %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = fdt_pack(dtb);
|
||||
if (err < 0) {
|
||||
ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that the info written to the DTB is visible
|
||||
* to other images.
|
||||
*/
|
||||
flush_dcache_range(config_base, fdt_totalsize(dtb));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function writes the Event Log address and its size
|
||||
* in the QEMU DTB.
|
||||
*
|
||||
* This function is supposed to be called only by BL2.
|
||||
*
|
||||
* Returns:
|
||||
* 0 = success
|
||||
* < 0 = error
|
||||
*/
|
||||
int imx8m_set_nt_fw_info(size_t log_size, uintptr_t *ns_log_addr)
|
||||
{
|
||||
uintptr_t ns_addr;
|
||||
int err;
|
||||
|
||||
assert(ns_log_addr != NULL);
|
||||
|
||||
ns_addr = PLAT_IMX8M_DTO_BASE + PLAT_IMX8M_DTO_MAX_SIZE;
|
||||
|
||||
imx8m_event_log_fdt_init_overlay(PLAT_IMX8M_DTO_BASE,
|
||||
PLAT_IMX8M_DTO_MAX_SIZE);
|
||||
|
||||
/* Write the Event Log address and its size in the DTB */
|
||||
err = imx8m_set_event_log_info(PLAT_IMX8M_DTO_BASE,
|
||||
ns_addr, log_size);
|
||||
|
||||
/* Return Event Log address in Non-secure memory */
|
||||
*ns_log_addr = (err < 0) ? 0UL : ns_addr;
|
||||
return err;
|
||||
}
|
||||
|
||||
#endif /* MEASURED_BOOT */
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/desc_image_load.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
void plat_flush_next_bl_params(void)
|
||||
{
|
||||
flush_bl_params_desc();
|
||||
}
|
||||
|
||||
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||
{
|
||||
return get_bl_load_info_from_mem_params_desc();
|
||||
}
|
||||
|
||||
bl_params_t *plat_get_next_bl_params(void)
|
||||
{
|
||||
return get_next_bl_params_from_mem_params_desc();
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "./include/imx8m_measured_boot.h"
|
||||
#include <drivers/measured_boot/event_log/event_log.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/* Event Log data */
|
||||
static uint8_t event_log[PLAT_IMX_EVENT_LOG_MAX_SIZE];
|
||||
|
||||
/* FVP table with platform specific image IDs, names and PCRs */
|
||||
static const event_log_metadata_t imx8m_event_log_metadata[] = {
|
||||
{ BL31_IMAGE_ID, EVLOG_BL31_STRING, PCR_0 },
|
||||
{ BL32_IMAGE_ID, EVLOG_BL32_STRING, PCR_0 },
|
||||
{ BL32_EXTRA1_IMAGE_ID, EVLOG_BL32_EXTRA1_STRING, PCR_0 },
|
||||
{ BL32_EXTRA2_IMAGE_ID, EVLOG_BL32_EXTRA2_STRING, PCR_0 },
|
||||
{ BL33_IMAGE_ID, EVLOG_BL33_STRING, PCR_0 },
|
||||
{ EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
|
||||
};
|
||||
|
||||
const event_log_metadata_t *plat_event_log_get_metadata(void)
|
||||
{
|
||||
return imx8m_event_log_metadata;
|
||||
}
|
||||
|
||||
int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
|
||||
{
|
||||
/* Calculate image hash and record data in Event Log */
|
||||
int err = event_log_measure_and_record(image_data->image_base,
|
||||
image_data->image_size,
|
||||
image_id);
|
||||
if (err != 0) {
|
||||
ERROR("%s%s image id %u (%i)\n",
|
||||
"Failed to ", "record", image_id, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void bl2_plat_mboot_init(void)
|
||||
{
|
||||
event_log_init(event_log, event_log + sizeof(event_log));
|
||||
event_log_write_header();
|
||||
}
|
||||
|
||||
void bl2_plat_mboot_finish(void)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
/* Event Log address in Non-Secure memory */
|
||||
uintptr_t ns_log_addr;
|
||||
|
||||
/* Event Log filled size */
|
||||
size_t event_log_cur_size;
|
||||
|
||||
event_log_cur_size = event_log_get_cur_size(event_log);
|
||||
|
||||
rc = imx8m_set_nt_fw_info(event_log_cur_size, &ns_log_addr);
|
||||
if (rc != 0) {
|
||||
ERROR("%s(): Unable to update %s_FW_CONFIG\n",
|
||||
__func__, "NT");
|
||||
/*
|
||||
* It is a fatal error because on i.MX U-boot assumes that
|
||||
* a valid event log exists and will use it to record the
|
||||
* measurements into the fTPM.
|
||||
*/
|
||||
panic();
|
||||
}
|
||||
|
||||
/* Copy Event Log to Non-secure memory */
|
||||
(void)memcpy((void *)ns_log_addr, (const void *)event_log,
|
||||
event_log_cur_size);
|
||||
|
||||
/* Ensure that the Event Log is visible in Non-secure memory */
|
||||
flush_dcache_range(ns_log_addr, event_log_cur_size);
|
||||
|
||||
dump_event_log((uint8_t *)event_log, event_log_cur_size);
|
||||
}
|
||||
@@ -0,0 +1,259 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
#include <dram.h>
|
||||
#include <gpc.h>
|
||||
#include <imx8m_psci.h>
|
||||
#include <plat_imx8.h>
|
||||
|
||||
/*
|
||||
* below callback functions need to be override by i.mx8mq,
|
||||
* for other i.mx8m soc, if no special requirement,
|
||||
* reuse below ones.
|
||||
*/
|
||||
#pragma weak imx_validate_power_state
|
||||
#pragma weak imx_domain_suspend
|
||||
#pragma weak imx_domain_suspend_finish
|
||||
#pragma weak imx_get_sys_suspend_power_state
|
||||
|
||||
int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
|
||||
{
|
||||
/* The non-secure entrypoint should be in RAM space */
|
||||
if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
int imx_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core_id;
|
||||
uint64_t base_addr = BL31_START;
|
||||
|
||||
core_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
imx_set_cpu_secure_entry(core_id, base_addr);
|
||||
imx_set_cpu_pwr_on(core_id);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
plat_gic_pcpu_init();
|
||||
plat_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
void imx_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr_el1();
|
||||
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
plat_gic_cpuif_disable();
|
||||
imx_set_cpu_pwr_off(core_id);
|
||||
}
|
||||
|
||||
int imx_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
|
||||
int pwr_type = psci_get_pstate_type(power_state);
|
||||
int state_id = psci_get_pstate_id(power_state);
|
||||
|
||||
if (pwr_lvl > PLAT_MAX_PWR_LVL)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
if (pwr_type == PSTATE_TYPE_STANDBY) {
|
||||
CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
|
||||
CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
|
||||
}
|
||||
|
||||
if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
|
||||
CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
|
||||
CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE;
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
void imx_cpu_standby(plat_local_state_t cpu_state)
|
||||
{
|
||||
dsb();
|
||||
write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
|
||||
isb();
|
||||
|
||||
wfi();
|
||||
|
||||
write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
|
||||
isb();
|
||||
}
|
||||
|
||||
void imx_domain_suspend(const psci_power_state_t *target_state)
|
||||
{
|
||||
uint64_t base_addr = BL31_START;
|
||||
uint64_t mpidr = read_mpidr_el1();
|
||||
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
|
||||
plat_gic_cpuif_disable();
|
||||
imx_set_cpu_secure_entry(core_id, base_addr);
|
||||
imx_set_cpu_lpm(core_id, true);
|
||||
} else {
|
||||
dsb();
|
||||
write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
|
||||
isb();
|
||||
}
|
||||
|
||||
if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
|
||||
imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state));
|
||||
|
||||
if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
|
||||
imx_set_sys_lpm(core_id, true);
|
||||
dram_enter_retention();
|
||||
imx_anamix_override(true);
|
||||
}
|
||||
}
|
||||
|
||||
void imx_domain_suspend_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr_el1();
|
||||
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
|
||||
imx_anamix_override(false);
|
||||
dram_exit_retention();
|
||||
imx_set_sys_lpm(core_id, false);
|
||||
}
|
||||
|
||||
if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) {
|
||||
imx_clear_rbc_count();
|
||||
imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
|
||||
}
|
||||
|
||||
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
|
||||
imx_set_cpu_lpm(core_id, false);
|
||||
plat_gic_cpuif_enable();
|
||||
} else {
|
||||
write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
|
||||
isb();
|
||||
}
|
||||
}
|
||||
|
||||
void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = IMX_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
|
||||
req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
|
||||
}
|
||||
|
||||
static void __dead2 imx_wdog_restart(bool external_reset)
|
||||
{
|
||||
uintptr_t wdog_base = IMX_WDOG_BASE;
|
||||
unsigned int val;
|
||||
|
||||
val = mmio_read_16(wdog_base);
|
||||
/*
|
||||
* Common watchdog init flags, for additional details check
|
||||
* 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
|
||||
*
|
||||
* Initial bit selection:
|
||||
* WDOG_WCR_WDE - Enable the watchdog.
|
||||
*
|
||||
* 0x000E mask is used to keep previous values (that could be set
|
||||
* in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
|
||||
*/
|
||||
val = (val & 0x000E) | WDOG_WCR_WDE;
|
||||
if (external_reset) {
|
||||
/*
|
||||
* To assert WDOG_B (external reset) we have
|
||||
* to set WDA bit 0 (already set in previous step).
|
||||
* SRS bits are required to be set to 1 (no effect on the
|
||||
* system).
|
||||
*/
|
||||
val |= WDOG_WCR_SRS;
|
||||
} else {
|
||||
/*
|
||||
* To assert Software Reset Signal (internal reset) we have
|
||||
* to set SRS bit to 0 (already set in previous step).
|
||||
* SRE bit is required to be set to 1 when used in
|
||||
* conjunction with the Software Reset Signal before
|
||||
* SRS asserton, otherwise SRS bit will just automatically
|
||||
* reset to 1.
|
||||
*
|
||||
* Also we set WDA to 1 (no effect on system).
|
||||
*/
|
||||
val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
|
||||
}
|
||||
|
||||
mmio_write_16(wdog_base, val);
|
||||
|
||||
mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
|
||||
mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa);
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void __dead2 imx_system_reset(void)
|
||||
{
|
||||
#ifdef IMX_WDOG_B_RESET
|
||||
imx_wdog_restart(true);
|
||||
#else
|
||||
imx_wdog_restart(false);
|
||||
#endif
|
||||
}
|
||||
|
||||
int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
|
||||
{
|
||||
imx_wdog_restart(false);
|
||||
|
||||
/*
|
||||
* imx_wdog_restart cannot return (as it's a __dead function),
|
||||
* however imx_system_reset2 has to return some value according
|
||||
* to PSCI v1.1 spec.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __dead2 imx_system_off(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = mmio_read_32(IMX_SNVS_BASE + SNVS_LPCR);
|
||||
val |= SNVS_LPCR_SRTC_ENV | SNVS_LPCR_DP_EN | SNVS_LPCR_TOP;
|
||||
mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, val);
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
|
||||
{
|
||||
/*
|
||||
* before enter WAIT or STOP mode with PLAT(SCU) power down,
|
||||
* rbc count need to be enabled to make sure PLAT is
|
||||
* power down successfully even if the the wakeup IRQ is pending
|
||||
* early before the power down sequence. the RBC counter is
|
||||
* drived by the 32K OSC, so delay 30us to make sure the counter
|
||||
* is really running.
|
||||
*/
|
||||
if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
|
||||
imx_set_rbc_count();
|
||||
udelay(30);
|
||||
}
|
||||
|
||||
while (1)
|
||||
wfi();
|
||||
}
|
||||
@@ -0,0 +1,414 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
#include <lib/smccc.h>
|
||||
#include <platform_def.h>
|
||||
#include <services/std_svc.h>
|
||||
|
||||
#include <gpc.h>
|
||||
#include <imx_sip_svc.h>
|
||||
|
||||
#define MIPI_PWR_REQ BIT(0)
|
||||
#define PCIE_PWR_REQ BIT(1)
|
||||
#define OTG1_PWR_REQ BIT(2)
|
||||
#define OTG2_PWR_REQ BIT(3)
|
||||
#define HSIOMIX_PWR_REQ BIT(4)
|
||||
#define GPU2D_PWR_REQ BIT(6)
|
||||
#define GPUMIX_PWR_REQ BIT(7)
|
||||
#define VPUMIX_PWR_REQ BIT(8)
|
||||
#define GPU3D_PWR_REQ BIT(9)
|
||||
#define DISPMIX_PWR_REQ BIT(10)
|
||||
#define VPU_G1_PWR_REQ BIT(11)
|
||||
#define VPU_G2_PWR_REQ BIT(12)
|
||||
#define VPU_H1_PWR_REQ BIT(13)
|
||||
|
||||
#define HSIOMIX_ADB400_SYNC (0x3 << 5)
|
||||
#define DISPMIX_ADB400_SYNC BIT(7)
|
||||
#define VPUMIX_ADB400_SYNC BIT(8)
|
||||
#define GPU3D_ADB400_SYNC BIT(9)
|
||||
#define GPU2D_ADB400_SYNC BIT(10)
|
||||
#define GPUMIX_ADB400_SYNC BIT(11)
|
||||
#define HSIOMIX_ADB400_ACK (0x3 << 23)
|
||||
#define DISPMIX_ADB400_ACK BIT(25)
|
||||
#define VPUMIX_ADB400_ACK BIT(26)
|
||||
#define GPU3D_ADB400_ACK BIT(27)
|
||||
#define GPU2D_ADB400_ACK BIT(28)
|
||||
#define GPUMIX_ADB400_ACK BIT(29)
|
||||
|
||||
#define MIPI_PGC 0xc00
|
||||
#define PCIE_PGC 0xc40
|
||||
#define OTG1_PGC 0xc80
|
||||
#define OTG2_PGC 0xcc0
|
||||
#define HSIOMIX_PGC 0xd00
|
||||
#define GPU2D_PGC 0xd80
|
||||
#define GPUMIX_PGC 0xdc0
|
||||
#define VPUMIX_PGC 0xe00
|
||||
#define GPU3D_PGC 0xe40
|
||||
#define DISPMIX_PGC 0xe80
|
||||
#define VPU_G1_PGC 0xec0
|
||||
#define VPU_G2_PGC 0xf00
|
||||
#define VPU_H1_PGC 0xf40
|
||||
|
||||
enum pu_domain_id {
|
||||
HSIOMIX,
|
||||
PCIE,
|
||||
OTG1,
|
||||
OTG2,
|
||||
GPUMIX,
|
||||
VPUMIX,
|
||||
VPU_G1,
|
||||
VPU_G2,
|
||||
VPU_H1,
|
||||
DISPMIX,
|
||||
MIPI,
|
||||
/* below two domain only for ATF internal use */
|
||||
GPU2D,
|
||||
GPU3D,
|
||||
MAX_DOMAINS,
|
||||
};
|
||||
|
||||
/* PU domain */
|
||||
static struct imx_pwr_domain pu_domains[] = {
|
||||
IMX_MIX_DOMAIN(HSIOMIX, false),
|
||||
IMX_PD_DOMAIN(PCIE, false),
|
||||
IMX_PD_DOMAIN(OTG1, true),
|
||||
IMX_PD_DOMAIN(OTG2, true),
|
||||
IMX_MIX_DOMAIN(GPUMIX, false),
|
||||
IMX_MIX_DOMAIN(VPUMIX, false),
|
||||
IMX_PD_DOMAIN(VPU_G1, false),
|
||||
IMX_PD_DOMAIN(VPU_G2, false),
|
||||
IMX_PD_DOMAIN(VPU_H1, false),
|
||||
IMX_MIX_DOMAIN(DISPMIX, false),
|
||||
IMX_PD_DOMAIN(MIPI, false),
|
||||
/* below two domain only for ATF internal use */
|
||||
IMX_MIX_DOMAIN(GPU2D, false),
|
||||
IMX_MIX_DOMAIN(GPU3D, false),
|
||||
};
|
||||
|
||||
static unsigned int pu_domain_status;
|
||||
|
||||
#define GPU_RCR 0x40
|
||||
#define VPU_RCR 0x44
|
||||
|
||||
#define VPU_CTL_BASE 0x38330000
|
||||
#define BLK_SFT_RSTN_CSR 0x0
|
||||
#define H1_SFT_RSTN BIT(2)
|
||||
#define G1_SFT_RSTN BIT(1)
|
||||
#define G2_SFT_RSTN BIT(0)
|
||||
|
||||
#define DISP_CTL_BASE 0x32e28000
|
||||
|
||||
void vpu_sft_reset_assert(uint32_t domain_id)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = mmio_read_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR);
|
||||
|
||||
switch (domain_id) {
|
||||
case VPU_G1:
|
||||
val &= ~G1_SFT_RSTN;
|
||||
mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
|
||||
break;
|
||||
case VPU_G2:
|
||||
val &= ~G2_SFT_RSTN;
|
||||
mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
|
||||
break;
|
||||
case VPU_H1:
|
||||
val &= ~H1_SFT_RSTN;
|
||||
mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void vpu_sft_reset_deassert(uint32_t domain_id)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = mmio_read_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR);
|
||||
|
||||
switch (domain_id) {
|
||||
case VPU_G1:
|
||||
val |= G1_SFT_RSTN;
|
||||
mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
|
||||
break;
|
||||
case VPU_G2:
|
||||
val |= G2_SFT_RSTN;
|
||||
mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
|
||||
break;
|
||||
case VPU_H1:
|
||||
val |= H1_SFT_RSTN;
|
||||
mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)
|
||||
{
|
||||
if (domain_id >= MAX_DOMAINS) {
|
||||
return;
|
||||
}
|
||||
|
||||
struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
|
||||
|
||||
if (on) {
|
||||
pu_domain_status |= (1 << domain_id);
|
||||
|
||||
if (domain_id == VPU_G1 || domain_id == VPU_G2 ||
|
||||
domain_id == VPU_H1) {
|
||||
vpu_sft_reset_assert(domain_id);
|
||||
}
|
||||
|
||||
/* HSIOMIX has no PU bit, so skip for it */
|
||||
if (domain_id != HSIOMIX) {
|
||||
/* clear the PGC bit */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
|
||||
|
||||
/* power up the domain */
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);
|
||||
|
||||
/* wait for power request done */
|
||||
while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
if (domain_id == VPU_G1 || domain_id == VPU_G2 ||
|
||||
domain_id == VPU_H1) {
|
||||
vpu_sft_reset_deassert(domain_id);
|
||||
/* dealy for a while to make sure reset done */
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
if (domain_id == GPUMIX) {
|
||||
/* assert reset */
|
||||
mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x1);
|
||||
|
||||
/* power up GPU2D */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1);
|
||||
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ);
|
||||
|
||||
/* wait for power request done */
|
||||
while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU2D_PWR_REQ) {
|
||||
;
|
||||
}
|
||||
|
||||
udelay(1);
|
||||
|
||||
/* power up GPU3D */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1);
|
||||
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ);
|
||||
|
||||
/* wait for power request done */
|
||||
while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU3D_PWR_REQ) {
|
||||
;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
/* release the gpumix reset */
|
||||
mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x0);
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/* vpu sft clock enable */
|
||||
if (domain_id == VPUMIX) {
|
||||
mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x1);
|
||||
udelay(5);
|
||||
mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x0);
|
||||
udelay(5);
|
||||
|
||||
/* enable all clock */
|
||||
mmio_write_32(VPU_CTL_BASE + 0x4, 0x7);
|
||||
}
|
||||
|
||||
if (domain_id == DISPMIX) {
|
||||
/* special setting for DISPMIX */
|
||||
mmio_write_32(DISP_CTL_BASE + 0x4, 0x1fff);
|
||||
mmio_write_32(DISP_CTL_BASE, 0x7f);
|
||||
mmio_write_32(DISP_CTL_BASE + 0x8, 0x30000);
|
||||
}
|
||||
|
||||
/* handle the ADB400 sync */
|
||||
if (pwr_domain->need_sync) {
|
||||
/* clear adb power down request */
|
||||
mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
|
||||
|
||||
/* wait for adb power request ack */
|
||||
while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
if (domain_id == GPUMIX) {
|
||||
/* power up GPU2D ADB */
|
||||
mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC);
|
||||
|
||||
/* wait for adb power request ack */
|
||||
while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* power up GPU3D ADB */
|
||||
mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC);
|
||||
|
||||
/* wait for adb power request ack */
|
||||
while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
pu_domain_status &= ~(1 << domain_id);
|
||||
|
||||
if (domain_id == OTG1 || domain_id == OTG2) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* GPU2D & GPU3D ADB power down */
|
||||
if (domain_id == GPUMIX) {
|
||||
mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC);
|
||||
|
||||
/* wait for adb power request ack */
|
||||
while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) {
|
||||
;
|
||||
}
|
||||
|
||||
mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC);
|
||||
|
||||
/* wait for adb power request ack */
|
||||
while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/* handle the ADB400 sync */
|
||||
if (pwr_domain->need_sync) {
|
||||
/* set adb power down request */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
|
||||
|
||||
/* wait for adb power request ack */
|
||||
while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
if (domain_id == GPUMIX) {
|
||||
/* power down GPU2D */
|
||||
mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1);
|
||||
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ);
|
||||
|
||||
/* wait for power request done */
|
||||
while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU2D_PWR_REQ) {
|
||||
;
|
||||
}
|
||||
|
||||
/* power down GPU3D */
|
||||
mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1);
|
||||
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ);
|
||||
|
||||
/* wait for power request done */
|
||||
while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU3D_PWR_REQ) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/* HSIOMIX has no PU bit, so skip for it */
|
||||
if (domain_id != HSIOMIX) {
|
||||
/* set the PGC bit */
|
||||
mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
|
||||
|
||||
/* power down the domain */
|
||||
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
|
||||
|
||||
/* wait for power request done */
|
||||
while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) {
|
||||
;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void imx_gpc_init(void)
|
||||
{
|
||||
unsigned int val;
|
||||
int i;
|
||||
|
||||
/* mask all the wakeup irq by default */
|
||||
for (i = 0; i < 4; i++) {
|
||||
mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
|
||||
mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
|
||||
mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
|
||||
mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
|
||||
mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
|
||||
}
|
||||
|
||||
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
|
||||
/* use GIC wake_request to wakeup C0~C3 from LPM */
|
||||
val |= 0x30c00000;
|
||||
/* clear the MASTER0 LPM handshake */
|
||||
val &= ~(1 << 6);
|
||||
mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
|
||||
|
||||
/* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
|
||||
mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
|
||||
MASTER2_MAPPING));
|
||||
|
||||
/* set all mix/PU in A53 domain */
|
||||
mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);
|
||||
|
||||
/*
|
||||
* Set the CORE & SCU power up timing:
|
||||
* SW = 0x1, SW2ISO = 0x1;
|
||||
* the CPU CORE and SCU power up timming counter
|
||||
* is drived by 32K OSC, each domain's power up
|
||||
* latency is (SW + SW2ISO) / 32768
|
||||
*/
|
||||
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
|
||||
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
|
||||
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
|
||||
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
|
||||
mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
|
||||
mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
|
||||
(0x59 << 10) | 0x5B | (0x2 << 20));
|
||||
|
||||
/* set DUMMY PDN/PUP ACK by default for A53 domain */
|
||||
mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
|
||||
A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
|
||||
|
||||
/* clear DSM by default */
|
||||
val = mmio_read_32(IMX_GPC_BASE + SLPCR);
|
||||
val &= ~SLPCR_EN_DSM;
|
||||
/* enable the fast wakeup wait mode */
|
||||
val |= SLPCR_A53_FASTWUP_WAIT_MODE;
|
||||
/* clear the RBC */
|
||||
val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
|
||||
/* set the STBY_COUNT to 0x5, (128 * 30)us */
|
||||
val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
|
||||
val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
|
||||
mmio_write_32(IMX_GPC_BASE + SLPCR, val);
|
||||
|
||||
/*
|
||||
* USB PHY power up needs to make sure RESET bit in SRC is clear,
|
||||
* otherwise, the PU power up bit in GPC will NOT self-cleared.
|
||||
* only need to do it once.
|
||||
*/
|
||||
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
|
||||
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
|
||||
}
|
||||
+143
@@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* Copyright 2021 Arm
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <context.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/generic_delay_timer.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/optee_utils.h>
|
||||
#include <lib/utils.h>
|
||||
#include <stdbool.h>
|
||||
#include <tbbr_img_def.h>
|
||||
|
||||
#include <imx_aipstz.h>
|
||||
#include <imx_csu.h>
|
||||
#include <imx_uart.h>
|
||||
#include <imx_usdhc.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include "imx8mm_private.h"
|
||||
#include "platform_def.h"
|
||||
|
||||
static const struct aipstz_cfg aipstz[] = {
|
||||
{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{0},
|
||||
};
|
||||
|
||||
static void imx8mm_usdhc_setup(void)
|
||||
{
|
||||
imx_usdhc_params_t params;
|
||||
struct mmc_device_info info;
|
||||
|
||||
params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE;
|
||||
/*
|
||||
The imx8mm SD Card Speed modes for USDHC2
|
||||
+--------------+--------------------+--------------+--------------+
|
||||
|Bus Speed Mode|Max. Clock Frequency|Max. Bus Speed|Signal Voltage|
|
||||
+--------------+--------------------+--------------+--------------+
|
||||
|Default Speed | 25 MHz | 12.5 MB/s | 3.3V |
|
||||
|High Speed | 50 MHz | 25 MB/s | 3.3V |
|
||||
+--------------+--------------------+--------------+--------------+
|
||||
|
||||
We pick 50 Mhz here for High Speed access.
|
||||
*/
|
||||
params.clk_rate = 50000000;
|
||||
params.bus_width = MMC_BUS_WIDTH_1;
|
||||
params.flags = 0;
|
||||
info.mmc_dev_type = MMC_IS_SD;
|
||||
info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
|
||||
imx_usdhc_init(¶ms, &info);
|
||||
}
|
||||
|
||||
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4)
|
||||
{
|
||||
int i;
|
||||
static console_t console;
|
||||
|
||||
/* enable CSU NS access permission */
|
||||
for (i = 0; i < MAX_CSU_NUM; i++) {
|
||||
mmio_write_32(IMX_CSU_BASE + i * 4, CSU_CSL_OPEN_ACCESS);
|
||||
}
|
||||
|
||||
/* config the aips access permission */
|
||||
imx_aipstz_init(aipstz);
|
||||
|
||||
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
|
||||
IMX_CONSOLE_BAUDRATE, &console);
|
||||
|
||||
generic_delay_timer_init();
|
||||
|
||||
/* select the CKIL source to 32K OSC */
|
||||
mmio_write_32(0x30360124, 0x1);
|
||||
|
||||
imx8mm_usdhc_setup();
|
||||
|
||||
/* Open handles to a FIP image */
|
||||
plat_imx_io_setup();
|
||||
}
|
||||
|
||||
void bl2_el3_plat_arch_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
int err = 0;
|
||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
bl_mem_params_node_t *pager_mem_params = NULL;
|
||||
bl_mem_params_node_t *paged_mem_params = NULL;
|
||||
|
||||
assert(bl_mem_params);
|
||||
|
||||
switch (image_id) {
|
||||
case BL32_IMAGE_ID:
|
||||
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
|
||||
assert(pager_mem_params);
|
||||
|
||||
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
|
||||
assert(paged_mem_params);
|
||||
|
||||
err = parse_optee_header(&bl_mem_params->ep_info,
|
||||
&pager_mem_params->image_info,
|
||||
&paged_mem_params->image_info);
|
||||
if (err != 0) {
|
||||
WARN("OPTEE header parse error.\n");
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
/* Do nothing in default case */
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
return COUNTER_FREQUENCY;
|
||||
}
|
||||
|
||||
void bl2_plat_runtime_setup(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
||||
{
|
||||
.image_id = BL31_IMAGE_ID,
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
SECURE | EXECUTABLE | EP_FIRST_EXE),
|
||||
.ep_info.pc = BL31_BASE,
|
||||
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
|
||||
DISABLE_ALL_EXCEPTIONS),
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_PLAT_SETUP),
|
||||
.image_info.image_base = BL31_BASE,
|
||||
.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
.image_id = BL32_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
SECURE | EXECUTABLE),
|
||||
.ep_info.pc = BL32_BASE,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
|
||||
image_info_t, 0),
|
||||
|
||||
.image_info.image_base = BL32_BASE,
|
||||
.image_info.image_max_size = BL32_SIZE,
|
||||
|
||||
.next_handoff_image_id = BL33_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
.image_id = BL32_EXTRA1_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
|
||||
image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
|
||||
.image_info.image_base = BL32_BASE,
|
||||
.image_info.image_max_size = BL32_SIZE,
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
/* This is a zero sized image so we don't set base or size */
|
||||
.image_id = BL32_EXTRA2_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||
VERSION_2, entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_SKIP_LOADING),
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
{
|
||||
.image_id = BL33_IMAGE_ID,
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
|
||||
entry_point_info_t,
|
||||
NON_SECURE | EXECUTABLE),
|
||||
# ifdef PRELOADED_BL33_BASE
|
||||
.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_SKIP_LOADING),
|
||||
# else
|
||||
.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t, 0),
|
||||
.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
|
||||
.image_info.image_max_size = PLAT_NS_IMAGE_SIZE,
|
||||
# endif /* PRELOADED_BL33_BASE */
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
}
|
||||
};
|
||||
|
||||
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
|
||||
+252
@@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <context.h>
|
||||
#include <drivers/arm/tzc380.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/generic_delay_timer.h>
|
||||
#include <lib/el3_runtime/context_mgmt.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <dram.h>
|
||||
#include <gpc.h>
|
||||
#include <imx_aipstz.h>
|
||||
#include <imx_uart.h>
|
||||
#include <imx_rdc.h>
|
||||
#include <imx8m_caam.h>
|
||||
#include <imx8m_csu.h>
|
||||
#include <plat_imx8.h>
|
||||
|
||||
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
|
||||
|
||||
/*
|
||||
* Note: DRAM region is mapped with entire size available and uses MT_RW
|
||||
* attributes.
|
||||
* See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section
|
||||
* for explanation of this mapping scheme.
|
||||
*/
|
||||
static const mmap_region_t imx_mmap[] = {
|
||||
MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
|
||||
MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
|
||||
MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */
|
||||
MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */
|
||||
MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */
|
||||
MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
|
||||
MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
|
||||
MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */
|
||||
MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */
|
||||
{0},
|
||||
};
|
||||
|
||||
static const struct aipstz_cfg aipstz[] = {
|
||||
{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
|
||||
{0},
|
||||
};
|
||||
|
||||
static const struct imx_rdc_cfg rdc[] = {
|
||||
/* Master domain assignment */
|
||||
RDC_MDAn(RDC_MDA_M4, DID1),
|
||||
|
||||
/* peripherals domain permission */
|
||||
RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
|
||||
RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
|
||||
|
||||
/* memory region */
|
||||
|
||||
/* Sentinel */
|
||||
{0},
|
||||
};
|
||||
|
||||
static const struct imx_csu_cfg csu_cfg[] = {
|
||||
/* peripherals csl setting */
|
||||
CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED),
|
||||
|
||||
/* master HP0~1 */
|
||||
|
||||
/* SA setting */
|
||||
|
||||
/* HP control setting */
|
||||
|
||||
/* Sentinel */
|
||||
{0}
|
||||
};
|
||||
|
||||
static entry_point_info_t bl32_image_ep_info;
|
||||
static entry_point_info_t bl33_image_ep_info;
|
||||
|
||||
/* get SPSR for BL33 entry */
|
||||
static uint32_t get_spsr_for_bl33_entry(void)
|
||||
{
|
||||
unsigned long el_status;
|
||||
unsigned long mode;
|
||||
uint32_t spsr;
|
||||
|
||||
/* figure out what mode we enter the non-secure world */
|
||||
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
|
||||
el_status &= ID_AA64PFR0_ELX_MASK;
|
||||
|
||||
mode = (el_status) ? MODE_EL2 : MODE_EL1;
|
||||
|
||||
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
|
||||
return spsr;
|
||||
}
|
||||
|
||||
void bl31_tzc380_setup(void)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
|
||||
if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
|
||||
return;
|
||||
|
||||
tzc380_init(IMX_TZASC_BASE);
|
||||
|
||||
/*
|
||||
* Need to substact offset 0x40000000 from CPU address when
|
||||
* programming tzasc region for i.mx8mm.
|
||||
*/
|
||||
|
||||
/* Enable 1G-5G S/NS RW */
|
||||
tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
|
||||
TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
|
||||
}
|
||||
|
||||
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
static console_t console;
|
||||
int i;
|
||||
|
||||
/* Enable CSU NS access permission */
|
||||
for (i = 0; i < 64; i++) {
|
||||
mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
|
||||
}
|
||||
|
||||
imx_aipstz_init(aipstz);
|
||||
|
||||
imx_rdc_init(rdc);
|
||||
|
||||
imx_csu_init(csu_cfg);
|
||||
|
||||
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
|
||||
IMX_CONSOLE_BAUDRATE, &console);
|
||||
/* This console is only used for boot stage */
|
||||
console_set_scope(&console, CONSOLE_FLAG_BOOT);
|
||||
|
||||
imx8m_caam_init();
|
||||
|
||||
/*
|
||||
* tell BL3-1 where the non-secure software image is located
|
||||
* and the entry state information.
|
||||
*/
|
||||
bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
|
||||
bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
|
||||
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
|
||||
|
||||
#if defined(SPD_opteed) || defined(SPD_trusty)
|
||||
/* Populate entry point information for BL32 */
|
||||
SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
|
||||
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
|
||||
bl32_image_ep_info.pc = BL32_BASE;
|
||||
bl32_image_ep_info.spsr = 0;
|
||||
|
||||
/* Pass TEE base and size to bl33 */
|
||||
bl33_image_ep_info.args.arg1 = BL32_BASE;
|
||||
bl33_image_ep_info.args.arg2 = BL32_SIZE;
|
||||
|
||||
#ifdef SPD_trusty
|
||||
bl32_image_ep_info.args.arg0 = BL32_SIZE;
|
||||
bl32_image_ep_info.args.arg1 = BL32_BASE;
|
||||
#else
|
||||
/* Make sure memory is clean */
|
||||
mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
|
||||
bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
|
||||
bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
bl31_tzc380_setup();
|
||||
}
|
||||
|
||||
#define MAP_BL31_TOTAL \
|
||||
MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE)
|
||||
#define MAP_BL31_RO \
|
||||
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
|
||||
#define MAP_COHERENT_MEM \
|
||||
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
|
||||
MT_DEVICE | MT_RW | MT_SECURE)
|
||||
#define MAP_BL32_TOTAL \
|
||||
MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW)
|
||||
|
||||
void bl31_plat_arch_setup(void)
|
||||
{
|
||||
const mmap_region_t bl_regions[] = {
|
||||
MAP_BL31_TOTAL,
|
||||
MAP_BL31_RO,
|
||||
#if USE_COHERENT_MEM
|
||||
MAP_COHERENT_MEM,
|
||||
#endif
|
||||
/* Map TEE memory */
|
||||
MAP_BL32_TOTAL,
|
||||
{0}
|
||||
};
|
||||
|
||||
setup_page_tables(bl_regions, imx_mmap);
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
|
||||
void bl31_platform_setup(void)
|
||||
{
|
||||
generic_delay_timer_init();
|
||||
|
||||
/* select the CKIL source to 32K OSC */
|
||||
mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
|
||||
|
||||
/* Init the dram info */
|
||||
dram_info_init(SAVED_DRAM_TIMING_BASE);
|
||||
|
||||
plat_gic_driver_init();
|
||||
plat_gic_init();
|
||||
|
||||
imx_gpc_init();
|
||||
}
|
||||
|
||||
entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
|
||||
{
|
||||
if (type == NON_SECURE)
|
||||
return &bl33_image_ep_info;
|
||||
if (type == SECURE)
|
||||
return &bl32_image_ep_info;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
return COUNTER_FREQUENCY;
|
||||
}
|
||||
|
||||
#ifdef SPD_trusty
|
||||
void plat_trusty_set_boot_args(aapcs64_params_t *args)
|
||||
{
|
||||
args->arg0 = BL32_SIZE;
|
||||
args->arg1 = BL32_BASE;
|
||||
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
#include <gpc.h>
|
||||
#include <imx8m_psci.h>
|
||||
#include <plat_imx8.h>
|
||||
|
||||
static const plat_psci_ops_t imx_plat_psci_ops = {
|
||||
.pwr_domain_on = imx_pwr_domain_on,
|
||||
.pwr_domain_on_finish = imx_pwr_domain_on_finish,
|
||||
.pwr_domain_off = imx_pwr_domain_off,
|
||||
.validate_ns_entrypoint = imx_validate_ns_entrypoint,
|
||||
.validate_power_state = imx_validate_power_state,
|
||||
.cpu_standby = imx_cpu_standby,
|
||||
.pwr_domain_suspend = imx_domain_suspend,
|
||||
.pwr_domain_suspend_finish = imx_domain_suspend_finish,
|
||||
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
|
||||
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
|
||||
.system_reset = imx_system_reset,
|
||||
.system_reset2 = imx_system_reset2,
|
||||
.system_off = imx_system_off,
|
||||
};
|
||||
|
||||
/* export the platform specific psci ops */
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
/* sec_entrypoint is used for warm reset */
|
||||
imx_mailbox_init(sec_entrypoint);
|
||||
|
||||
*psci_ops = &imx_plat_psci_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
.global imx8mm_rotpk_hash
|
||||
.global imx8mm_rotpk_hash_end
|
||||
imx8mm_rotpk_hash:
|
||||
/* DER header */
|
||||
.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
|
||||
.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
|
||||
/* SHA256 */
|
||||
.incbin ROTPK_HASH
|
||||
imx8mm_rotpk_hash_end:
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
extern char imx8mm_rotpk_hash[], imx8mm_rotpk_hash_end[];
|
||||
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
*key_ptr = imx8mm_rotpk_hash;
|
||||
*key_len = imx8mm_rotpk_hash_end - imx8mm_rotpk_hash;
|
||||
*flags = ROTPK_IS_HASH;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
|
||||
{
|
||||
*nv_ctr = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
|
||||
{
|
||||
return get_mbedtls_heap_helper(heap_addr, heap_size);
|
||||
}
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef GPC_REG_H
|
||||
#define GPC_REG_H
|
||||
|
||||
#define LPCR_A53_BSC 0x0
|
||||
#define LPCR_A53_BSC2 0x108
|
||||
#define LPCR_A53_AD 0x4
|
||||
#define LPCR_M4 0x8
|
||||
#define SLPCR 0x14
|
||||
#define MST_CPU_MAPPING 0x18
|
||||
#define MLPCR 0x20
|
||||
#define PGC_ACK_SEL_A53 0x24
|
||||
#define IMR1_CORE0_A53 0x30
|
||||
#define IMR1_CORE1_A53 0x40
|
||||
#define IMR1_CORE2_A53 0x1C0
|
||||
#define IMR1_CORE3_A53 0x1D0
|
||||
#define IMR1_CORE0_M4 0x50
|
||||
#define SLT0_CFG 0xB0
|
||||
#define GPC_PU_PWRHSK 0x1FC
|
||||
#define PGC_CPU_0_1_MAPPING 0xEC
|
||||
#define CPU_PGC_UP_TRG 0xF0
|
||||
#define PU_PGC_UP_TRG 0xF8
|
||||
#define CPU_PGC_DN_TRG 0xFC
|
||||
#define PU_PGC_DN_TRG 0x104
|
||||
#define LPS_CPU1 0x114
|
||||
#define A53_CORE0_PGC 0x800
|
||||
#define A53_PLAT_PGC 0x900
|
||||
#define PLAT_PGC_PCR 0x900
|
||||
#define NOC_PGC_PCR 0xa40
|
||||
#define PGC_SCU_TIMING 0x910
|
||||
|
||||
#define MASK_DSM_TRIGGER_A53 BIT(31)
|
||||
#define IRQ_SRC_A53_WUP BIT(30)
|
||||
#define IRQ_SRC_A53_WUP_SHIFT 30
|
||||
#define IRQ_SRC_C1 BIT(29)
|
||||
#define IRQ_SRC_C0 BIT(28)
|
||||
#define IRQ_SRC_C3 BIT(23)
|
||||
#define IRQ_SRC_C2 BIT(22)
|
||||
#define CPU_CLOCK_ON_LPM BIT(14)
|
||||
#define A53_CLK_ON_LPM BIT(14)
|
||||
#define MASTER0_LPM_HSK BIT(6)
|
||||
#define MASTER1_LPM_HSK BIT(7)
|
||||
#define MASTER2_LPM_HSK BIT(8)
|
||||
|
||||
#define L2PGE BIT(31)
|
||||
#define EN_L2_WFI_PDN BIT(5)
|
||||
#define EN_PLAT_PDN BIT(4)
|
||||
|
||||
#define SLPCR_EN_DSM BIT(31)
|
||||
#define SLPCR_RBC_EN BIT(30)
|
||||
#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
|
||||
#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
|
||||
#define SLPCR_VSTBY BIT(2)
|
||||
#define SLPCR_SBYOS BIT(1)
|
||||
#define SLPCR_BYPASS_PMIC_READY BIT(0)
|
||||
#define SLPCR_RBC_COUNT_SHIFT 24
|
||||
#define SLPCR_STBY_COUNT_SHFT 3
|
||||
|
||||
#define A53_DUMMY_PDN_ACK BIT(15)
|
||||
#define A53_DUMMY_PUP_ACK BIT(31)
|
||||
#define A53_PLAT_PDN_ACK BIT(2)
|
||||
#define A53_PLAT_PUP_ACK BIT(18)
|
||||
#define NOC_PDN_SLT_CTRL BIT(10)
|
||||
#define NOC_PUP_SLT_CTRL BIT(11)
|
||||
#define NOC_PGC_PDN_ACK BIT(3)
|
||||
#define NOC_PGC_PUP_ACK BIT(19)
|
||||
|
||||
#define PLAT_PUP_SLT_CTRL BIT(9)
|
||||
#define PLAT_PDN_SLT_CTRL BIT(8)
|
||||
|
||||
#define SLT_PLAT_PDN BIT(8)
|
||||
#define SLT_PLAT_PUP BIT(9)
|
||||
|
||||
#define MASTER1_MAPPING BIT(1)
|
||||
#define MASTER2_MAPPING BIT(2)
|
||||
|
||||
#define MIPI_PWR_REQ BIT(0)
|
||||
#define PCIE_PWR_REQ BIT(1)
|
||||
#define OTG1_PWR_REQ BIT(2)
|
||||
#define OTG2_PWR_REQ BIT(3)
|
||||
#define HSIOMIX_PWR_REQ BIT(4)
|
||||
#define DDRMIX_PWR_REQ BIT(5)
|
||||
#define GPU2D_PWR_REQ BIT(6)
|
||||
#define GPUMIX_PWR_REQ BIT(7)
|
||||
#define VPUMIX_PWR_REQ BIT(8)
|
||||
#define GPU3D_PWR_REQ BIT(9)
|
||||
#define DISPMIX_PWR_REQ BIT(10)
|
||||
#define VPU_G1_PWR_REQ BIT(11)
|
||||
#define VPU_G2_PWR_REQ BIT(12)
|
||||
#define VPU_H1_PWR_REQ BIT(13)
|
||||
|
||||
#define DDRMIX_ADB400_SYNC BIT(2)
|
||||
#define HSIOMIX_ADB400_SYNC (0x3 << 5)
|
||||
#define DISPMIX_ADB400_SYNC BIT(7)
|
||||
#define VPUMIX_ADB400_SYNC BIT(8)
|
||||
#define GPU3D_ADB400_SYNC BIT(9)
|
||||
#define GPU2D_ADB400_SYNC BIT(10)
|
||||
#define GPUMIX_ADB400_SYNC BIT(11)
|
||||
#define DDRMIX_ADB400_ACK BIT(20)
|
||||
#define HSIOMIX_ADB400_ACK (0x3 << 23)
|
||||
#define DISPMIX_ADB400_ACK BIT(25)
|
||||
#define VPUMIX_ADB400_ACK BIT(26)
|
||||
#define GPU3D_ADB400_ACK BIT(27)
|
||||
#define GPU2D_ADB400_ACK BIT(28)
|
||||
#define GPUMIX_ADB400_ACK BIT(29)
|
||||
|
||||
#define MIPI_PGC 0xc00
|
||||
#define PCIE_PGC 0xc40
|
||||
#define OTG1_PGC 0xc80
|
||||
#define OTG2_PGC 0xcc0
|
||||
#define HSIOMIX_PGC 0xd00
|
||||
#define DDRMIX_PGC 0xd40
|
||||
#define GPU2D_PGC 0xd80
|
||||
#define GPUMIX_PGC 0xdc0
|
||||
#define VPUMIX_PGC 0xe00
|
||||
#define GPU3D_PGC 0xe40
|
||||
#define DISPMIX_PGC 0xe80
|
||||
#define VPU_G1_PGC 0xec0
|
||||
#define VPU_G2_PGC 0xf00
|
||||
#define VPU_H1_PGC 0xf40
|
||||
|
||||
#define IRQ_IMR_NUM U(4)
|
||||
|
||||
#endif /* GPC_REG_H */
|
||||
+15
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8MM_PRIVATE_H
|
||||
#define IMX8MM_PRIVATE_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void plat_imx_io_setup(void);
|
||||
|
||||
#endif /* IMX8MM_PRIVATE_H */
|
||||
+216
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
* Copyright 2020-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_SEC_DEF_H
|
||||
#define IMX_SEC_DEF_H
|
||||
|
||||
/* RDC MDA index */
|
||||
enum rdc_mda_idx {
|
||||
RDC_MDA_A53 = 0,
|
||||
RDC_MDA_M4 = 1,
|
||||
RDC_MDA_PCIE_CTRL1 = 2,
|
||||
RDC_MDA_SDMA3p = 3,
|
||||
RDC_MDA_VPU_Decoders = 4,
|
||||
RDC_MDA_LCDIF = 5,
|
||||
RDC_MDA_CSI1 = 6,
|
||||
RDC_MDA_SDMA3b = 7,
|
||||
RDC_MDA_Coresight = 8,
|
||||
RDC_MDA_DAP = 9,
|
||||
RDC_MDA_CAAM = 10,
|
||||
RDC_MDA_SDMA1p = 11,
|
||||
RDC_MDA_SDMA1b = 12,
|
||||
RDC_MDA_APBHDMA = 13,
|
||||
RDC_MDA_NAND = 14,
|
||||
RDC_MDA_uSDHC1 = 15,
|
||||
RDC_MDA_uSDHC2 = 16,
|
||||
RDC_MDA_uSDHC3 = 17,
|
||||
RDC_MDA_GPU = 18,
|
||||
RDC_MDA_USB1 = 19,
|
||||
RDC_MDA_USB2 = 20,
|
||||
RDC_MDA_TESTPORT = 21,
|
||||
RDC_MDA_ENET1_TX = 22,
|
||||
RDC_MDA_ENET1_RX = 23,
|
||||
RDC_MDA_SDMA2p = 24,
|
||||
RDC_MDA_SDMA2b = 24,
|
||||
RDC_MDA_SDMA2_to_SPBA2 = 24,
|
||||
RDC_MDA_SDMA3_to_SPBA2 = 25,
|
||||
RDC_MDA_SDMA1_to_SPBA1 = 26,
|
||||
};
|
||||
|
||||
/* RDC Peripherals index */
|
||||
enum rdc_pdap_idx {
|
||||
RDC_PDAP_GPIO2 = 1,
|
||||
RDC_PDAP_GPIO3 = 2,
|
||||
RDC_PDAP_GPIO4 = 3,
|
||||
RDC_PDAP_GPIO5 = 4,
|
||||
RDC_PDAP_ANA_TSENSOR = 6,
|
||||
RDC_PDAP_ANA_OSC = 7,
|
||||
RDC_PDAP_WDOG1 = 8,
|
||||
RDC_PDAP_WDOG2 = 9,
|
||||
RDC_PDAP_WDOG3 = 10,
|
||||
RDC_PDAP_SDMA3 = 11,
|
||||
RDC_PDAP_SDMA2 = 12,
|
||||
RDC_PDAP_GPT1 = 13,
|
||||
RDC_PDAP_GPT2 = 14,
|
||||
RDC_PDAP_GPT3 = 15,
|
||||
RDC_PDAP_ROMCP = 17,
|
||||
RDC_PDAP_IOMUXC = 19,
|
||||
RDC_PDAP_IOMUXC_GPR = 20,
|
||||
RDC_PDAP_OCOTP_CTRL = 21,
|
||||
RDC_PDAP_ANA_PLL = 22,
|
||||
RDC_PDAP_SNVS_HP = 23,
|
||||
RDC_PDAP_CCM = 24,
|
||||
RDC_PDAP_SRC = 25,
|
||||
RDC_PDAP_GPC = 26,
|
||||
RDC_PDAP_SEMAPHORE1 = 27,
|
||||
RDC_PDAP_SEMAPHORE2 = 28,
|
||||
RDC_PDAP_RDC = 29,
|
||||
RDC_PDAP_CSU = 30,
|
||||
RDC_PDAP_LCDIF = 32,
|
||||
RDC_PDAP_MIPI_DSI = 33,
|
||||
RDC_PDAP_CSI = 34,
|
||||
RDC_PDAP_MIPI_CSI = 35,
|
||||
RDC_PDAP_USB1 = 36,
|
||||
RDC_PDAP_PWM1 = 38,
|
||||
RDC_PDAP_PWM2 = 39,
|
||||
RDC_PDAP_PWM3 = 40,
|
||||
RDC_PDAP_PWM4 = 41,
|
||||
RDC_PDAP_System_Counter_RD = 42,
|
||||
RDC_PDAP_System_Counter_CMP = 43,
|
||||
RDC_PDAP_System_Counter_CTRL = 44,
|
||||
RDC_PDAP_GPT6 = 46,
|
||||
RDC_PDAP_GPT5 = 47,
|
||||
RDC_PDAP_GPT4 = 48,
|
||||
RDC_PDAP_TZASC = 56,
|
||||
RDC_PDAP_USB2 = 59,
|
||||
RDC_PDAP_PERFMON1 = 60,
|
||||
RDC_PDAP_PERFMON2 = 61,
|
||||
RDC_PDAP_PLATFORM_CTRL = 62,
|
||||
RDC_PDAP_QoSC = 63,
|
||||
RDC_PDAP_I2C1 = 66,
|
||||
RDC_PDAP_I2C2 = 67,
|
||||
RDC_PDAP_I2C3 = 68,
|
||||
RDC_PDAP_I2C4 = 69,
|
||||
RDC_PDAP_UART4 = 70,
|
||||
RDC_PDAP_MU_A = 74,
|
||||
RDC_PDAP_MU_B = 75,
|
||||
RDC_PDAP_SEMAPHORE_HS = 76,
|
||||
RDC_PDAP_SAI1 = 78,
|
||||
RDC_PDAP_SAI2 = 79,
|
||||
RDC_PDAP_SAI3 = 80,
|
||||
RDC_PDAP_SAI5 = 82,
|
||||
RDC_PDAP_SAI6 = 83,
|
||||
RDC_PDAP_uSDHC1 = 84,
|
||||
RDC_PDAP_uSDHC2 = 85,
|
||||
RDC_PDAP_uSDHC3 = 86,
|
||||
RDC_PDAP_PCIE_PHY1 = 88,
|
||||
RDC_PDAP_SPBA2 = 90,
|
||||
RDC_PDAP_QSPI = 91,
|
||||
RDC_PDAP_SDMA1 = 93,
|
||||
RDC_PDAP_ENET1 = 94,
|
||||
RDC_PDAP_SPDIF1 = 97,
|
||||
RDC_PDAP_eCSPI1 = 98,
|
||||
RDC_PDAP_eCSPI2 = 99,
|
||||
RDC_PDAP_eCSPI3 = 100,
|
||||
RDC_PDAP_MICFIL = 101,
|
||||
RDC_PDAP_UART1 = 102,
|
||||
RDC_PDAP_UART3 = 104,
|
||||
RDC_PDAP_UART2 = 105,
|
||||
RDC_PDAP_SPDIF2 = 106,
|
||||
RDC_PDAP_SPBA1 = 111,
|
||||
RDC_PDAP_CAAM = 114,
|
||||
};
|
||||
|
||||
enum csu_csl_idx {
|
||||
CSU_CSL_GPIO1 = 0,
|
||||
CSU_CSL_GPIO2 = 1,
|
||||
CSU_CSL_GPIO3 = 2,
|
||||
CSU_CSL_GPIO4 = 3,
|
||||
CSU_CSL_GPIO5 = 4,
|
||||
CSU_CSL_ANA_TSENSOR = 6,
|
||||
CSU_CSL_ANA_OSC = 7,
|
||||
CSU_CSL_WDOG1 = 8,
|
||||
CSU_CSL_WDOG2 = 9,
|
||||
CSU_CSL_WDOG3 = 10,
|
||||
CSU_CSL_SDMA2 = 12,
|
||||
CSU_CSL_GPT1 = 13,
|
||||
CSU_CSL_GPT2 = 14,
|
||||
CSU_CSL_GPT3 = 15,
|
||||
CSU_CSL_ROMCP = 17,
|
||||
CSU_CSL_LCDIF = 18,
|
||||
CSU_CSL_IOMUXC = 19,
|
||||
CSU_CSL_IOMUXC_GPR = 20,
|
||||
CSU_CSL_OCOTP_CTRL = 21,
|
||||
CSU_CSL_ANA_PLL = 22,
|
||||
CSU_CSL_SNVS_HP = 23,
|
||||
CSU_CSL_CCM = 24,
|
||||
CSU_CSL_SRC = 25,
|
||||
CSU_CSL_GPC = 26,
|
||||
CSU_CSL_SEMAPHORE1 = 27,
|
||||
CSU_CSL_SEMAPHORE2 = 28,
|
||||
CSU_CSL_RDC = 29,
|
||||
CSU_CSL_CSU = 30,
|
||||
CSU_CSL_DC_MST0 = 32,
|
||||
CSU_CSL_DC_MST1 = 33,
|
||||
CSU_CSL_DC_MST2 = 34,
|
||||
CSU_CSL_DC_MST3 = 35,
|
||||
CSU_CSL_PWM1 = 38,
|
||||
CSU_CSL_PWM2 = 39,
|
||||
CSU_CSL_PWM3 = 40,
|
||||
CSU_CSL_PWM4 = 41,
|
||||
CSU_CSL_System_Counter_RD = 42,
|
||||
CSU_CSL_System_Counter_CMP = 43,
|
||||
CSU_CSL_System_Counter_CTRL = 44,
|
||||
CSU_CSL_GPT6 = 46,
|
||||
CSU_CSL_GPT5 = 47,
|
||||
CSU_CSL_GPT4 = 48,
|
||||
CSU_CSL_TZASC = 56,
|
||||
CSU_CSL_MTR = 59,
|
||||
CSU_CSL_PERFMON1 = 60,
|
||||
CSU_CSL_PERFMON2 = 61,
|
||||
CSU_CSL_PLATFORM_CTRL = 62,
|
||||
CSU_CSL_QoSC = 63,
|
||||
CSU_CSL_MIPI_PHY = 64,
|
||||
CSU_CSL_MIPI_DSI = 65,
|
||||
CSU_CSL_I2C1 = 66,
|
||||
CSU_CSL_I2C2 = 67,
|
||||
CSU_CSL_I2C3 = 68,
|
||||
CSU_CSL_I2C4 = 69,
|
||||
CSU_CSL_UART4 = 70,
|
||||
CSU_CSL_MIPI_CSI1 = 71,
|
||||
CSU_CSL_MIPI_CSI_PHY1 = 72,
|
||||
CSU_CSL_CSI1 = 73,
|
||||
CSU_CSL_MU_A = 74,
|
||||
CSU_CSL_MU_B = 75,
|
||||
CSU_CSL_SEMAPHORE_HS = 76,
|
||||
CSU_CSL_SAI1 = 78,
|
||||
CSU_CSL_SAI6 = 80,
|
||||
CSU_CSL_SAI5 = 81,
|
||||
CSU_CSL_SAI4 = 82,
|
||||
CSU_CSL_uSDHC1 = 84,
|
||||
CSU_CSL_uSDHC2 = 85,
|
||||
CSU_CSL_MIPI_CSI2 = 86,
|
||||
CSU_CSL_MIPI_CSI_PHY2 = 87,
|
||||
CSU_CSL_CSI2 = 88,
|
||||
CSU_CSL_SPBA2 = 90,
|
||||
CSU_CSL_QSPI = 91,
|
||||
CSU_CSL_SDMA1 = 93,
|
||||
CSU_CSL_ENET1 = 94,
|
||||
CSU_CSL_SPDIF1 = 97,
|
||||
CSU_CSL_eCSPI1 = 98,
|
||||
CSU_CSL_eCSPI2 = 99,
|
||||
CSU_CSL_eCSPI3 = 100,
|
||||
CSU_CSL_UART1 = 102,
|
||||
CSU_CSL_UART3 = 104,
|
||||
CSU_CSL_UART2 = 105,
|
||||
CSU_CSL_SPDIF2 = 106,
|
||||
CSU_CSL_SAI2 = 107,
|
||||
CSU_CSL_SAI3 = 108,
|
||||
CSU_CSL_SPBA1 = 111,
|
||||
CSU_CSL_CAAM = 114,
|
||||
};
|
||||
|
||||
#endif /* IMX_SEC_DEF_H */
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
#define PLATFORM_STACK_SIZE 0xB00
|
||||
#define CACHE_WRITEBACK_GRANULE 64
|
||||
|
||||
#define PLAT_PRIMARY_CPU U(0x0)
|
||||
#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
|
||||
|
||||
#define IMX_PWR_LVL0 MPIDR_AFFLVL0
|
||||
#define IMX_PWR_LVL1 MPIDR_AFFLVL1
|
||||
#define IMX_PWR_LVL2 MPIDR_AFFLVL2
|
||||
|
||||
#define PWR_DOMAIN_AT_MAX_LVL U(1)
|
||||
#define PLAT_MAX_PWR_LVL U(2)
|
||||
#define PLAT_MAX_OFF_STATE U(4)
|
||||
#define PLAT_MAX_RET_STATE U(2)
|
||||
|
||||
#define PLAT_WAIT_RET_STATE U(1)
|
||||
#define PLAT_STOP_OFF_STATE U(3)
|
||||
|
||||
#define PLAT_PRI_BITS U(3)
|
||||
#define PLAT_SDEI_CRITICAL_PRI 0x10
|
||||
#define PLAT_SDEI_NORMAL_PRI 0x20
|
||||
#define PLAT_SDEI_SGI_PRIVATE U(9)
|
||||
|
||||
#if defined(NEED_BL2)
|
||||
#define BL2_BASE U(0x920000)
|
||||
#define BL2_SIZE SZ_128K
|
||||
#define BL2_LIMIT (BL2_BASE + BL2_SIZE)
|
||||
#define BL31_BASE U(0x900000)
|
||||
#define IMX_FIP_BASE U(0x40310000)
|
||||
#define IMX_FIP_SIZE U(0x000300000)
|
||||
#define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
|
||||
|
||||
/* Define FIP image location on eMMC */
|
||||
#define IMX_FIP_MMC_BASE U(0x100000)
|
||||
|
||||
#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */
|
||||
#else
|
||||
#define BL31_BASE U(0x920000)
|
||||
#endif
|
||||
|
||||
#define BL31_SIZE SZ_128K
|
||||
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
|
||||
|
||||
/* non-secure uboot base */
|
||||
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
|
||||
#define PLAT_NS_IMAGE_SIZE U(0x00200000)
|
||||
|
||||
#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000)
|
||||
|
||||
/* GICv3 base address */
|
||||
#define PLAT_GICD_BASE U(0x38800000)
|
||||
#define PLAT_GICR_BASE U(0x38880000)
|
||||
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
|
||||
|
||||
#define MAX_XLAT_TABLES 8
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
#define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */
|
||||
|
||||
#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */
|
||||
|
||||
#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
|
||||
#define PLAT_CRASH_UART_CLK_IN_HZ 24000000
|
||||
#define IMX_CONSOLE_BAUDRATE 115200
|
||||
|
||||
#define IMX_AIPSTZ1 U(0x301f0000)
|
||||
#define IMX_AIPSTZ2 U(0x305f0000)
|
||||
#define IMX_AIPSTZ3 U(0x309f0000)
|
||||
#define IMX_AIPSTZ4 U(0x32df0000)
|
||||
|
||||
#define IMX_AIPS_BASE U(0x30000000)
|
||||
#define IMX_AIPS_SIZE U(0x3000000)
|
||||
#define IMX_GPV_BASE U(0x32000000)
|
||||
#define IMX_GPV_SIZE U(0x800000)
|
||||
#define IMX_AIPS1_BASE U(0x30200000)
|
||||
#define IMX_AIPS4_BASE U(0x32c00000)
|
||||
#define IMX_ANAMIX_BASE U(0x30360000)
|
||||
#define IMX_CCM_BASE U(0x30380000)
|
||||
#define IMX_SRC_BASE U(0x30390000)
|
||||
#define IMX_GPC_BASE U(0x303a0000)
|
||||
#define IMX_RDC_BASE U(0x303d0000)
|
||||
#define IMX_CSU_BASE U(0x303e0000)
|
||||
#define IMX_WDOG_BASE U(0x30280000)
|
||||
#define IMX_SNVS_BASE U(0x30370000)
|
||||
#define IMX_NOC_BASE U(0x32700000)
|
||||
#define IMX_TZASC_BASE U(0x32F80000)
|
||||
#define IMX_IOMUX_GPR_BASE U(0x30340000)
|
||||
#define IMX_CAAM_BASE U(0x30900000)
|
||||
#define IMX_DDRC_BASE U(0x3d400000)
|
||||
#define IMX_DDRPHY_BASE U(0x3c000000)
|
||||
#define IMX_DDR_IPS_BASE U(0x3d000000)
|
||||
#define IMX_DDR_IPS_SIZE U(0x1800000)
|
||||
#define IMX_VPUMIX_BASE U(0x38330000)
|
||||
#define IMX_VPUMIX_SIZE U(0x100000)
|
||||
#define IMX_ROM_BASE U(0x0)
|
||||
#define IMX_ROM_SIZE U(0x40000)
|
||||
#define IMX_NS_OCRAM_BASE U(0x900000)
|
||||
#define IMX_NS_OCRAM_SIZE U(0x20000)
|
||||
#define IMX_CAAM_RAM_BASE U(0x100000)
|
||||
#define IMX_CAAM_RAM_SIZE U(0x10000)
|
||||
#define IMX_DRAM_BASE U(0x40000000)
|
||||
#define IMX_DRAM_SIZE U(0xc0000000)
|
||||
|
||||
#define GPV_BASE U(0x32000000)
|
||||
#define GPV_SIZE U(0x800000)
|
||||
#define IMX_GIC_BASE PLAT_GICD_BASE
|
||||
#define IMX_GIC_SIZE U(0x200000)
|
||||
|
||||
#define WDOG_WSR U(0x2)
|
||||
#define WDOG_WCR_WDZST BIT(0)
|
||||
#define WDOG_WCR_WDBG BIT(1)
|
||||
#define WDOG_WCR_WDE BIT(2)
|
||||
#define WDOG_WCR_WDT BIT(3)
|
||||
#define WDOG_WCR_SRS BIT(4)
|
||||
#define WDOG_WCR_WDA BIT(5)
|
||||
#define WDOG_WCR_SRE BIT(6)
|
||||
#define WDOG_WCR_WDW BIT(7)
|
||||
|
||||
#define SRC_A53RCR0 U(0x4)
|
||||
#define SRC_A53RCR1 U(0x8)
|
||||
#define SRC_OTG1PHY_SCR U(0x20)
|
||||
#define SRC_OTG2PHY_SCR U(0x24)
|
||||
#define SRC_GPR1_OFFSET U(0x74)
|
||||
#define SRC_GPR10_OFFSET U(0x98)
|
||||
#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
|
||||
|
||||
#define SNVS_LPCR U(0x38)
|
||||
#define SNVS_LPCR_SRTC_ENV BIT(0)
|
||||
#define SNVS_LPCR_DP_EN BIT(5)
|
||||
#define SNVS_LPCR_TOP BIT(6)
|
||||
|
||||
#define IOMUXC_GPR10 U(0x28)
|
||||
#define GPR_TZASC_EN BIT(0)
|
||||
#define GPR_TZASC_EN_LOCK BIT(16)
|
||||
|
||||
#define ANAMIX_MISC_CTL U(0x124)
|
||||
#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50)
|
||||
|
||||
#define MAX_CSU_NUM U(64)
|
||||
|
||||
#define OCRAM_S_BASE U(0x00180000)
|
||||
#define OCRAM_S_SIZE U(0x8000)
|
||||
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
|
||||
#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE
|
||||
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
#define IMX_WDOG_B_RESET
|
||||
|
||||
#define MAX_IO_HANDLES 3U
|
||||
#define MAX_IO_DEVICES 2U
|
||||
#define MAX_IO_BLOCK_DEVICES 1U
|
||||
|
||||
#define PLAT_IMX8M_DTO_BASE 0x53000000
|
||||
#define PLAT_IMX8M_DTO_MAX_SIZE 0x1000
|
||||
#define PLAT_IMX_EVENT_LOG_MAX_SIZE UL(0x400)
|
||||
@@ -0,0 +1,185 @@
|
||||
#
|
||||
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
# Translation tables library
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_INCLUDES := -Iplat/imx/common/include \
|
||||
-Iplat/imx/imx8m/include \
|
||||
-Iplat/imx/imx8m/imx8mm/include \
|
||||
-Idrivers/imx/usdhc \
|
||||
-Iinclude/common/tbbr \
|
||||
-Iinclude/lib/libfdt
|
||||
|
||||
# Include GICv3 driver files
|
||||
include drivers/arm/gic/v3/gicv3.mk
|
||||
|
||||
include lib/libfdt/libfdt.mk
|
||||
|
||||
IMX_DRAM_SOURCES := plat/imx/imx8m/ddr/dram.c \
|
||||
plat/imx/imx8m/ddr/clock.c \
|
||||
plat/imx/imx8m/ddr/dram_retention.c \
|
||||
plat/imx/imx8m/ddr/ddr4_dvfs.c \
|
||||
plat/imx/imx8m/ddr/lpddr4_dvfs.c
|
||||
|
||||
IMX_GIC_SOURCES := ${GICV3_SOURCES} \
|
||||
plat/common/plat_gicv3.c \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/imx/common/plat_imx8_gic.c
|
||||
|
||||
BL31_SOURCES += plat/imx/common/imx8_helpers.S \
|
||||
plat/imx/imx8m/gpc_common.c \
|
||||
plat/imx/imx8m/imx_hab.c \
|
||||
plat/imx/imx8m/imx_aipstz.c \
|
||||
plat/imx/imx8m/imx_rdc.c \
|
||||
plat/imx/imx8m/imx8m_csu.c \
|
||||
plat/imx/imx8m/imx8m_caam.c \
|
||||
plat/imx/imx8m/imx8m_psci_common.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_psci.c \
|
||||
plat/imx/imx8m/imx8mm/gpc.c \
|
||||
plat/imx/common/imx8_topology.c \
|
||||
plat/imx/common/imx_sip_handler.c \
|
||||
plat/imx/common/imx_sip_svc.c \
|
||||
plat/imx/common/imx_uart_console.S \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
drivers/arm/tzc/tzc380.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
${XLAT_TABLES_LIB_SRCS} \
|
||||
${IMX_DRAM_SOURCES} \
|
||||
${IMX_GIC_SOURCES}
|
||||
|
||||
ifeq (${NEED_BL2},yes)
|
||||
BL2_SOURCES += common/desc_image_load.c \
|
||||
common/fdt_wrappers.c \
|
||||
plat/imx/common/imx8_helpers.S \
|
||||
plat/imx/common/imx_uart_console.S \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c \
|
||||
plat/imx/imx8m/imx8mm/gpc.c \
|
||||
plat/imx/imx8m/imx_aipstz.c \
|
||||
plat/common/plat_psci_common.c \
|
||||
lib/xlat_tables/aarch64/xlat_tables.c \
|
||||
lib/xlat_tables/xlat_tables_common.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
${PLAT_GIC_SOURCES} \
|
||||
${PLAT_DRAM_SOURCES} \
|
||||
drivers/mmc/mmc.c \
|
||||
drivers/io/io_block.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/io/io_memmap.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/imx/usdhc/imx_usdhc.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c \
|
||||
plat/imx/common/imx_io_storage.c \
|
||||
plat/imx/imx8m/imx8m_image_load.c \
|
||||
lib/optee/optee_utils.c
|
||||
endif
|
||||
|
||||
# Add the build options to pack BLx images and kernel device tree
|
||||
# in the FIP if the platform requires.
|
||||
ifneq ($(BL2),)
|
||||
RESET_TO_BL31 := 0
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
|
||||
endif
|
||||
ifneq ($(BL32_EXTRA1),)
|
||||
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
|
||||
endif
|
||||
ifneq ($(BL32_EXTRA2),)
|
||||
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
|
||||
endif
|
||||
ifneq ($(HW_CONFIG),)
|
||||
$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
|
||||
endif
|
||||
|
||||
ifeq (${NEED_BL2},yes)
|
||||
$(eval $(call add_define,NEED_BL2))
|
||||
LOAD_IMAGE_V2 := 1
|
||||
# Non-TF Boot ROM
|
||||
BL2_AT_EL3 := 1
|
||||
endif
|
||||
|
||||
ifneq (${TRUSTED_BOARD_BOOT},0)
|
||||
|
||||
include drivers/auth/mbedtls/mbedtls_crypto.mk
|
||||
include drivers/auth/mbedtls/mbedtls_x509.mk
|
||||
|
||||
AUTH_SOURCES := drivers/auth/auth_mod.c \
|
||||
drivers/auth/crypto_mod.c \
|
||||
drivers/auth/img_parser_mod.c \
|
||||
drivers/auth/tbbr/tbbr_cot_common.c \
|
||||
drivers/auth/tbbr/tbbr_cot_bl2.c
|
||||
|
||||
BL2_SOURCES += ${AUTH_SOURCES} \
|
||||
plat/common/tbbr/plat_tbbr.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c \
|
||||
plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
|
||||
|
||||
ROT_KEY = $(BUILD_PLAT)/rot_key.pem
|
||||
ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
|
||||
|
||||
$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
|
||||
$(eval $(call MAKE_LIB_DIRS))
|
||||
|
||||
$(BUILD_PLAT)/bl2/imx8mm_rotpk.o: $(ROTPK_HASH)
|
||||
|
||||
certificates: $(ROT_KEY)
|
||||
|
||||
$(ROT_KEY): | $(BUILD_PLAT)
|
||||
@echo " OPENSSL $@"
|
||||
@if [ ! -f $(ROT_KEY) ]; then \
|
||||
${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
|
||||
fi
|
||||
|
||||
$(ROTPK_HASH): $(ROT_KEY)
|
||||
@echo " OPENSSL $@"
|
||||
$(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
|
||||
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
|
||||
endif
|
||||
|
||||
ENABLE_PIE := 1
|
||||
USE_COHERENT_MEM := 1
|
||||
RESET_TO_BL31 := 1
|
||||
A53_DISABLE_NON_TEMPORAL_HINT := 0
|
||||
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 1
|
||||
|
||||
BL32_BASE ?= 0xbe000000
|
||||
$(eval $(call add_define,BL32_BASE))
|
||||
|
||||
BL32_SIZE ?= 0x2000000
|
||||
$(eval $(call add_define,BL32_SIZE))
|
||||
|
||||
IMX_BOOT_UART_BASE ?= 0x30890000
|
||||
$(eval $(call add_define,IMX_BOOT_UART_BASE))
|
||||
|
||||
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
|
||||
ifeq (${SDEI_SUPPORT}, 1)
|
||||
BL31_SOURCES += plat/imx/common/imx_ehf.c \
|
||||
plat/imx/common/imx_sdei.c
|
||||
endif
|
||||
|
||||
ifeq (${MEASURED_BOOT},1)
|
||||
MEASURED_BOOT_MK := drivers/measured_boot/event_log/event_log.mk
|
||||
$(info Including ${MEASURED_BOOT_MK})
|
||||
include ${MEASURED_BOOT_MK}
|
||||
|
||||
ifneq (${MBOOT_EL_HASH_ALG}, sha256)
|
||||
$(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512))
|
||||
endif
|
||||
|
||||
BL2_SOURCES += plat/imx/imx8m/imx8m_measured_boot.c \
|
||||
plat/imx/imx8m/imx8m_dyn_cfg_helpers.c \
|
||||
${EVENT_LOG_SOURCES}
|
||||
endif
|
||||
|
||||
ifeq (${SPD},trusty)
|
||||
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
|
||||
endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user