GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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#
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# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Architecture
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$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
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TF_CFLAGS += -mfpu=neon
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ASFLAGS += -mfpu=neon
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# Platform
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PLAT_INCLUDES := -Idrivers/imx/uart \
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-Iplat/imx/common/include \
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-Iplat/imx/imx7/include \
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-Idrivers/imx/timer \
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-Idrivers/imx/usdhc \
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-Iinclude/common/tbbr
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# Translation tables library
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include lib/xlat_tables_v2/xlat_tables.mk
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BL2_SOURCES += common/desc_image_load.c \
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drivers/delay_timer/delay_timer.c \
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drivers/mmc/mmc.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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drivers/io/io_storage.c \
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drivers/imx/timer/imx_gpt.c \
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drivers/imx/uart/imx_uart.c \
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drivers/imx/uart/imx_crash_uart.S \
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lib/aarch32/arm32_aeabi_divmod.c \
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lib/aarch32/arm32_aeabi_divmod_a32.S \
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lib/cpus/aarch32/cortex_a7.S \
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lib/optee/optee_utils.c \
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plat/imx/common/imx_aips.c \
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plat/imx/common/imx_caam.c \
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plat/imx/common/imx_clock.c \
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plat/imx/common/imx_csu.c \
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plat/imx/common/imx_io_mux.c \
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plat/imx/common/imx_snvs.c \
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plat/imx/common/imx_wdog.c \
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plat/imx/common/imx7_clock.c \
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plat/imx/imx7/common/imx7_bl2_mem_params_desc.c \
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plat/imx/imx7/common/imx7_bl2_el3_common.c \
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plat/imx/imx7/common/imx7_helpers.S \
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plat/imx/imx7/common/imx7_image_load.c \
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plat/imx/common/imx_io_storage.c \
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plat/imx/common/aarch32/imx_uart_console.S \
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${XLAT_TABLES_LIB_SRCS}
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ifneq (${TRUSTED_BOARD_BOOT},0)
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include drivers/auth/mbedtls/mbedtls_crypto.mk
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include drivers/auth/mbedtls/mbedtls_x509.mk
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AUTH_SOURCES := drivers/auth/auth_mod.c \
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drivers/auth/crypto_mod.c \
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drivers/auth/img_parser_mod.c \
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drivers/auth/tbbr/tbbr_cot_common.c
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BL2_SOURCES += ${AUTH_SOURCES} \
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plat/common/tbbr/plat_tbbr.c \
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plat/imx/imx7/common/imx7_trusted_boot.c \
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plat/imx/imx7/common/imx7_rotpk.S \
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drivers/auth/tbbr/tbbr_cot_bl2.c
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ROT_KEY = $(BUILD_PLAT)/rot_key.pem
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ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
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$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
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$(eval $(call MAKE_LIB_DIRS))
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$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH)
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certificates: $(ROT_KEY)
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$(ROT_KEY): | $(BUILD_PLAT)
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@echo " OPENSSL $@"
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@if [ ! -f $(ROT_KEY) ]; then \
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${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
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fi
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$(ROTPK_HASH): $(ROT_KEY)
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@echo " OPENSSL $@"
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$(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
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${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
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endif
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# Add the build options to pack BLx images and kernel device tree
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# in the FIP if the platform requires.
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ifneq ($(BL2),)
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$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
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endif
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ifneq ($(BL32_EXTRA1),)
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$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
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endif
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ifneq ($(BL32_EXTRA2),)
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$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
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endif
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ifneq ($(HW_CONFIG),)
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$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
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endif
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# Verify build config
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# -------------------
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ifeq (${ARCH},aarch64)
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$(error Error: AArch64 not supported on i.mx7)
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endif
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+198
@@ -0,0 +1,198 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/mmc.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/utils.h>
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#include <imx_aips.h>
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#include <imx_caam.h>
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#include <imx_clock.h>
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#include <imx_csu.h>
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#include <imx_gpt.h>
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#include <imx_uart.h>
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#include <imx_snvs.h>
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#include <imx_wdog.h>
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#include <imx7_def.h>
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#ifndef AARCH32_SP_OPTEE
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#error "Must build with OPTEE support included"
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#endif
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return IMX7_UBOOT_BASE;
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}
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static uint32_t imx7_get_spsr_for_bl32_entry(void)
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{
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return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS);
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}
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static uint32_t imx7_get_spsr_for_bl33_entry(void)
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{
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return SPSR_MODE32(MODE32_svc,
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plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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bl_mem_params_node_t *hw_cfg_mem_params = NULL;
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0)
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WARN("OPTEE header parse error.\n");
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/*
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* When ATF loads the DTB the address of the DTB is passed in
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* arg2, if an hw config image is present use the base address
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* as DTB address an pass it as arg2
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*/
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hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
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bl_mem_params->ep_info.args.arg0 =
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bl_mem_params->ep_info.args.arg1;
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bl_mem_params->ep_info.args.arg1 = 0;
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if (hw_cfg_mem_params)
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bl_mem_params->ep_info.args.arg2 =
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hw_cfg_mem_params->image_info.image_base;
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else
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bl_mem_params->ep_info.args.arg2 = 0;
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bl_mem_params->ep_info.args.arg3 = 0;
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bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry();
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break;
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case BL33_IMAGE_ID:
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/* AArch32 only core: OP-TEE expects NSec EP in register LR */
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pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
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assert(pager_mem_params);
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pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry();
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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void bl2_el3_plat_arch_setup(void)
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{
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/* Setup the MMU here */
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}
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static void imx7_setup_system_counter(void)
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{
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unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
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/* Set the frequency table index to our target frequency */
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write_cntfrq(freq);
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/* Enable system counter @ frequency table index 0, halt on debug */
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mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
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}
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static void imx7_setup_wdog_clocks(void)
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{
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uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT;
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imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
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imx_clock_enable_wdog(0);
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imx_clock_enable_wdog(1);
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imx_clock_enable_wdog(2);
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imx_clock_enable_wdog(3);
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}
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/*
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* bl2_el3_early_platform_setup()
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* MMU off
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*/
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void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
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u_register_t arg3, u_register_t arg4)
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{
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static console_t console;
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int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME;
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/* Initialize common components */
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imx_aips_init();
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imx_csu_init();
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imx_snvs_init();
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imx_gpt_ops_init(GPT1_BASE_ADDR);
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imx_clock_init();
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imx7_setup_system_counter();
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imx7_setup_wdog_clocks();
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/* Platform specific setup */
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imx7_platform_setup(arg1, arg2, arg3, arg4);
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/* Init UART, clock should be enabled in imx7_platform_setup() */
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console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE,
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PLAT_IMX7_BOOT_UART_CLK_IN_HZ,
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PLAT_IMX7_CONSOLE_BAUDRATE,
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&console);
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console_set_scope(&console, console_scope);
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/* Open handles to persistent storage */
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plat_imx_io_setup();
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/* Setup higher-level functionality CAAM, RTC etc */
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imx_caam_init();
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imx_wdog_init();
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/* Print out the expected memory map */
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VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT);
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VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
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VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
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VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX_FIP_BASE, IMX_FIP_LIMIT);
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VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT);
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VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT);
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VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT);
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}
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/*
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* bl2_platform_setup()
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* MMU on - enabled by bl2_el3_plat_arch_setup()
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*/
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void bl2_platform_setup(void)
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{
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}
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+81
@@ -0,0 +1,81 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <plat/common/platform.h>
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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{
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.image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL32_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, 0),
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.image_info.image_base = IMX7_OPTEE_BASE,
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.image_info.image_max_size = IMX7_OPTEE_SIZE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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{
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.image_id = BL32_EXTRA1_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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.image_info.image_base = IMX7_OPTEE_BASE,
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.image_info.image_max_size = IMX7_OPTEE_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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{
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/* This is a zero sized image so we don't set base or size */
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.image_id = BL32_EXTRA2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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NON_SECURE | EXECUTABLE),
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# ifdef PRELOADED_BL33_BASE
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.ep_info.pc = PRELOADED_BL33_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_SKIP_LOADING),
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# else
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.ep_info.pc = BL33_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = IMX7_UBOOT_BASE,
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.image_info.image_max_size = IMX7_UBOOT_SIZE,
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# endif /* PRELOADED_BL33_BASE */
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
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@@ -0,0 +1,59 @@
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/*
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* Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved.
|
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*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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#include <imx_hab.h>
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.globl platform_mem_init
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.globl plat_get_my_entrypoint
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
|
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.globl plat_panic_handler
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||||
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||||
/* ---------------------------------------------
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* int plat_mem_init(void)
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* Function to initialize memory.
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* The HAB hands off the DDR controller already
|
||||
* setup and ready to use.
|
||||
* Implement the mandatory function as a NOP
|
||||
* ---------------------------------------------
|
||||
*/
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||||
func platform_mem_init
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bx lr
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||||
endfunc platform_mem_init
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||||
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||||
func plat_get_my_entrypoint
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mov r0, #0
|
||||
bx lr
|
||||
endfunc plat_get_my_entrypoint
|
||||
|
||||
func plat_crash_console_init
|
||||
mov_imm r0, PLAT_IMX7_BOOT_UART_BASE
|
||||
mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ
|
||||
mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE
|
||||
b imx_crash_uart_init
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
func plat_crash_console_putc
|
||||
mov_imm r1, PLAT_IMX7_BOOT_UART_BASE
|
||||
b imx_crash_uart_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
||||
func plat_crash_console_flush
|
||||
/* Placeholder */
|
||||
mov r0, #0
|
||||
bx lr
|
||||
endfunc plat_crash_console_flush
|
||||
|
||||
func plat_panic_handler
|
||||
mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE
|
||||
ldr r3, [r3, #0]
|
||||
blx r3
|
||||
endfunc plat_panic_handler
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/bl_common.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
void plat_flush_next_bl_params(void)
|
||||
{
|
||||
flush_bl_params_desc();
|
||||
}
|
||||
|
||||
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||
{
|
||||
return get_bl_load_info_from_mem_params_desc();
|
||||
}
|
||||
|
||||
bl_params_t *plat_get_next_bl_params(void)
|
||||
{
|
||||
return get_next_bl_params_from_mem_params_desc();
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
.global imx7_rotpk_hash
|
||||
.global imx7_rotpk_hash_end
|
||||
imx7_rotpk_hash:
|
||||
/* DER header */
|
||||
.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
|
||||
.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
|
||||
/* SHA256 */
|
||||
.incbin ROTPK_HASH
|
||||
imx7_rotpk_hash_end:
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[];
|
||||
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
*key_ptr = imx7_rotpk_hash;
|
||||
*key_len = imx7_rotpk_hash_end - imx7_rotpk_hash;
|
||||
*flags = ROTPK_IS_HASH;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
|
||||
{
|
||||
*nv_ctr = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
|
||||
{
|
||||
return get_mbedtls_heap_helper(heap_addr, heap_size);
|
||||
}
|
||||
Reference in New Issue
Block a user