GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT)
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#define WARP7_PRIMARY_CPU U(0)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET 1
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF 2
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH 4
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#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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* i.MX7 has a 32 byte cacheline size
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 pg 244
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*/
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#define CACHE_WRITEBACK_SHIFT 4
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*
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* Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
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*/
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#define BOOT_ROM_BASE 0x00000000
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#define BOOT_ROM_SIZE 0x00020000
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#define OCRAM_S_BASE 0x00180000
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#define OCRAM_S_SIZE 0x00008000
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/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
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#define DRAM_BASE 0x80000000
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#define DRAM_SIZE 0x20000000
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#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
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/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
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#define IMX7_OPTEE_SIZE 0x02000000
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#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE)
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#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
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/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
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#define BL2_RAM_SIZE 0x00100000
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#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE)
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#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
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/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
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#define SHARED_RAM_SIZE 0x00001000
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#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
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#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
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/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
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#define IMX7_UBOOT_SIZE 0x00100000
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#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000)
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#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
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/* Define FIP image absolute location 0x80000000 - 0x80100000 */
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#define IMX_FIP_SIZE 0x00100000
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#define IMX_FIP_BASE (DRAM_BASE)
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#define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE)
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/* Define FIP image location at 1MB offset */
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#define IMX_FIP_MMC_BASE (1024 * 1024)
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/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
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#define IMX7_DTB_SIZE 0x00100000
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#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000)
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#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE)
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/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */
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#define IMX7_DTB_OVERLAY_SIZE 0x00001000
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#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT
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#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \
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IMX7_DTB_OVERLAY_SIZE)
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/*
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* BL2 specific defines.
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*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE BL2_RAM_BASE
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#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
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/*
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* BL3-2/OPTEE
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*/
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# define BL32_BASE IMX7_OPTEE_BASE
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# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE)
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/*
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* BL3-3/U-BOOT
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*/
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#define BL33_BASE IMX7_UBOOT_BASE
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#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
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/*
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* ATF's view of memory
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*
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* 0xa0000000 +-----------------+
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* | DDR | BL32/OPTEE
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* 0x9e000000 +-----------------+
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* | DDR | BL23 ATF
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* 0x9df00000 +-----------------+
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* | DDR | Shared MBOX RAM
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* 0x9de00000 +-----------------+
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* | DDR | Unallocated
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* 0x87900000 +-----------------+
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* | DDR | BL33/U-BOOT
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* 0x87800000 +-----------------+
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* | DDR | Unallocated
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* 0x83101000 +-----------------+
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* | DDR | DTB Overlay
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* 0x83100000 +-----------------+
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* | DDR | DTB
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* 0x83000000 +-----------------+
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* | DDR | Unallocated
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* 0x80100000 +-----------------+
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* | DDR | FIP
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* 0x80000000 +-----------------+
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* | SOC I/0 |
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* 0x00a00000 +-----------------+
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* | OCRAM | Not used
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* 0x00900000 +-----------------+
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* | SOC I/0 |
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* 0x00188000 +-----------------+
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* | OCRAM_S | Not used
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* 0x00180000 +-----------------+
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* | SOC I/0 |
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* 0x00020000 +-----------------+
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* | BootROM | BL1
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* 0x00000000 +-----------------+
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_MMAP_REGIONS 10
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#define MAX_XLAT_TABLES 6
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#define MAX_IO_DEVICES 2
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#define MAX_IO_HANDLES 3
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#define MAX_IO_BLOCK_DEVICES 1U
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/* UART defines */
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#if PLAT_WARP7_UART == 1
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#define PLAT_WARP7_UART_BASE MXC_UART1_BASE
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#elif PLAT_WARP7_UART == 6
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#define IMX_UART_DTE
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#define PLAT_WARP7_UART_BASE MXC_UART6_BASE
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#else
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#error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
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#endif
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#define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE
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#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000
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#define PLAT_IMX7_CONSOLE_BAUDRATE 115200
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/* MMC defines */
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#ifndef PLAT_WARP7_SD
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#define PLAT_WARP7_SD 3
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#endif
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#if PLAT_WARP7_SD == 1
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#define PLAT_WARP7_BOOT_MMC_BASE USDHC1_BASE
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#endif /* PLAT_WARP7_SD == 1 */
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#if PLAT_WARP7_SD == 2
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#define PLAT_WARP7_BOOT_MMC_BASE USDHC2_BASE
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#endif /* PLAT_WARP7_SD == 2 */
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#if PLAT_WARP7_SD == 3
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#define PLAT_WARP7_BOOT_MMC_BASE USDHC3_BASE
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#endif /* PLAT_WARP7_SD == 3 */
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
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#endif /* PLATFORM_DEF_H */
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@@ -0,0 +1,37 @@
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#
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# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Include imx7 common
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include plat/imx/imx7/common/imx7.mk
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# Platform
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PLAT_INCLUDES += -Iplat/imx/imx7/warp7/include
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BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \
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plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
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# Build config flags
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# ------------------
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ARM_CORTEX_A7 := yes
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WORKAROUND_CVE_2017_5715 := 0
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RESET_TO_BL31 := 0
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# Non-TF Boot ROM
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BL2_AT_EL3 := 1
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# Indicate single-core
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COLD_BOOT_SINGLE_CPU := 1
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# Have different sections for code and rodata
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SEPARATE_CODE_AND_RODATA := 1
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# Use Coherent memory
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USE_COHERENT_MEM := 1
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PLAT_WARP7_UART :=1
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$(eval $(call add_define,PLAT_WARP7_UART))
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+143
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/*
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/mmc.h>
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#include <lib/utils.h>
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#include <imx_caam.h>
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#include <imx_clock.h>
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#include <imx_io_mux.h>
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#include <imx_uart.h>
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#include <imx_usdhc.h>
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#include <imx7_def.h>
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#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
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#define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M)
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#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
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CCM_TARGET_POST_PODF(2))
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#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
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#define WARP7_UART1_TX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
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#define WARP7_UART1_TX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4)
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#define WARP7_UART1_RX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA
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#define WARP7_UART1_RX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4)
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#define WARP7_UART6_TX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA
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#define WARP7_UART6_TX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4)
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#define WARP7_UART6_RX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA
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#define WARP7_UART6_RX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
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static struct mmc_device_info mmc_info;
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static void warp7_setup_pinmux(void)
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{
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/* Configure UART1 TX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET,
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WARP7_UART1_TX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET,
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WARP7_UART1_TX_FEATURES);
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/* Configure UART1 RX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET,
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WARP7_UART1_RX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET,
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WARP7_UART1_RX_FEATURES);
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/* Configure UART6 TX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET,
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WARP7_UART6_TX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET,
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WARP7_UART6_TX_FEATURES);
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/* Configure UART6 RX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET,
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WARP7_UART6_RX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET,
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WARP7_UART6_RX_FEATURES);
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}
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static void warp7_usdhc_setup(void)
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{
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imx_usdhc_params_t params;
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zeromem(¶ms, sizeof(imx_usdhc_params_t));
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params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
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params.clk_rate = 25000000;
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params.bus_width = MMC_BUS_WIDTH_8;
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mmc_info.mmc_dev_type = MMC_IS_EMMC;
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imx_usdhc_init(¶ms, &mmc_info);
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}
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static void warp7_setup_usb_clocks(void)
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{
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uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
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imx_clock_set_usb_clk_root_bits(usb_en_bits);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
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}
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void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
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u_register_t arg3, u_register_t arg4)
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{
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uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
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uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
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uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
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/* Initialize clocks etc */
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imx_clock_enable_uart(0, uart1_en_bits);
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imx_clock_enable_uart(5, uart6_en_bits);
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imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
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warp7_setup_usb_clocks();
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/* Setup pin-muxes */
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warp7_setup_pinmux();
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warp7_usdhc_setup();
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}
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