GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright 2019-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl31/interrupt_mgmt.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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#include <plat/common/platform.h>
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#include <dram.h>
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#define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10
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#define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11
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struct dram_info dram_info;
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/* lock used for DDR DVFS */
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spinlock_t dfs_lock;
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static volatile uint32_t wfe_done;
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static volatile bool wait_ddrc_hwffc_done = true;
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static unsigned int dev_fsp = 0x1;
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static uint32_t fsp_init_reg[3][4] = {
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{ DDRC_INIT3(0), DDRC_INIT4(0), DDRC_INIT6(0), DDRC_INIT7(0) },
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{ DDRC_FREQ1_INIT3(0), DDRC_FREQ1_INIT4(0), DDRC_FREQ1_INIT6(0), DDRC_FREQ1_INIT7(0) },
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{ DDRC_FREQ2_INIT3(0), DDRC_FREQ2_INIT4(0), DDRC_FREQ2_INIT6(0), DDRC_FREQ2_INIT7(0) },
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};
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static void get_mr_values(uint32_t (*mr_value)[8])
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{
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uint32_t init_val;
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unsigned int i, fsp_index;
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for (fsp_index = 0U; fsp_index < 3U; fsp_index++) {
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for (i = 0U; i < 4U; i++) {
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init_val = mmio_read_32(fsp_init_reg[fsp_index][i]);
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mr_value[fsp_index][2*i] = init_val >> 16;
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mr_value[fsp_index][2*i + 1] = init_val & 0xFFFF;
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}
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}
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}
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/* Restore the ddrc configs */
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void dram_umctl2_init(struct dram_timing_info *timing)
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{
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struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg;
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unsigned int i;
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for (i = 0U; i < timing->ddrc_cfg_num; i++) {
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mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val);
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ddrc_cfg++;
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}
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/* set the default fsp to P0 */
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mmio_write_32(DDRC_MSTR2(0), 0x0);
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}
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/* Restore the dram PHY config */
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void dram_phy_init(struct dram_timing_info *timing)
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{
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struct dram_cfg_param *cfg = timing->ddrphy_cfg;
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unsigned int i;
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/* Restore the PHY init config */
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cfg = timing->ddrphy_cfg;
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for (i = 0U; i < timing->ddrphy_cfg_num; i++) {
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dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
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cfg++;
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}
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/* Restore the DDR PHY CSRs */
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cfg = timing->ddrphy_trained_csr;
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for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) {
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dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
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cfg++;
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}
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/* Load the PIE image */
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cfg = timing->ddrphy_pie;
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for (i = 0U; i < timing->ddrphy_pie_num; i++) {
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dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
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cfg++;
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}
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}
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/* EL3 SGI-8 IPI handler for DDR Dynamic frequency scaling */
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static uint64_t waiting_dvfs(uint32_t id, uint32_t flags,
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void *handle, void *cookie)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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uint32_t irq;
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irq = plat_ic_acknowledge_interrupt();
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if (irq < 1022U) {
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plat_ic_end_of_interrupt(irq);
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}
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/* set the WFE done status */
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spin_lock(&dfs_lock);
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wfe_done |= (1 << cpu_id * 8);
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dsb();
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spin_unlock(&dfs_lock);
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while (1) {
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/* ddr frequency change done */
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if (!wait_ddrc_hwffc_done)
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break;
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wfe();
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}
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return 0;
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}
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void dram_info_init(unsigned long dram_timing_base)
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{
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uint32_t ddrc_mstr, current_fsp;
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unsigned int idx = 0;
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uint32_t flags = 0;
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uint32_t rc;
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unsigned int i;
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/* Get the dram type & rank */
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ddrc_mstr = mmio_read_32(DDRC_MSTR(0));
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dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK;
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dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK;
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/* Get current fsp info */
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current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf;
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dram_info.boot_fsp = current_fsp;
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dram_info.current_fsp = current_fsp;
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get_mr_values(dram_info.mr_table);
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dram_info.timing_info = (struct dram_timing_info *)dram_timing_base;
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/* get the num of supported fsp */
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for (i = 0U; i < 4U; ++i) {
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if (!dram_info.timing_info->fsp_table[i]) {
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break;
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}
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idx = i;
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}
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dram_info.num_fsp = i;
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/* check if has bypass mode support */
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if (dram_info.timing_info->fsp_table[idx] < 666) {
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dram_info.bypass_mode = true;
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} else {
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dram_info.bypass_mode = false;
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}
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/* Register the EL3 handler for DDR DVFS */
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set_interrupt_rm_flag(flags, NON_SECURE);
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rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags);
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if (rc != 0) {
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panic();
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}
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}
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/*
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* For each freq return the following info:
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*
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* r1: data rate
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* r2: 1 + dram_core parent
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* r3: 1 + dram_alt parent index
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* r4: 1 + dram_apb parent index
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*
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* The parent indices can be used by an OS who manages source clocks to enabled
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* them ahead of the switch.
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*
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* A parent value of "0" means "don't care".
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*
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* Current implementation of freq switch is hardcoded in
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* plat/imx/common/imx8m/clock.c but in theory this can be enhanced to support
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* a wide variety of rates.
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*/
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int dram_dvfs_get_freq_info(void *handle, u_register_t index)
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{
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switch (index) {
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case 0:
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SMC_RET4(handle, dram_info.timing_info->fsp_table[0],
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1, 0, 5);
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case 1:
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if (!dram_info.bypass_mode) {
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SMC_RET4(handle, dram_info.timing_info->fsp_table[1],
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1, 0, 0);
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}
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SMC_RET4(handle, dram_info.timing_info->fsp_table[1],
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2, 2, 4);
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case 2:
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if (!dram_info.bypass_mode) {
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SMC_RET4(handle, dram_info.timing_info->fsp_table[2],
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1, 0, 0);
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}
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SMC_RET4(handle, dram_info.timing_info->fsp_table[2],
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2, 3, 3);
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case 3:
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SMC_RET4(handle, dram_info.timing_info->fsp_table[3],
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1, 0, 0);
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default:
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SMC_RET1(handle, -3);
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}
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}
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int dram_dvfs_handler(uint32_t smc_fid, void *handle,
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u_register_t x1, u_register_t x2, u_register_t x3)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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unsigned int fsp_index = x1;
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uint32_t online_cores = x2;
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if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_COUNT) {
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SMC_RET1(handle, dram_info.num_fsp);
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} else if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_INFO) {
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return dram_dvfs_get_freq_info(handle, x2);
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} else if (x1 < 4) {
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wait_ddrc_hwffc_done = true;
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dsb();
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/* trigger the SGI IPI to info other cores */
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for (int i = 0; i < PLATFORM_CORE_COUNT; i++) {
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if (cpu_id != i && (online_cores & (0x1 << (i * 8)))) {
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plat_ic_raise_el3_sgi(0x8, i);
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}
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}
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/* make sure all the core in WFE */
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online_cores &= ~(0x1 << (cpu_id * 8));
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while (1) {
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if (online_cores == wfe_done) {
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break;
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}
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}
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/* flush the L1/L2 cache */
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dcsw_op_all(DCCSW);
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if (dram_info.dram_type == DDRC_LPDDR4) {
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lpddr4_swffc(&dram_info, dev_fsp, fsp_index);
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dev_fsp = (~dev_fsp) & 0x1;
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} else if (dram_info.dram_type == DDRC_DDR4) {
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ddr4_swffc(&dram_info, fsp_index);
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}
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dram_info.current_fsp = fsp_index;
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wait_ddrc_hwffc_done = false;
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wfe_done = 0;
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dsb();
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sev();
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isb();
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}
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SMC_RET1(handle, 0);
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}
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