GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <lib/mmio.h>
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#include <dram.h>
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#include <platform_def.h>
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#define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000)
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#define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004)
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#define PU_PGC_UP_TRG 0xf8
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#define PU_PGC_DN_TRG 0x104
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#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC)
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#define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800)
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#define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000)
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#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n))
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#define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n))
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#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50)
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#define DBGCAM_EMPTY 0x36000000
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void dram_enter_retention(void)
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{
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/* Wait DBGCAM to be empty */
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while (mmio_read_32(DDRC_DBGCAM(0)) != DBGCAM_EMPTY) {
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;
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}
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/* Block AXI ports from taking anymore transactions */
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mmio_write_32(DDRC_PCTRL_0(0), 0x0);
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/* Wait until all AXI ports are idle */
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while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) {
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;
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}
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/* Enter self refresh */
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mmio_write_32(DDRC_PWRCTL(0), 0xaa);
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/* LPDDR4 & DDR4/DDR3L need to check different status */
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if (dram_info.dram_type == DDRC_LPDDR4) {
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while (0x223 != (mmio_read_32(DDRC_STAT(0)) & 0x33f)) {
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;
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}
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} else {
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while (0x23 != (mmio_read_32(DDRC_STAT(0)) & 0x3f)) {
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;
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}
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}
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mmio_write_32(DDRC_DFIMISC(0), 0x0);
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mmio_write_32(DDRC_SWCTL(0), 0x0);
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mmio_write_32(DDRC_DFIMISC(0), 0x1f00);
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mmio_write_32(DDRC_DFIMISC(0), 0x1f20);
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while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) {
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;
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}
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mmio_write_32(DDRC_DFIMISC(0), 0x1f00);
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/* wait DFISTAT.dfi_init_complete to 1 */
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while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) {
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;
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}
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mmio_write_32(DDRC_SWCTL(0), 0x1);
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/* should check PhyInLP3 pub reg */
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dwc_ddrphy_apb_wr(0xd0000, 0x0);
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if (!(dwc_ddrphy_apb_rd(0x90028) & 0x1)) {
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INFO("PhyInLP3 = 1\n");
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}
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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#if defined(PLAT_imx8mq)
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/* pwrdnreqn_async adbm/adbs of ddr */
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mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1));
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while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) {
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;
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}
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mmio_setbits_32(GPC_PU_PWRHSK, BIT(1));
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#else
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/* pwrdnreqn_async adbm/adbs of ddr */
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mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2));
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while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) {
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;
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}
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mmio_setbits_32(GPC_PU_PWRHSK, BIT(2));
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#endif
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/* remove PowerOk */
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mmio_write_32(SRC_DDR1_RCR, 0x8F000008);
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mmio_write_32(CCM_CCGR(5), 0);
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mmio_write_32(CCM_SRC_CTRL(15), 2);
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/* enable the phy iso */
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mmio_setbits_32(IMX_GPC_BASE + 0xd40, 1);
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5));
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VERBOSE("dram enter retention\n");
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}
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void dram_exit_retention(void)
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{
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VERBOSE("dram exit retention\n");
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/* assert all reset */
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#if defined(PLAT_imx8mq)
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mmio_write_32(SRC_DDR2_RCR, 0x8F000003);
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mmio_write_32(SRC_DDR1_RCR, 0x8F00000F);
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mmio_write_32(SRC_DDR2_RCR, 0x8F000000);
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#else
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mmio_write_32(SRC_DDR1_RCR, 0x8F00001F);
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mmio_write_32(SRC_DDR1_RCR, 0x8F00000F);
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#endif
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mmio_write_32(CCM_CCGR(5), 2);
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mmio_write_32(CCM_SRC_CTRL(15), 2);
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/* disable iso */
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5));
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mmio_write_32(SRC_DDR1_RCR, 0x8F000006);
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/* wait dram pll locked */
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while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) {
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;
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}
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/* ddrc re-init */
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dram_umctl2_init(dram_info.timing_info);
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/*
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* Skips the DRAM init routine and starts up in selfrefresh mode
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* Program INIT0.skip_dram_init = 2'b11
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*/
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mmio_setbits_32(DDRC_INIT0(0), 0xc0000000);
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/* Keeps the controller in self-refresh mode */
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mmio_write_32(DDRC_PWRCTL(0), 0xaa);
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mmio_write_32(DDRC_DBG1(0), 0x0);
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mmio_write_32(SRC_DDR1_RCR, 0x8F000004);
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mmio_write_32(SRC_DDR1_RCR, 0x8F000000);
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/* before write Dynamic reg, sw_done should be 0 */
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mmio_write_32(DDRC_SWCTL(0), 0x0);
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#if !PLAT_imx8mn
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if (dram_info.dram_type == DDRC_LPDDR4) {
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mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */
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}
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#endif /* !PLAT_imx8mn */
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mmio_write_32(DDRC_DFIMISC(0), 0x0);
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/* dram phy re-init */
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dram_phy_init(dram_info.timing_info);
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/* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
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dwc_ddrphy_apb_wr(0xd0000, 0x0);
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while (dwc_ddrphy_apb_rd(0x20097)) {
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;
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}
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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/* before write Dynamic reg, sw_done should be 0 */
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mmio_write_32(DDRC_SWCTL(0), 0x0);
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mmio_write_32(DDRC_DFIMISC(0), 0x20);
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/* wait DFISTAT.dfi_init_complete to 1 */
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while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) {
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;
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}
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/* clear DFIMISC.dfi_init_start */
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mmio_write_32(DDRC_DFIMISC(0), 0x0);
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/* set DFIMISC.dfi_init_complete_en */
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mmio_write_32(DDRC_DFIMISC(0), 0x1);
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/* set SWCTL.sw_done to enable quasi-dynamic register programming */
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mmio_write_32(DDRC_SWCTL(0), 0x1);
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/* wait SWSTAT.sw_done_ack to 1 */
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while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) {
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;
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}
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mmio_write_32(DDRC_PWRCTL(0), 0x88);
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/* wait STAT to normal state */
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while (0x1 != (mmio_read_32(DDRC_STAT(0)) & 0x7)) {
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;
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}
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mmio_write_32(DDRC_PCTRL_0(0), 0x1);
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/* dis_auto-refresh is set to 0 */
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mmio_write_32(DDRC_RFSHCTL3(0), 0x0);
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/* should check PhyInLP3 pub reg */
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dwc_ddrphy_apb_wr(0xd0000, 0x0);
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if (!(dwc_ddrphy_apb_rd(0x90028) & 0x1)) {
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VERBOSE("PHYInLP3 = 0\n");
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}
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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}
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