GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <gpc.h>
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#include <imx8m_psci.h>
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#include <plat_imx8.h>
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#define MAX_PLL_NUM U(10)
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static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, };
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DEFINE_BAKERY_LOCK(gpc_lock);
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#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
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#pragma weak imx_set_cpu_pwr_off
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#pragma weak imx_set_cpu_pwr_on
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#pragma weak imx_set_cpu_lpm
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#pragma weak imx_set_cluster_powerdown
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void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint)
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{
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uint64_t temp_base;
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temp_base = (uint64_t) sec_entrypoint;
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temp_base >>= 2;
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mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3),
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((uint32_t)(temp_base >> 22) & 0xffff));
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mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4,
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((uint32_t)temp_base & 0x003fffff));
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}
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void imx_set_cpu_pwr_off(unsigned int core_id)
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{
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bakery_lock_get(&gpc_lock);
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/* enable the wfi power down of the core */
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mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));
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bakery_lock_release(&gpc_lock);
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/* assert the pcg pcr bit of the core */
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mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
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}
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void imx_set_cpu_pwr_on(unsigned int core_id)
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{
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bakery_lock_get(&gpc_lock);
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/* clear the wfi power down bit of the core */
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mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));
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bakery_lock_release(&gpc_lock);
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/* assert the ncpuporeset */
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mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));
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/* assert the pcg pcr bit of the core */
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mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
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/* sw power up the core */
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mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id));
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/* wait for the power up finished */
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while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0)
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;
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/* deassert the pcg pcr bit of the core */
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mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
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/* deassert the ncpuporeset */
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mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));
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}
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void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
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{
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bakery_lock_get(&gpc_lock);
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if (pdn) {
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/* enable the core WFI PDN & IRQ PUP */
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mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
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COREx_IRQ_WUP(core_id));
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/* assert the pcg pcr bit of the core */
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mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
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} else {
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/* disbale CORE WFI PDN & IRQ PUP */
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mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
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COREx_IRQ_WUP(core_id));
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/* deassert the pcg pcr bit of the core */
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mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
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}
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bakery_lock_release(&gpc_lock);
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}
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/*
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* the plat and noc can only be power up & down by slot method,
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* slot0: plat power down; slot1: noc power down; slot2: noc power up;
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* slot3: plat power up. plat's pup&pdn ack is used by default. if
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* noc is config to power down, then noc's pdn ack should be used.
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*/
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static void imx_a53_plat_slot_config(bool pdn)
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{
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if (pdn) {
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mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL);
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mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL);
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mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK |
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A53_PLAT_PUP_ACK);
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mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1);
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} else {
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mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL);
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mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL);
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mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |
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A53_DUMMY_PDN_ACK);
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mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1);
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}
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}
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void imx_set_cluster_standby(bool enter)
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{
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/*
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* Enable BIT 6 of A53 AD register to make sure system
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* don't enter LPM mode.
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*/
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if (enter)
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mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6));
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else
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mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6));
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}
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/* i.mx8mq need to override it */
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void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
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{
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uint32_t val;
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if (!is_local_state_run(power_state)) {
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/* config C0~1's LPM, enable a53 clock off in LPM */
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mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM,
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LPM_MODE(power_state));
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/* config C2-3's LPM */
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mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state));
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/* enable PLAT/SCU power down */
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val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
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val &= ~EN_L2_WFI_PDN;
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/* L2 cache memory is on in WAIT mode */
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if (is_local_state_off(power_state)) {
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val |= (L2PGE | EN_PLAT_PDN);
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imx_a53_plat_slot_config(true);
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}
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mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
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} else {
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/* clear the slot and ack for cluster power down */
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imx_a53_plat_slot_config(false);
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/* reverse the cluster level setting */
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mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM);
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mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf);
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/* clear PLAT/SCU power down */
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mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN),
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EN_L2_WFI_PDN);
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}
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}
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static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ISENABLER_SHIFT;
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return mmio_read_32(base + GICD_ISENABLER + (n << 2));
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}
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/*
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* gic's clock will be gated in system suspend, so gic has no ability to
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* to wakeup the system, we need to config the imr based on the irq
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* enable status in gic, then gpc will monitor the wakeup irq
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*/
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void imx_set_sys_wakeup(unsigned int last_core, bool pdn)
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{
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uint32_t irq_mask;
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uintptr_t gicd_base = PLAT_GICD_BASE;
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if (pdn)
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mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core),
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IRQ_SRC_A53_WUP);
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else
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mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP,
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A53_CORE_WUP_SRC(last_core));
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/* clear last core's IMR based on GIC's mask setting */
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for (int i = 0; i < IRQ_IMR_NUM; i++) {
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if (pdn)
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/* set the wakeup irq base GIC */
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irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1));
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else
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irq_mask = IMR_MASK_ALL;
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mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4,
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irq_mask);
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}
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}
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#pragma weak imx_noc_slot_config
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/*
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* this function only need to be override by platform
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* that support noc power down, for example: imx8mm.
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* otherwize, keep it empty.
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*/
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void imx_noc_slot_config(bool pdn)
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{
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}
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/* this is common for all imx8m soc */
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void imx_set_sys_lpm(unsigned int last_core, bool retention)
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{
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uint32_t val;
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val = mmio_read_32(IMX_GPC_BASE + SLPCR);
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val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
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SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE);
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if (retention)
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val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
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SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE);
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mmio_write_32(IMX_GPC_BASE + SLPCR, val);
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/* config the noc power down */
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imx_noc_slot_config(retention);
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/* config wakeup irqs' mask in gpc */
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imx_set_sys_wakeup(last_core, retention);
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}
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void imx_set_rbc_count(void)
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{
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mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN |
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(0x8 << SLPCR_RBC_COUNT_SHIFT));
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}
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void imx_clear_rbc_count(void)
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{
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mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN |
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(0x3f << SLPCR_RBC_COUNT_SHIFT));
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}
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struct pll_override {
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uint32_t reg;
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uint32_t override_mask;
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};
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struct pll_override pll[MAX_PLL_NUM] = {
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{.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), },
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{.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), },
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{.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), },
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{.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), },
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{.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), },
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{.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), },
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{.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), },
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{.reg = 0x94, .override_mask = 0x5555500, },
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{.reg = 0x104, .override_mask = 0x5555500, },
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{.reg = 0x114, .override_mask = 0x500, },
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};
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#define PLL_BYPASS BIT(4)
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void imx_anamix_override(bool enter)
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{
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unsigned int i;
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/*
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* bypass all the plls & enable the override bit before
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* entering DSM mode.
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*/
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for (i = 0U; i < MAX_PLL_NUM; i++) {
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if (enter) {
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mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS);
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mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask);
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} else {
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mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS);
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mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask);
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}
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}
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}
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int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3)
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{
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switch (x1) {
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case FSL_SIP_CONFIG_GPC_PM_DOMAIN:
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imx_gpc_pm_domain_enable(x2, x3);
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break;
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default:
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return SMC_UNK;
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}
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return 0;
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}
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