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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/gpc.c
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/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <platform_def.h>
#include <services/std_svc.h>
#include <gpc.h>
/* use wfi power down the core */
void imx_set_cpu_pwr_off(unsigned int core_id)
{
bakery_lock_get(&gpc_lock);
/* enable the wfi power down of the core */
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
(1 << (core_id + 20)));
bakery_lock_release(&gpc_lock);
/* assert the pcg pcr bit of the core */
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
};
/* if out of lpm, we need to do reverse steps */
void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
{
bakery_lock_get(&gpc_lock);
if (pdn) {
/* enable the core WFI PDN & IRQ PUP */
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
(1 << (core_id + 20)) | COREx_IRQ_WUP(core_id));
/* assert the pcg pcr bit of the core */
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
} else {
/* disable CORE WFI PDN & IRQ PUP */
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
COREx_IRQ_WUP(core_id));
/* deassert the pcg pcr bit of the core */
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
}
bakery_lock_release(&gpc_lock);
}
void imx_pup_pdn_slot_config(int last_core, bool pdn)
{
if (pdn) {
/* SLOT0 for A53 PLAT power down */
mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN);
/* SLOT1 for A53 PLAT power up */
mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP);
/* SLOT2 for A53 primary core power up */
mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core));
/* ACK setting: PLAT ACK for PDN, CORE ACK for PUP */
mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,
A53_PLAT_PDN_ACK | A53_PLAT_PUP_ACK);
} else {
mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF);
mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF);
mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF);
mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,
A53_DUMMY_PDN_ACK | A53_DUMMY_PUP_ACK);
}
}
void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
{
uint32_t val;
if (is_local_state_off(power_state)) {
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
val |= A53_LPM_STOP; /* enable C0-C1's STOP mode */
val &= ~CPU_CLOCK_ON_LPM; /* disable CPU clock in LPM mode */
mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
/* enable C2-3's STOP mode */
mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP);
/* enable PLAT/SCU power down */
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
val &= ~EN_L2_WFI_PDN;
val |= L2PGE | EN_PLAT_PDN;
val &= ~COREx_IRQ_WUP(last_core); /* disable IRQ PUP for last core */
val |= COREx_LPM_PUP(last_core); /* enable LPM PUP for last core */
mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
imx_pup_pdn_slot_config(last_core, true);
/* enable PLAT PGC */
mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);
} else {
/* clear PLAT PGC */
mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);
/* clear the slot and ack for cluster power down */
imx_pup_pdn_slot_config(last_core, false);
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */
val |= CPU_CLOCK_ON_LPM; /* disable cpu clock in LPM */
mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
/* set A53 LPM to RUN mode */
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK);
/* clear PLAT/SCU power down */
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
val |= EN_L2_WFI_PDN;
val &= ~(L2PGE | EN_PLAT_PDN);
val &= ~COREx_LPM_PUP(last_core); /* disable C0's LPM PUP */
mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
}
}
void imx_gpc_init(void)
{
uint32_t val;
int i;
/* mask all the interrupt by default */
for (i = 0; i < 4; i++) {
mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
}
/* Due to the hardware design requirement, need to make
* sure GPR interrupt(#32) is unmasked during RUN mode to
* avoid entering DSM mode by mistake.
*/
mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53, 0xFFFFFFFE);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53, 0xFFFFFFFE);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53, 0xFFFFFFFE);
mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53, 0xFFFFFFFE);
/* use external IRQs to wakeup C0~C3 from LPM */
val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
val |= IRQ_SRC_A53_WUP;
/* clear the MASTER0 LPM handshake */
val &= ~MASTER0_LPM_HSK;
mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
/* mask M4 DSM trigger if M4 is NOT enabled */
mmio_setbits_32(IMX_GPC_BASE + LPCR_M4, DSM_MODE_MASK);
/* set all mix/PU in A53 domain */
mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
/* set SCU timming */
mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
(0x59 << 10) | 0x5B | (0x2 << 20));
/* set DUMMY PDN/PUP ACK by default for A53 domain */
mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |
A53_DUMMY_PDN_ACK);
/* disable DSM mode by default */
mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK);
/*
* USB PHY power up needs to make sure RESET bit in SRC is clear,
* otherwise, the PU power up bit in GPC will NOT self-cleared.
* only need to do it once.
*/
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
/*
* for USB OTG, the limitation are:
* 1. before system clock config, the IPG clock run at 12.5MHz, delay time
* should be longer than 82us.
* 2. after system clock config, ipg clock run at 66.5MHz, delay time
* be longer that 15.3 us.
* Add 100us to make sure the USB OTG SRC is clear safely.
*/
udelay(100);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
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/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <stdbool.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
#include <drivers/arm/tzc380.h>
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <gpc.h>
#include <imx_aipstz.h>
#include <imx_uart.h>
#include <imx8m_caam.h>
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
static const mmap_region_t imx_mmap[] = {
MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
{0},
};
static const struct aipstz_cfg aipstz[] = {
{AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{0},
};
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
static uint32_t imx_soc_revision;
int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
u_register_t x3)
{
return imx_soc_revision;
}
#define ANAMIX_DIGPROG 0x6c
#define ROM_SOC_INFO_A0 0x800
#define ROM_SOC_INFO_B0 0x83C
#define OCOTP_SOC_INFO_B1 0x40
static void imx8mq_soc_info_init(void)
{
uint32_t rom_version;
uint32_t ocotp_val;
imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG);
rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0);
if (rom_version == 0x10)
return;
rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0);
if (rom_version == 0x20) {
imx_soc_revision &= ~0xff;
imx_soc_revision |= rom_version;
return;
}
/* 0xff0055aa is magic number for B1 */
ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1);
if (ocotp_val == 0xff0055aa) {
imx_soc_revision &= ~0xff;
imx_soc_revision |= 0x21;
return;
}
}
/* get SPSR for BL33 entry */
static uint32_t get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
unsigned long mode;
uint32_t spsr;
/* figure out what mode we enter the non-secure world */
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
el_status &= ID_AA64PFR0_ELX_MASK;
mode = (el_status) ? MODE_EL2 : MODE_EL1;
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
static void bl31_tz380_setup(void)
{
unsigned int val;
val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10);
if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
return;
tzc380_init(IMX_TZASC_BASE);
/*
* Need to substact offset 0x40000000 from CPU address when
* programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW
*/
tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
}
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
int i;
/* enable CSU NS access permission */
for (i = 0; i < 64; i++) {
mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
}
imx_aipstz_init(aipstz);
#if DEBUG_CONSOLE
static console_t console;
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
#endif
imx8m_caam_init();
/*
* tell BL3-1 where the non-secure software image is located
* and the entry state information.
*/
bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#if defined(SPD_opteed) || defined(SPD_trusty)
/* Populate entry point information for BL32 */
SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = 0;
/* Pass TEE base and size to bl33 */
bl33_image_ep_info.args.arg1 = BL32_BASE;
bl33_image_ep_info.args.arg2 = BL32_SIZE;
#ifdef SPD_trusty
bl32_image_ep_info.args.arg0 = BL32_SIZE;
bl32_image_ep_info.args.arg1 = BL32_BASE;
#else
/* Make sure memory is clean */
mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
#endif
#endif
bl31_tz380_setup();
}
void bl31_plat_arch_setup(void)
{
mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
MT_MEMORY | MT_RW | MT_SECURE);
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
MT_MEMORY | MT_RO | MT_SECURE);
/* Map TEE memory */
mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
mmap_add(imx_mmap);
#if USE_COHERENT_MEM
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE);
#endif
/* setup xlat table */
init_xlat_tables();
/* enable the MMU */
enable_mmu_el3(0);
}
void bl31_platform_setup(void)
{
generic_delay_timer_init();
/* init the GICv3 cpu and distributor interface */
plat_gic_driver_init();
plat_gic_init();
/* determine SOC revision for erratas */
imx8mq_soc_info_init();
/* gpc init */
imx_gpc_init();
}
entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
{
if (type == NON_SECURE)
return &bl33_image_ep_info;
if (type == SECURE)
return &bl32_image_ep_info;
return NULL;
}
unsigned int plat_get_syscnt_freq2(void)
{
return COUNTER_FREQUENCY;
}
void bl31_plat_runtime_setup(void)
{
return;
}
#ifdef SPD_trusty
void plat_trusty_set_boot_args(aapcs64_params_t *args)
{
args->arg0 = BL32_SIZE;
args->arg1 = BL32_BASE;
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
}
#endif
source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/imx8mq_psci.c
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/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdbool.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <gpc.h>
#include <imx8m_psci.h>
#include <plat_imx8.h>
int imx_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
int pwr_type = psci_get_pstate_type(power_state);
int state_id = psci_get_pstate_id(power_state);
if (pwr_lvl > PLAT_MAX_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
if (pwr_type == PSTATE_TYPE_STANDBY) {
CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
}
if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
}
return PSCI_E_SUCCESS;
}
void imx_domain_suspend(const psci_power_state_t *target_state)
{
uint64_t base_addr = BL31_BASE;
uint64_t mpidr = read_mpidr_el1();
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
/* disable the cpu interface */
plat_gic_cpuif_disable();
imx_set_cpu_secure_entry(core_id, base_addr);
imx_set_cpu_lpm(core_id, true);
} else {
dsb();
write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
isb();
}
if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
imx_set_cluster_powerdown(core_id, true);
else
imx_set_cluster_standby(true);
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
imx_set_sys_lpm(core_id, true);
}
}
void imx_domain_suspend_finish(const psci_power_state_t *target_state)
{
uint64_t mpidr = read_mpidr_el1();
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
/* check the system level status */
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
imx_set_sys_lpm(core_id, false);
imx_clear_rbc_count();
}
/* check the cluster level power status */
if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
imx_set_cluster_powerdown(core_id, false);
else
imx_set_cluster_standby(false);
/* check the core level power status */
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
/* clear the core lpm setting */
imx_set_cpu_lpm(core_id, false);
/* enable the gic cpu interface */
plat_gic_cpuif_enable();
} else {
write_scr_el3(read_scr_el3() & (~0x4));
isb();
}
}
void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
unsigned int i;
for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
}
static const plat_psci_ops_t imx_plat_psci_ops = {
.pwr_domain_on = imx_pwr_domain_on,
.pwr_domain_on_finish = imx_pwr_domain_on_finish,
.pwr_domain_off = imx_pwr_domain_off,
.validate_ns_entrypoint = imx_validate_ns_entrypoint,
.validate_power_state = imx_validate_power_state,
.cpu_standby = imx_cpu_standby,
.pwr_domain_suspend = imx_domain_suspend,
.pwr_domain_suspend_finish = imx_domain_suspend_finish,
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
.system_reset = imx_system_reset,
.system_reset2 = imx_system_reset2,
.system_off = imx_system_off,
};
/* export the platform specific psci ops */
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
imx_mailbox_init(sec_entrypoint);
/* sec_entrypoint is used for warm reset */
*psci_ops = &imx_plat_psci_ops;
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/include/gpc_reg.h
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/*
* Copyright 2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef GPC_REG_H
#define GPC_REG_H
#define LPCR_A53_BSC 0x0
#define LPCR_A53_BSC2 0x108
#define LPCR_A53_AD 0x4
#define LPCR_M4 0x8
#define SLPCR 0x14
#define MST_CPU_MAPPING 0x18
#define MLPCR 0x20
#define PGC_ACK_SEL_A53 0x24
#define IMR1_CORE0_A53 0x30
#define IMR1_CORE1_A53 0x40
#define IMR1_CORE2_A53 0x1C0
#define IMR1_CORE3_A53 0x1D0
#define IMR1_CORE0_M4 0x50
#define SLT0_CFG 0xB0
#define GPC_PU_PWRHSK 0x1FC
#define PGC_CPU_0_1_MAPPING 0xEC
#define CPU_PGC_UP_TRG 0xF0
#define PU_PGC_UP_TRG 0xF8
#define CPU_PGC_DN_TRG 0xFC
#define PU_PGC_DN_TRG 0x104
#define LPS_CPU1 0x114
#define A53_CORE0_PGC 0x800
#define A53_PLAT_PGC 0x900
#define PLAT_PGC_PCR 0x900
#define NOC_PGC_PCR 0xa40
#define PGC_SCU_TIMING 0x910
#define MASK_DSM_TRIGGER_A53 BIT(31)
#define IRQ_SRC_A53_WUP BIT(30)
#define IRQ_SRC_A53_WUP_SHIFT 30
#define IRQ_SRC_C1 BIT(29)
#define IRQ_SRC_C0 BIT(28)
#define IRQ_SRC_C3 BIT(23)
#define IRQ_SRC_C2 BIT(22)
#define CPU_CLOCK_ON_LPM BIT(14)
#define A53_CLK_ON_LPM BIT(14)
#define MASTER0_LPM_HSK BIT(6)
#define MASTER1_LPM_HSK BIT(7)
#define MASTER2_LPM_HSK BIT(8)
#define L2PGE BIT(31)
#define EN_L2_WFI_PDN BIT(5)
#define EN_PLAT_PDN BIT(4)
#define SLPCR_EN_DSM BIT(31)
#define SLPCR_RBC_EN BIT(30)
#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
#define SLPCR_VSTBY BIT(2)
#define SLPCR_SBYOS BIT(1)
#define SLPCR_BYPASS_PMIC_READY BIT(0)
#define SLPCR_RBC_COUNT_SHIFT 24
#define SLPCR_STBY_COUNT_SHFT 3
#define A53_DUMMY_PDN_ACK BIT(15)
#define A53_DUMMY_PUP_ACK BIT(31)
#define A53_PLAT_PDN_ACK BIT(2)
#define A53_PLAT_PUP_ACK BIT(18)
#define NOC_PDN_SLT_CTRL BIT(10)
#define NOC_PUP_SLT_CTRL BIT(11)
#define NOC_PGC_PDN_ACK BIT(3)
#define NOC_PGC_PUP_ACK BIT(19)
#define DDRMIX_PWR_REQ BIT(5)
#define DDRMIX_ADB400_SYNC BIT(1)
#define DDRMIX_ADB400_ACK BIT(18)
#define DDRMIX_PGC 0xd40
#define PLAT_PUP_SLT_CTRL BIT(9)
#define PLAT_PDN_SLT_CTRL BIT(8)
#define SLT_PLAT_PDN BIT(8)
#define SLT_PLAT_PUP BIT(9)
#define MASTER1_MAPPING BIT(1)
#define MASTER2_MAPPING BIT(2)
#define IRQ_IMR_NUM U(4)
#endif /* GPC_REG_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/include/imx_sec_def.h
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/*
* Copyright 2020-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IMX_SEC_DEF_H
#define IMX_SEC_DEF_H
/* RDC MDA index */
enum rdc_mda_idx {
RDC_MDA_A53 = 0,
RDC_MDA_M4 = 1,
RDC_MDA_PCIE_CTRL1 = 2,
RDC_MDA_PCIE_CTRL2 = 3,
RDC_MDA_VPU_DEC = 4,
RDC_MDA_LCDIF = 5,
RDC_MDA_CSI1 = 6,
RDC_MDA_CSI2 = 7,
RDC_MDA_Coresight = 8,
RDC_MDA_DAP = 9,
RDC_MDA_CAAM = 10,
RDC_MDA_SDMAp = 11,
RDC_MDA_SDMAb = 12,
RDC_MDA_APBHDMA = 13,
RDC_MDA_RAWNAND = 14,
RDC_MDA_uSDHC1 = 15,
RDC_MDA_uSDHC2 = 16,
RDC_MDA_DCSS = 17,
RDC_MDA_GPU = 18,
RDC_MDA_USB1 = 19,
RDC_MDA_USB2 = 20,
RDC_MDA_TESTPORT = 21,
RDC_MDA_ENET1_TX = 22,
RDC_MDA_ENET1_RX = 23,
RDC_MDA_SDMA2 = 24,
RDC_MDA_SDMA1 = 26,
};
/* RDC Peripherals index */
enum rdc_pdap_idx {
RDC_PDAP_GPIO1 = 0,
RDC_PDAP_GPIO2 = 1,
RDC_PDAP_GPIO3 = 2,
RDC_PDAP_GPIO4 = 3,
RDC_PDAP_GPIO5 = 4,
RDC_PDAP_ANA_TSENSOR = 6,
RDC_PDAP_ANA_OSC = 7,
RDC_PDAP_WDOG1 = 8,
RDC_PDAP_WDOG2 = 9,
RDC_PDAP_WDOG3 = 10,
RDC_PDAP_SDMA2 = 12,
RDC_PDAP_GPT1 = 13,
RDC_PDAP_GPT2 = 14,
RDC_PDAP_GPT3 = 15,
RDC_PDAP_ROMCP = 17,
RDC_PDAP_LCDIF = 18,
RDC_PDAP_IOMUXC = 19,
RDC_PDAP_IOMUXC_GPR = 20,
RDC_PDAP_OCOTP_CTRL = 21,
RDC_PDAP_ANATOP_PLL = 22,
RDC_PDAP_SNVS_HP = 23,
RDC_PDAP_CCM = 24,
RDC_PDAP_SRC = 25,
RDC_PDAP_GPC = 26,
RDC_PDAP_SEMAPHORE1 = 27,
RDC_PDAP_SEMAPHORE2 = 28,
RDC_PDAP_RDC = 29,
RDC_PDAP_CSU = 30,
RDC_PDAP_MST0 = 32,
RDC_PDAP_MST1 = 33,
RDC_PDAP_MST2 = 34,
RDC_PDAP_MST3 = 35,
RDC_PDAP_HDMI_SEC = 36,
RDC_PDAP_PWM1 = 38,
RDC_PDAP_PWM2 = 39,
RDC_PDAP_PWM3 = 40,
RDC_PDAP_PWM4 = 41,
RDC_PDAP_SysCounter_RD = 42,
RDC_PDAP_SysCounter_CMP = 43,
RDC_PDAP_SysCounter_CTRL = 44,
RDC_PDAP_HDMI_CTRL = 45,
RDC_PDAP_GPT6 = 46,
RDC_PDAP_GPT5 = 47,
RDC_PDAP_GPT4 = 48,
RDC_PDAP_TZASC = 56,
RDC_PDAP_MTR = 59,
RDC_PDAP_PERFMON1 = 60,
RDC_PDAP_PERFMON2 = 61,
RDC_PDAP_PLATFORM_CTRL = 62,
RDC_PDAP_QoSC = 63,
RDC_PDAP_MIPI_PHY = 64,
RDC_PDAP_MIPI_DSI = 65,
RDC_PDAP_I2C1 = 66,
RDC_PDAP_I2C2 = 67,
RDC_PDAP_I2C3 = 68,
RDC_PDAP_I2C4 = 69,
RDC_PDAP_UART4 = 70,
RDC_PDAP_MIPI_CSI1 = 71,
RDC_PDAP_MIPI_CSI_PHY1 = 72,
RDC_PDAP_CSI1 = 73,
RDC_PDAP_MU_A = 74,
RDC_PDAP_MU_B = 75,
RDC_PDAP_SEMAPHORE_HS = 76,
RDC_PDAP_SAI1 = 78,
RDC_PDAP_SAI6 = 80,
RDC_PDAP_SAI5 = 81,
RDC_PDAP_SAI4 = 82,
RDC_PDAP_USDHC1 = 84,
RDC_PDAP_USDHC2 = 85,
RDC_PDAP_MIPI_CSI2 = 86,
RDC_PDAP_MIPI_CSI_PHY2 = 87,
RDC_PDAP_CSI2 = 88,
RDC_PDAP_QSPI = 91,
RDC_PDAP_SDMA1 = 93,
RDC_PDAP_ENET1 = 94,
RDC_PDAP_SPDIF1 = 97,
RDC_PDAP_ECSPI1 = 98,
RDC_PDAP_ECSPI2 = 99,
RDC_PDAP_ECSPI3 = 100,
RDC_PDAP_UART1 = 102,
RDC_PDAP_UART3 = 104,
RDC_PDAP_UART2 = 105,
RDC_PDAP_SPDIF2 = 106,
RDC_PDAP_SAI2 = 107,
RDC_PDAP_SAI3 = 108,
RDC_PDAP_SPBA1 = 111,
RDC_PDAP_CAAM = 114,
RDC_PDAP_DDRC_SEC = 115,
RDC_PDAP_GIC_EXSC = 116,
RDC_PDAP_USB_EXSC = 117,
RDC_PDAP_OCRAM_TZ = 118,
RDC_PDAP_OCRAM_S_TZ = 119,
RDC_PDAP_VPU_SEC = 120,
RDC_PDAP_DAP_EXSC = 121,
RDC_PDAP_ROMCP_SEC = 122,
RDC_PDAP_APBHDMA_SEC = 123,
RDC_PDAP_M4_SEC = 124,
RDC_PDAP_QSPI_SEC = 125,
RDC_PDAP_GPU_EXSC = 126,
RDC_PDAP_PCIE = 127,
};
enum csu_csl_idx {
CSU_CSL_GPIO1 = 0,
CSU_CSL_GPIO2 = 1,
CSU_CSL_GPIO3 = 2,
CSU_CSL_GPIO4 = 3,
CSU_CSL_GPIO5 = 4,
CSU_CSL_ANA_TSENSOR = 6,
CSU_CSL_ANA_OSC = 7,
CSU_CSL_WDOG1 = 8,
CSU_CSL_WDOG2 = 9,
CSU_CSL_WDOG3 = 10,
CSU_CSL_SDMA2 = 12,
CSU_CSL_GPT1 = 13,
CSU_CSL_GPT2 = 14,
CSU_CSL_GPT3 = 15,
CSU_CSL_ROMCP = 17,
CSU_CSL_LCDIF = 18,
CSU_CSL_IOMUXC = 19,
CSU_CSL_IOMUXC_GPR = 20,
CSU_CSL_OCOTP_CTRL = 21,
CSU_CSL_ANATOP_PLL = 22,
CSU_CSL_SNVS_HP = 23,
CSU_CSL_CCM = 24,
CSU_CSL_SRC = 25,
CSU_CSL_GPC = 26,
CSU_CSL_SEMAPHORE1 = 27,
CSU_CSL_SEMAPHORE2 = 28,
CSU_CSL_RDC = 29,
CSU_CSL_CSU = 30,
CSU_CSL_MST0 = 32,
CSU_CSL_MST1 = 33,
CSU_CSL_MST2 = 34,
CSU_CSL_MST3 = 35,
CSU_CSL_HDMI_SEC = 36,
CSU_CSL_PWM1 = 38,
CSU_CSL_PWM2 = 39,
CSU_CSL_PWM3 = 40,
CSU_CSL_PWM4 = 41,
CSU_CSL_SysCounter_RD = 42,
CSU_CSL_SysCounter_CMP = 43,
CSU_CSL_SysCounter_CTRL = 44,
CSU_CSL_HDMI_CTRL = 45,
CSU_CSL_GPT6 = 46,
CSU_CSL_GPT5 = 47,
CSU_CSL_GPT4 = 48,
CSU_CSL_TZASC = 56,
CSU_CSL_MTR = 59,
CSU_CSL_PERFMON1 = 60,
CSU_CSL_PERFMON2 = 61,
CSU_CSL_PLATFORM_CTRL = 62,
CSU_CSL_QoSC = 63,
CSU_CSL_MIPI_PHY = 64,
CSU_CSL_MIPI_DSI = 65,
CSU_CSL_I2C1 = 66,
CSU_CSL_I2C2 = 67,
CSU_CSL_I2C3 = 68,
CSU_CSL_I2C4 = 69,
CSU_CSL_UART4 = 70,
CSU_CSL_MIPI_CSI1 = 71,
CSU_CSL_MIPI_CSI_PHY1 = 72,
CSU_CSL_CSI1 = 73,
CSU_CSL_MU_A = 74,
CSU_CSL_MU_B = 75,
CSU_CSL_SEMAPHORE_HS = 76,
CSU_CSL_SAI1 = 78,
CSU_CSL_SAI6 = 80,
CSU_CSL_SAI5 = 81,
CSU_CSL_SAI4 = 82,
CSU_CSL_USDHC1 = 84,
CSU_CSL_USDHC2 = 85,
CSU_CSL_MIPI_CSI2 = 86,
CSU_CSL_MIPI_CSI_PHY2 = 87,
CSU_CSL_CSI2 = 88,
CSU_CSL_QSPI = 91,
CSU_CSL_SDMA1 = 93,
CSU_CSL_ENET1 = 94,
CSU_CSL_SPDIF1 = 97,
CSU_CSL_ECSPI1 = 98,
CSU_CSL_ECSPI2 = 99,
CSU_CSL_ECSPI3 = 100,
CSU_CSL_UART1 = 102,
CSU_CSL_UART3 = 104,
CSU_CSL_UART2 = 105,
CSU_CSL_SPDIF2 = 106,
CSU_CSL_SAI2 = 107,
CSU_CSL_SAI3 = 108,
CSU_CSL_SPBA1 = 111,
CSU_CSL_MOD_EN3 = 112,
CSU_CSL_MOD_EN0 = 113,
CSU_CSL_CAAM = 114,
CSU_CSL_DDRC_SEC = 115,
CSU_CSL_GIC_EXSC = 116,
CSU_CSL_USB_EXSC = 117,
CSU_CSL_OCRAM_TZ = 118,
CSU_CSL_OCRAM_S_TZ = 119,
CSU_CSL_VPU_SEC = 120,
CSU_CSL_DAP_EXSC = 121,
CSU_CSL_ROMCP_SEC = 122,
CSU_CSL_APBHDMA_SEC = 123,
CSU_CSL_M4_SEC = 124,
CSU_CSL_QSPI_SEC = 125,
CSU_CSL_GPU_EXSC = 126,
CSU_CSL_PCIE = 127,
};
#endif /* IMX_SEC_DEF_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/include/platform_def.h
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/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
#define PLATFORM_STACK_SIZE 0x800
#define CACHE_WRITEBACK_GRANULE 64
#define PLAT_PRIMARY_CPU U(0x0)
#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
#define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
#define IMX_PWR_LVL0 MPIDR_AFFLVL0
#define IMX_PWR_LVL1 MPIDR_AFFLVL1
#define IMX_PWR_LVL2 MPIDR_AFFLVL2
#define PWR_DOMAIN_AT_MAX_LVL U(1)
#define PLAT_MAX_PWR_LVL U(2)
#define PLAT_MAX_OFF_STATE U(4)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_WAIT_RET_STATE PLAT_MAX_RET_STATE
#define PLAT_WAIT_OFF_STATE U(2)
#define PLAT_STOP_OFF_STATE U(3)
#define BL31_BASE U(0x910000)
#define BL31_LIMIT U(0x920000)
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000)
/* GICv3 base address */
#define PLAT_GICD_BASE U(0x38800000)
#define PLAT_GICR_BASE U(0x38880000)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
#ifdef SPD_trusty
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS 15
#else
#define MAX_XLAT_TABLES 4
#define MAX_MMAP_REGIONS 14
#endif
#define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */
#define IMX_BOOT_UART_BASE U(0x30860000)
#define IMX_BOOT_UART_CLK_IN_HZ 25000000 /* Select 25Mhz oscillator */
#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
#define PLAT_CRASH_UART_CLK_IN_HZ 25000000
#define IMX_CONSOLE_BAUDRATE 115200
#define IMX_AIPS_BASE U(0x30200000)
#define IMX_AIPS_SIZE U(0xC00000)
#define IMX_AIPS1_BASE U(0x30200000)
#define IMX_AIPS3_ARB_BASE U(0x30800000)
#define IMX_OCOTP_BASE U(0x30350000)
#define IMX_ANAMIX_BASE U(0x30360000)
#define IMX_CCM_BASE U(0x30380000)
#define IMX_SRC_BASE U(0x30390000)
#define IMX_GPC_BASE U(0x303a0000)
#define IMX_RDC_BASE U(0x303d0000)
#define IMX_CSU_BASE U(0x303e0000)
#define IMX_WDOG_BASE U(0x30280000)
#define IMX_SNVS_BASE U(0x30370000)
#define IMX_NOC_BASE U(0x32700000)
#define IMX_TZASC_BASE U(0x32F80000)
#define IMX_CAAM_BASE U(0x30900000)
#define IMX_IOMUX_GPR_BASE U(0x30340000)
#define IMX_DDRC_BASE U(0x3d400000)
#define IMX_DDRPHY_BASE U(0x3c000000)
#define IMX_DDR_IPS_BASE U(0x3d000000)
#define IMX_ROM_BASE U(0x00000000)
#define IMX_ROM_SIZE U(0x20000)
#define AIPSTZ1_BASE U(0x301f0000)
#define AIPSTZ2_BASE U(0x305f0000)
#define AIPSTZ3_BASE U(0x309f0000)
#define AIPSTZ4_BASE U(0x32df0000)
#define GPV_BASE U(0x32000000)
#define GPV_SIZE U(0x800000)
#define IMX_GIC_BASE PLAT_GICD_BASE
#define IMX_GIC_SIZE U(0x200000)
#define WDOG_WSR U(0x2)
#define WDOG_WCR_WDZST BIT(0)
#define WDOG_WCR_WDBG BIT(1)
#define WDOG_WCR_WDE BIT(2)
#define WDOG_WCR_WDT BIT(3)
#define WDOG_WCR_SRS BIT(4)
#define WDOG_WCR_WDA BIT(5)
#define WDOG_WCR_SRE BIT(6)
#define WDOG_WCR_WDW BIT(7)
#define SRC_A53RCR0 U(0x4)
#define SRC_A53RCR1 U(0x8)
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
#define SRC_GPR10_OFFSET U(0x98)
#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)
#define SNVS_LPCR_DP_EN BIT(5)
#define SNVS_LPCR_TOP BIT(6)
#define IOMUXC_GPR10 U(0x28)
#define GPR_TZASC_EN BIT(0)
#define GPR_TZASC_EN_LOCK BIT(16)
#define OCRAM_S_BASE U(0x00180000)
#define OCRAM_S_SIZE U(0x8000)
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
#define COUNTER_FREQUENCY 8333333 /* 25MHz / 3 */
#define DEBUG_CONSOLE 0
#define IMX_WDOG_B_RESET
source/trusted-firmware/trusted-firmware-a-2.8/plat/imx/imx8m/imx8mq/platform.mk
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#
# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Translation tables library
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_INCLUDES := -Iplat/imx/common/include \
-Iplat/imx/imx8m/include \
-Iplat/imx/imx8m/imx8mq/include
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
IMX_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c \
plat/imx/imx8m/imx8mq/imx8mq_psci.c \
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx8m_caam.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mq/gpc.c \
plat/imx/common/imx8_topology.c \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
plat/imx/common/imx_uart_console.S \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${XLAT_TABLES_LIB_SRCS} \
${IMX_GIC_SOURCES}
USE_COHERENT_MEM := 1
RESET_TO_BL31 := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
BL32_BASE ?= 0xfe000000
$(eval $(call add_define,BL32_BASE))
BL32_SIZE ?= 0x2000000
$(eval $(call add_define,BL32_SIZE))
ifeq (${SPD},trusty)
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif