GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright 2019-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_DDRC_H
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#define IMX_DDRC_H
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#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
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#define DDRC_DDR_SS_GPR0 0x3d000000
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/* DWC ddr umctl2 REGs offset*/
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/**********************/
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#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
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#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
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#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
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#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
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#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
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#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
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#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
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#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
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#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
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#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
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#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
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#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
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#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
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#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
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#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
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#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
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#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
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#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
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#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
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#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
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#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
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#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
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#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
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#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
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#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
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#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
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#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
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#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
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#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
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#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
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#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
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#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
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#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
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#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
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#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
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#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
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#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
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#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
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#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
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#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
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#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
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#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
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#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
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#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
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#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
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#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
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#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
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#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
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#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
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#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
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#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
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#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
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#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
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#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
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#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
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#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
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#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
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#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
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#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
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#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
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#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
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#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
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#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
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#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
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#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
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#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
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#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
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#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
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#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
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#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
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#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
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#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
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#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
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#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
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#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
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#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
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#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
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#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
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#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
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#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
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#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
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#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
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#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
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#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
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#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
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#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
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#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
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#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
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#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
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#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
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#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
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#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
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#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
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#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
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#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
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#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
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#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
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#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
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#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
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#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
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#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
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#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
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#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
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#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
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#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
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#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
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#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
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#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
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#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
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#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
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#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
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#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
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#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
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#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
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#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
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#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
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#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
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#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
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#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
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#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
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#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
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#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
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#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
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#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
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#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
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#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
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#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
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#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
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#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
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#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
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#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
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#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
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#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
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#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
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#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
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#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
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#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
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#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
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#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
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#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
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#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
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#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
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#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
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#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
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#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
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#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
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#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
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#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
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#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
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#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
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#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
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#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
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#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
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#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
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#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
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#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
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#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
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#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
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#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
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#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
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#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
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#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
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#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
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#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
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#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
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#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
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#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
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#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
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#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
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#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
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#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
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#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
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#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
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#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
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#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
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#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
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#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
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#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
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/* SHADOW registers */
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#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
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#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
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#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
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#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
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#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
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#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
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#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
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#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
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#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
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#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
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#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
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#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
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#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
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#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
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#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
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#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
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#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
|
||||
#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
|
||||
#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
|
||||
#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
|
||||
#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
|
||||
#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
|
||||
#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
|
||||
#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
|
||||
#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
|
||||
#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
|
||||
#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
|
||||
#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
|
||||
#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
|
||||
#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
|
||||
#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
|
||||
#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
|
||||
|
||||
#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
|
||||
#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
|
||||
#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
|
||||
#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
|
||||
#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
|
||||
#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
|
||||
#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
|
||||
#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
|
||||
#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
|
||||
#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
|
||||
#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
|
||||
#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
|
||||
#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
|
||||
#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
|
||||
#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
|
||||
#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
|
||||
#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
|
||||
#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
|
||||
#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
|
||||
#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
|
||||
#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
|
||||
#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
|
||||
#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
|
||||
#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
|
||||
#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
|
||||
#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
|
||||
#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
|
||||
#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
|
||||
#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
|
||||
#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
|
||||
#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
|
||||
#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
|
||||
|
||||
#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
|
||||
#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
|
||||
#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
|
||||
#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
|
||||
#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
|
||||
#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
|
||||
#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
|
||||
#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
|
||||
#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
|
||||
#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
|
||||
#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
|
||||
#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
|
||||
#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
|
||||
#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
|
||||
#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
|
||||
#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
|
||||
#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
|
||||
#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
|
||||
#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
|
||||
#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
|
||||
#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
|
||||
#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
|
||||
#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
|
||||
#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
|
||||
#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
|
||||
|
||||
#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
|
||||
#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
|
||||
#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
|
||||
#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
|
||||
#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
|
||||
#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
|
||||
#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
|
||||
#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
|
||||
#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
|
||||
#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
|
||||
#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
|
||||
|
||||
#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
|
||||
#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
|
||||
#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
|
||||
#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
|
||||
#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
|
||||
#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
|
||||
#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
|
||||
#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
|
||||
#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
|
||||
#define DRC_PERF_MON_DPCR_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x30)
|
||||
#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
|
||||
#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
|
||||
#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
|
||||
#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
|
||||
#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
|
||||
#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
|
||||
#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
|
||||
#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
|
||||
#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
|
||||
#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
|
||||
#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
|
||||
#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
|
||||
#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
|
||||
#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
|
||||
#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
|
||||
#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
|
||||
|
||||
#define dwc_ddrphy_apb_rd(addr) mmio_read_32(IMX_DDRPHY_BASE + 4 * (addr))
|
||||
#define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IMX_DDRPHY_BASE + 4 * (addr), val)
|
||||
|
||||
#endif /*IMX_DDRC_H */
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright 2019-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef DRAM_H
|
||||
#define DRAM_H
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <ddrc.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define DDRC_LPDDR4 BIT(5)
|
||||
#define DDRC_DDR4 BIT(4)
|
||||
#define DDRC_DDR3L BIT(0)
|
||||
#define DDR_TYPE_MASK U(0x3f)
|
||||
#define ACTIVE_RANK_MASK U(0x3)
|
||||
|
||||
/* reg & config param */
|
||||
struct dram_cfg_param {
|
||||
unsigned int reg;
|
||||
unsigned int val;
|
||||
};
|
||||
|
||||
struct dram_timing_info {
|
||||
/* umctl2 config */
|
||||
struct dram_cfg_param *ddrc_cfg;
|
||||
unsigned int ddrc_cfg_num;
|
||||
/* ddrphy config */
|
||||
struct dram_cfg_param *ddrphy_cfg;
|
||||
unsigned int ddrphy_cfg_num;
|
||||
/* ddr fsp train info */
|
||||
struct dram_fsp_msg *fsp_msg;
|
||||
unsigned int fsp_msg_num;
|
||||
/* ddr phy trained CSR */
|
||||
struct dram_cfg_param *ddrphy_trained_csr;
|
||||
unsigned int ddrphy_trained_csr_num;
|
||||
/* ddr phy PIE */
|
||||
struct dram_cfg_param *ddrphy_pie;
|
||||
unsigned int ddrphy_pie_num;
|
||||
/* initialized fsp table */
|
||||
unsigned int fsp_table[4];
|
||||
};
|
||||
|
||||
struct dram_info {
|
||||
int dram_type;
|
||||
unsigned int num_rank;
|
||||
uint32_t num_fsp;
|
||||
int current_fsp;
|
||||
int boot_fsp;
|
||||
bool bypass_mode;
|
||||
struct dram_timing_info *timing_info;
|
||||
/* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */
|
||||
uint32_t mr_table[3][8];
|
||||
};
|
||||
|
||||
extern struct dram_info dram_info;
|
||||
|
||||
void dram_info_init(unsigned long dram_timing_base);
|
||||
void dram_umctl2_init(struct dram_timing_info *timing);
|
||||
void dram_phy_init(struct dram_timing_info *timing);
|
||||
|
||||
/* dram retention */
|
||||
void dram_enter_retention(void);
|
||||
void dram_exit_retention(void);
|
||||
|
||||
void dram_clock_switch(unsigned int target_drate, bool bypass_mode);
|
||||
|
||||
/* dram frequency change */
|
||||
void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index);
|
||||
void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate);
|
||||
|
||||
#endif /* DRAM_H */
|
||||
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8M_GPC_H
|
||||
#define IMX8M_GPC_H
|
||||
|
||||
#include <gpc_reg.h>
|
||||
|
||||
/* helper macro */
|
||||
#define A53_LPM_MASK U(0xF)
|
||||
#define A53_LPM_WAIT U(0x5)
|
||||
#define A53_LPM_STOP U(0xA)
|
||||
#define LPM_MODE(local_state) ((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP)
|
||||
|
||||
#define DSM_MODE_MASK BIT(31)
|
||||
#define CORE_WKUP_FROM_GIC (IRQ_SRC_C0 | IRQ_SRC_C1 | IRQ_SRC_C2 | IRQ_SRC_C3)
|
||||
#define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2))
|
||||
#define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40)
|
||||
#define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16))
|
||||
#define COREx_IRQ_WUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 + 20)))
|
||||
#define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21)))
|
||||
#define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4)))
|
||||
#define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2))
|
||||
|
||||
#define IMR_MASK_ALL 0xffffffff
|
||||
|
||||
#define IMX_PD_DOMAIN(name, on) \
|
||||
{ \
|
||||
.pwr_req = name##_PWR_REQ, \
|
||||
.pgc_offset = name##_PGC, \
|
||||
.need_sync = false, \
|
||||
.always_on = (on), \
|
||||
}
|
||||
|
||||
#define IMX_MIX_DOMAIN(name, on) \
|
||||
{ \
|
||||
.pwr_req = name##_PWR_REQ, \
|
||||
.pgc_offset = name##_PGC, \
|
||||
.adb400_sync = name##_ADB400_SYNC, \
|
||||
.adb400_ack = name##_ADB400_ACK, \
|
||||
.need_sync = true, \
|
||||
.always_on = (on), \
|
||||
}
|
||||
|
||||
struct imx_pwr_domain {
|
||||
uint32_t pwr_req;
|
||||
uint32_t adb400_sync;
|
||||
uint32_t adb400_ack;
|
||||
uint32_t pgc_offset;
|
||||
bool need_sync;
|
||||
bool always_on;
|
||||
};
|
||||
|
||||
DECLARE_BAKERY_LOCK(gpc_lock);
|
||||
|
||||
/* function declare */
|
||||
void imx_gpc_init(void);
|
||||
void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint);
|
||||
void imx_set_cpu_pwr_off(unsigned int core_index);
|
||||
void imx_set_cpu_pwr_on(unsigned int core_index);
|
||||
void imx_set_cpu_lpm(unsigned int core_index, bool pdn);
|
||||
void imx_set_cluster_standby(bool retention);
|
||||
void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state);
|
||||
void imx_noc_slot_config(bool pdn);
|
||||
void imx_set_sys_wakeup(unsigned int last_core, bool pdn);
|
||||
void imx_set_sys_lpm(unsigned last_core, bool retention);
|
||||
void imx_set_rbc_count(void);
|
||||
void imx_clear_rbc_count(void);
|
||||
void imx_anamix_override(bool enter);
|
||||
void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on);
|
||||
|
||||
#endif /*IMX8M_GPC_H */
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2019, NXP. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8M_CAAM_H
|
||||
#define IMX8M_CAAM_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define CAAM_JR0MID (IMX_CAAM_BASE + 0x10)
|
||||
#define CAAM_JR1MID (IMX_CAAM_BASE + 0x18)
|
||||
#define CAAM_JR2MID (IMX_CAAM_BASE + 0x20)
|
||||
#define CAAM_NS_MID (0x1)
|
||||
|
||||
#define JR0_BASE (IMX_CAAM_BASE + 0x1000)
|
||||
|
||||
#define SM_P0_PERM (JR0_BASE + 0xa04)
|
||||
#define SM_P0_SMAG2 (JR0_BASE + 0xa08)
|
||||
#define SM_P0_SMAG1 (JR0_BASE + 0xa0c)
|
||||
#define SM_CMD (JR0_BASE + 0xbe4)
|
||||
|
||||
/* secure memory command */
|
||||
#define SMC_PAGE_SHIFT 16
|
||||
#define SMC_PART_SHIFT 8
|
||||
|
||||
#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
|
||||
#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
|
||||
|
||||
void imx8m_caam_init(void);
|
||||
|
||||
#endif /* IMX8M_CAAM_H */
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright 2020-2022 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_CSU_H
|
||||
#define IMX_CSU_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#define CSU_SEC_LEVEL_0 0xff
|
||||
#define CSU_SEC_LEVEL_1 0xbb
|
||||
#define CSU_SEC_LEVEL_2 0x3f
|
||||
#define CSU_SEC_LEVEL_3 0x3b
|
||||
#define CSU_SEC_LEVEL_4 0x33
|
||||
#define CSU_SEC_LEVEL_5 0x22
|
||||
#define CSU_SEC_LEVEL_6 0x03
|
||||
#define CSU_SEC_LEVEL_7 0x0
|
||||
|
||||
#define LOCKED 0x1
|
||||
#define UNLOCKED 0x0
|
||||
|
||||
#define CSLx_REG(x) (IMX_CSU_BASE + ((x) / 2) * 4)
|
||||
#define CSLx_LOCK(x) ((0x1 << (((x) % 2) * 16 + 8)))
|
||||
#define CSLx_CFG(x, n) ((x) << (((n) % 2) * 16))
|
||||
|
||||
#define CSU_HP_REG(x) (IMX_CSU_BASE + ((x) / 16) * 4 + 0x200)
|
||||
#define CSU_HP_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
|
||||
#define CSU_HP_CFG(x, n) ((x) << (((n) % 16) * 2))
|
||||
|
||||
#define CSU_SA_REG(x) (IMX_CSU_BASE + 0x218)
|
||||
#define CSU_SA_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
|
||||
#define CSU_SA_CFG(x, n) ((x) << (((n) % 16) * 2))
|
||||
|
||||
#define CSU_HPCONTROL_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x358)
|
||||
#define CSU_HPCONTROL_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1)))
|
||||
#define CSU_HPCONTROL_CFG(x, n) ((x) << (((n) % 16) * 2))
|
||||
|
||||
enum csu_cfg_type {
|
||||
CSU_INVALID,
|
||||
CSU_CSL,
|
||||
CSU_HP,
|
||||
CSU_SA,
|
||||
CSU_HPCONTROL,
|
||||
};
|
||||
|
||||
struct imx_csu_cfg {
|
||||
enum csu_cfg_type type;
|
||||
uint16_t idx;
|
||||
uint16_t lock : 1;
|
||||
uint16_t csl_level : 8;
|
||||
uint16_t hp : 1;
|
||||
uint16_t sa : 1;
|
||||
uint16_t hpctrl : 1;
|
||||
};
|
||||
|
||||
#define CSU_CSLx(i, level, lk) \
|
||||
{CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),}
|
||||
|
||||
#define CSU_HPx(i, val, lk) \
|
||||
{CSU_HP, .idx = (i), .hp = (val), .lock = (lk), }
|
||||
|
||||
#define CSU_SA(i, val, lk) \
|
||||
{CSU_SA, .idx = (i), .sa = (val), .lock = (lk), }
|
||||
|
||||
#define CSU_HPCTRL(i, val, lk) \
|
||||
{CSU_HPCONTROL, .idx = (i), .hpctrl = (val), .lock = (lk), }
|
||||
|
||||
void imx_csu_init(const struct imx_csu_cfg *csu_cfg);
|
||||
|
||||
#endif /* IMX_CSU_H */
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Linaro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8M_MEASURED_BOOT_H
|
||||
#define IMX8M_MEASURED_BOOT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
|
||||
int imx8m_set_nt_fw_info(size_t log_size, uintptr_t *ns_log_addr);
|
||||
|
||||
#endif /* IMX8M_MEASURED_BOOT_H */
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX8M_PSCI_H
|
||||
#define IMX8M_PSCI_H
|
||||
|
||||
#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
|
||||
#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
|
||||
#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
|
||||
|
||||
int imx_pwr_domain_on(u_register_t mpidr);
|
||||
void imx_pwr_domain_on_finish(const psci_power_state_t *target_state);
|
||||
void imx_pwr_domain_off(const psci_power_state_t *target_state);
|
||||
int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint);
|
||||
void imx_cpu_standby(plat_local_state_t cpu_state);
|
||||
void imx_domain_suspend(const psci_power_state_t *target_state);
|
||||
void imx_domain_suspend_finish(const psci_power_state_t *target_state);
|
||||
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
|
||||
int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
|
||||
|
||||
#endif /* IMX8M_PSCI_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_AIPSTZ_H
|
||||
#define IMX_AIPSTZ_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define AIPSTZ_MPR0 U(0x0)
|
||||
#define AIPSTZ_MPR1 U(0x4)
|
||||
|
||||
#define AIPSTZ_OPACR_NUM U(0x5)
|
||||
#define OPACR_OFFSET(i) U((i) * 4 + 0x40)
|
||||
|
||||
struct aipstz_cfg {
|
||||
uintptr_t base;
|
||||
uint32_t mpr0;
|
||||
uint32_t mpr1;
|
||||
uint32_t opacr[AIPSTZ_OPACR_NUM];
|
||||
};
|
||||
|
||||
void imx_aipstz_init(const struct aipstz_cfg *aipstz_cfg);
|
||||
|
||||
#endif /* IMX_AIPSTZ_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022 NXP. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IMX_RDC_H
|
||||
#define IMX_RDC_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include <imx_sec_def.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4)
|
||||
#define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4)
|
||||
#define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 0x10)
|
||||
#define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 0x10)
|
||||
#define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 0x10)
|
||||
|
||||
#define LCK BIT(31)
|
||||
#define SREQ BIT(30)
|
||||
#define ENA BIT(30)
|
||||
|
||||
#define DID0 U(0x0)
|
||||
#define DID1 U(0x1)
|
||||
#define DID2 U(0x2)
|
||||
#define DID3 U(0x3)
|
||||
|
||||
#define D3R BIT(7)
|
||||
#define D3W BIT(6)
|
||||
#define D2R BIT(5)
|
||||
#define D2W BIT(4)
|
||||
#define D1R BIT(3)
|
||||
#define D1W BIT(2)
|
||||
#define D0R BIT(1)
|
||||
#define D0W BIT(0)
|
||||
|
||||
union rdc_setting {
|
||||
uint32_t rdc_mda; /* Master Domain Assignment */
|
||||
uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */
|
||||
uint32_t rdc_mem_region[3]; /* Memory Region Access Control */
|
||||
};
|
||||
|
||||
enum rdc_type {
|
||||
RDC_INVALID,
|
||||
RDC_MDA,
|
||||
RDC_PDAP,
|
||||
RDC_MEM_REGION,
|
||||
};
|
||||
|
||||
struct imx_rdc_cfg {
|
||||
enum rdc_type type; /* config type Master, Peripheral or Memory region */
|
||||
int index;
|
||||
union rdc_setting setting;
|
||||
};
|
||||
|
||||
#define RDC_MDAn(i, mda) \
|
||||
{RDC_MDA, (i), .setting.rdc_mda = (mda), }
|
||||
#define RDC_PDAPn(i, pdap) \
|
||||
{RDC_PDAP, (i), .setting.rdc_pdap = (pdap), }
|
||||
|
||||
#define RDC_MEM_REGIONn(i, msa, mea, mrc) \
|
||||
{ RDC_MEM_REGION, (i), \
|
||||
.setting.rdc_mem_region[0] = (msa), \
|
||||
.setting.rdc_mem_region[1] = (mea), \
|
||||
.setting.rdc_mem_region[2] = (mrc), \
|
||||
}
|
||||
|
||||
void imx_rdc_init(const struct imx_rdc_cfg *cfg);
|
||||
|
||||
#endif /* IMX_RDC_H */
|
||||
|
||||
Reference in New Issue
Block a user