GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <platform_def.h>
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/* ---------------------------------------------
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* The below required platform porting macro
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* prints out relevant platform registers
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* whenever an unhandled exception is taken in
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* BL31.
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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.endm
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#endif /* PLAT_MACROS_S */
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+242
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/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/interrupt_props.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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/* Platform Type */
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#define PLAT_SOCFPGA_STRATIX10 1
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#define PLAT_SOCFPGA_AGILEX 2
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#define PLAT_SOCFPGA_N5X 3
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#define PLAT_SOCFPGA_EMULATOR 0
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/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
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#define PLAT_CPU_RELEASE_ADDR 0xffd12210
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/*
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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* is done and HPS should trigger warm reset via RMR_EL3.
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*/
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Magic word to indicate L2 reset is completed */
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#define L2_RESET_DONE_STATUS 0x1228E5E7
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/* Define next boot image name and offset */
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#define PLAT_NS_IMAGE_OFFSET 0x10000000
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#define PLAT_HANDOFF_OFFSET 0xFFE3F000
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/* SoCFPGA supports up to 124GB RAM */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x2000
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/* PSCI related constant */
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#define PLAT_NUM_POWER_DOMAINS 5
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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/* Interrupt related constant */
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#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15
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#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define DRAM_BASE (0x0)
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#define DRAM_SIZE (0x80000000)
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#define OCRAM_BASE (0xFFE00000)
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#define OCRAM_SIZE (0x00040000)
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#define MEM64_BASE (0x0100000000)
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#define MEM64_SIZE (0x1F00000000)
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#define DEVICE1_BASE (0x80000000)
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#define DEVICE1_SIZE (0x60000000)
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#define DEVICE2_BASE (0xF7000000)
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#define DEVICE2_SIZE (0x08E00000)
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#define DEVICE3_BASE (0xFFFC0000)
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#define DEVICE3_SIZE (0x00008000)
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define BL1_RO_BASE (0xffe00000)
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#define BL1_RO_LIMIT (0xffe0f000)
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#define BL1_RW_BASE (0xffe10000)
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#define BL1_RW_LIMIT (0xffe1ffff)
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#define BL1_RW_SIZE (0x14000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe1b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
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#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
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#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
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#define PLAT_SEC_WARM_ENTRY 0
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define MAX_XLAT_TABLES 8
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
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#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE
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#if PLAT_SOCFPGA_EMULATOR
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#define PLAT_BAUDRATE (4800)
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#define PLAT_UART_CLOCK (76800)
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#else
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#define PLAT_BAUDRATE (115200)
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#define PLAT_UART_CLOCK (100000000)
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#endif
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/*******************************************************************************
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* PHY related constants
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******************************************************************************/
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#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII
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#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
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#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_SYS_COUNTER_CONVERT_TO_MHZ (1000000)
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#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE
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#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE)
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#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp)
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#define MAX_IO_HANDLES 4
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#define MAX_IO_DEVICES 4
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#define MAX_IO_BLOCK_DEVICES 2
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#ifndef __ASSEMBLER__
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struct socfpga_bl31_params {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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#endif
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#endif /* PLATFORM_DEF_H */
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+24
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/*
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* Copyright (c) 2020, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_EMAC_H
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#define SOCFPGA_EMAC_H
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/* EMAC PHY Mode */
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#define PHY_INTERFACE_MODE_GMII_MII 0
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#define PHY_INTERFACE_MODE_RGMII 1
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#define PHY_INTERFACE_MODE_RMII 2
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#define PHY_INTERFACE_MODE_RESET 3
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/* Mask Definitions */
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#define PHY_INTF_SEL_MSK 0x3
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#define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8))
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void socfpga_emac_init(void);
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#endif /* SOCFPGA_EMAC_H */
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+39
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/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_F2SDRAMMANAGER_H
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#define SOCFPGA_F2SDRAMMANAGER_H
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#include "socfpga_plat_def.h"
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/* FPGA2SDRAM Register Map */
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#define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGINSTATUS0 0x14
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#define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTCLR0 0x54
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#define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTSET0 0x50
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#define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1))
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#define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4))
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#define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7))
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#define FLAGOUTSETCLR_F2SDRAM0_IDLEREQ (BIT(0))
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#define FLAGOUTSETCLR_F2SDRAM1_IDLEREQ (BIT(3))
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#define FLAGOUTSETCLR_F2SDRAM2_IDLEREQ (BIT(6))
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#define FLAGINTSTATUS_F2SDRAM0_IDLEACK (BIT(1))
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#define FLAGINTSTATUS_F2SDRAM1_IDLEACK (BIT(5))
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#define FLAGINTSTATUS_F2SDRAM2_IDLEACK (BIT(9))
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#define FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN (BIT(2))
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#define FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN (BIT(5))
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#define FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN (BIT(8))
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#define FLAGINTSTATUS_F2SOC_RESPEMPTY (BIT(3))
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#define FLAGINTSTATUS_F2SDRAM0_RESPEMPTY (BIT(3))
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#define FLAGINTSTATUS_F2SDRAM1_RESPEMPTY (BIT(7))
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#define FLAGINTSTATUS_F2SDRAM2_RESPEMPTY (BIT(11))
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#define SOCFPGA_F2SDRAMMGR(_reg) (SOCFPGA_F2SDRAMMGR_REG_BASE \
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+ (SOCFPGA_F2SDRAMMGR_##_reg))
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#endif /* SOCFPGA_F2SDRAMMGR_H */
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+316
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/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_FCS_H
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#define SOCFPGA_FCS_H
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/* FCS Definitions */
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#define FCS_RANDOM_WORD_SIZE 8U
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#define FCS_PROV_DATA_WORD_SIZE 44U
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#define FCS_SHA384_WORD_SIZE 12U
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#define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U)
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#define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U
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#define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U)
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#define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U)
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#define FCS_RANDOM_EXT_OFFSET 3
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#define FCS_MODE_DECRYPT 0x0
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#define FCS_MODE_ENCRYPT 0x1
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#define FCS_ENCRYPTION_DATA_0 0x10100
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#define FCS_DECRYPTION_DATA_0 0x10102
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#define FCS_OWNER_ID_OFFSET 0xC
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#define FCS_CRYPTION_CRYPTO_HEADER 0x07000000
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#define FCS_CRYPTION_RESP_WORD_SIZE 4U
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#define FCS_CRYPTION_RESP_SIZE_OFFSET 3U
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#define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4
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#define PSGSIGMA_SESSION_ID_ONE 0x1
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#define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF
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#define RESERVED_AS_ZERO 0x0
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/* FCS Single cert */
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#define FCS_BIG_CNTR_SEL 0x1
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#define FCS_SVN_CNTR_0_SEL 0x2
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#define FCS_SVN_CNTR_1_SEL 0x3
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#define FCS_SVN_CNTR_2_SEL 0x4
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#define FCS_SVN_CNTR_3_SEL 0x5
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#define FCS_BIG_CNTR_VAL_MAX 495U
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#define FCS_SVN_CNTR_VAL_MAX 64U
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/* FCS Attestation Cert Request Parameter */
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#define FCS_ATTEST_FIRMWARE_CERT 0x01
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#define FCS_ATTEST_DEV_ID_SELF_SIGN_CERT 0x02
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#define FCS_ATTEST_DEV_ID_ENROLL_CERT 0x04
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#define FCS_ATTEST_ENROLL_SELF_SIGN_CERT 0x08
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#define FCS_ATTEST_ALIAS_CERT 0x10
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#define FCS_ATTEST_CERT_MAX_REQ_PARAM 0xFF
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/* FCS Crypto Service */
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#define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U
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#define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U
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#define FCS_CS_KEY_RESP_STATUS_MASK 0xFF
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#define FCS_CS_KEY_RESP_STATUS_OFFSET 16U
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#define FCS_CS_FIELD_SIZE_MASK 0xFFFF
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#define FCS_CS_FIELD_FLAG_OFFSET 24
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#define FCS_CS_FIELD_FLAG_INIT BIT(0)
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#define FCS_CS_FIELD_FLAG_UPDATE BIT(1)
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#define FCS_CS_FIELD_FLAG_FINALIZE BIT(2)
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#define FCS_AES_MAX_DATA_SIZE 0x10000000 /* 256 MB */
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#define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */
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#define FCS_AES_CMD_MAX_WORD_SIZE 15U
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||||
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||||
#define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U
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#define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U
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#define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U
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#define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U
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#define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U
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||||
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#define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE 5U
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||||
#define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE 7U
|
||||
#define FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE 43U
|
||||
#define FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE 17U
|
||||
#define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U
|
||||
#define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U
|
||||
|
||||
#define FCS_CRYPTO_ECB_BUFFER_SIZE 12U
|
||||
#define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U
|
||||
#define FCS_CRYPTO_BLOCK_MODE_MASK 0x07
|
||||
#define FCS_CRYPTO_ECB_MODE 0x00
|
||||
#define FCS_CRYPTO_CBC_MODE 0x01
|
||||
#define FCS_CRYPTO_CTR_MODE 0x02
|
||||
|
||||
/* FCS Payload Structure */
|
||||
typedef struct fcs_rng_payload_t {
|
||||
uint32_t session_id;
|
||||
uint32_t context_id;
|
||||
uint32_t crypto_header;
|
||||
uint32_t size;
|
||||
} fcs_rng_payload;
|
||||
|
||||
typedef struct fcs_encrypt_payload_t {
|
||||
uint32_t first_word;
|
||||
uint32_t src_addr;
|
||||
uint32_t src_size;
|
||||
uint32_t dst_addr;
|
||||
uint32_t dst_size;
|
||||
} fcs_encrypt_payload;
|
||||
|
||||
typedef struct fcs_decrypt_payload_t {
|
||||
uint32_t first_word;
|
||||
uint32_t owner_id[2];
|
||||
uint32_t src_addr;
|
||||
uint32_t src_size;
|
||||
uint32_t dst_addr;
|
||||
uint32_t dst_size;
|
||||
} fcs_decrypt_payload;
|
||||
|
||||
typedef struct fcs_encrypt_ext_payload_t {
|
||||
uint32_t session_id;
|
||||
uint32_t context_id;
|
||||
uint32_t crypto_header;
|
||||
uint32_t src_addr;
|
||||
uint32_t src_size;
|
||||
uint32_t dst_addr;
|
||||
uint32_t dst_size;
|
||||
} fcs_encrypt_ext_payload;
|
||||
|
||||
typedef struct fcs_decrypt_ext_payload_t {
|
||||
uint32_t session_id;
|
||||
uint32_t context_id;
|
||||
uint32_t crypto_header;
|
||||
uint32_t owner_id[2];
|
||||
uint32_t src_addr;
|
||||
uint32_t src_size;
|
||||
uint32_t dst_addr;
|
||||
uint32_t dst_size;
|
||||
} fcs_decrypt_ext_payload;
|
||||
|
||||
typedef struct psgsigma_teardown_msg_t {
|
||||
uint32_t reserved_word;
|
||||
uint32_t magic_word;
|
||||
uint32_t session_id;
|
||||
} psgsigma_teardown_msg;
|
||||
|
||||
typedef struct fcs_cntr_set_preauth_payload_t {
|
||||
uint32_t first_word;
|
||||
uint32_t counter_value;
|
||||
} fcs_cntr_set_preauth_payload;
|
||||
|
||||
typedef struct fcs_cs_key_payload_t {
|
||||
uint32_t session_id;
|
||||
uint32_t reserved0;
|
||||
uint32_t reserved1;
|
||||
uint32_t key_id;
|
||||
} fcs_cs_key_payload;
|
||||
|
||||
typedef struct fcs_crypto_service_data_t {
|
||||
uint32_t session_id;
|
||||
uint32_t context_id;
|
||||
uint32_t key_id;
|
||||
uint32_t crypto_param_size;
|
||||
uint64_t crypto_param;
|
||||
uint8_t is_updated;
|
||||
} fcs_crypto_service_data;
|
||||
|
||||
typedef struct fcs_crypto_service_aes_data_t {
|
||||
uint32_t session_id;
|
||||
uint32_t context_id;
|
||||
uint32_t param_size;
|
||||
uint32_t key_id;
|
||||
uint32_t crypto_param[7];
|
||||
uint8_t is_updated;
|
||||
} fcs_crypto_service_aes_data;
|
||||
|
||||
/* Functions Definitions */
|
||||
|
||||
uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t size, uint32_t *send_id);
|
||||
uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
|
||||
uint32_t *send_id);
|
||||
uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
|
||||
uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
|
||||
int32_t counter_value,
|
||||
uint32_t test_bit,
|
||||
uint32_t *mbox_error);
|
||||
uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size,
|
||||
uint32_t dst_addr, uint32_t dst_size,
|
||||
uint32_t *send_id);
|
||||
|
||||
uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
|
||||
uint32_t dst_addr, uint32_t dst_size,
|
||||
uint32_t *send_id);
|
||||
|
||||
int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint32_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint32_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
|
||||
int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
|
||||
int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_create_cert_on_reload(uint32_t cert_request,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
|
||||
uint32_t *dst_size, uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_open_crypto_service_session(uint32_t *session_id,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_close_crypto_service_session(uint32_t session_id,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint32_t param_size,
|
||||
uint64_t param_data, uint32_t *mbox_error);
|
||||
int intel_fcs_get_digest_update_finalize(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint8_t is_finalised, uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint32_t param_size,
|
||||
uint64_t param_data, uint32_t *mbox_error);
|
||||
int intel_fcs_mac_verify_update_finalize(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t data_size, uint8_t is_finalised,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint32_t param_size,
|
||||
uint64_t param_data, uint32_t *mbox_error);
|
||||
int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint32_t param_size,
|
||||
uint64_t param_data, uint32_t *mbox_error);
|
||||
int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id,
|
||||
uint32_t context_id, uint32_t key_id,
|
||||
uint32_t param_size, uint64_t param_data,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id,
|
||||
uint32_t context_id, uint32_t src_addr,
|
||||
uint32_t src_size, uint64_t dst_addr,
|
||||
uint32_t *dst_size, uint8_t is_finalised,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id,
|
||||
uint32_t context_id, uint32_t key_id,
|
||||
uint32_t param_size, uint64_t param_data,
|
||||
uint32_t *mbox_error);
|
||||
int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id,
|
||||
uint32_t context_id, uint32_t src_addr,
|
||||
uint32_t src_size, uint64_t dst_addr,
|
||||
uint32_t *dst_size, uint32_t data_size,
|
||||
uint8_t is_finalised, uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint32_t param_size,
|
||||
uint64_t param_data, uint32_t *mbox_error);
|
||||
int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint32_t param_size,
|
||||
uint64_t param_data, uint32_t *mbox_error);
|
||||
int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t src_addr, uint32_t src_size,
|
||||
uint64_t dst_addr, uint32_t *dst_size,
|
||||
uint32_t *mbox_error);
|
||||
|
||||
int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id,
|
||||
uint32_t key_id, uint64_t param_addr,
|
||||
uint32_t param_size, uint32_t *mbox_error);
|
||||
int intel_fcs_aes_crypt_update_finalize(uint32_t session_id,
|
||||
uint32_t context_id, uint64_t src_addr,
|
||||
uint32_t src_size, uint64_t dst_addr,
|
||||
uint32_t dst_size, uint8_t is_finalised,
|
||||
uint32_t *send_id);
|
||||
|
||||
#endif /* SOCFPGA_FCS_H */
|
||||
+135
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef HANDOFF_H
|
||||
#define HANDOFF_H
|
||||
|
||||
#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
|
||||
#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
|
||||
#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
|
||||
#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
|
||||
#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
|
||||
#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
|
||||
#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
|
||||
|
||||
#include <socfpga_plat_def.h>
|
||||
|
||||
typedef struct handoff_t {
|
||||
/* header */
|
||||
uint32_t header_magic;
|
||||
uint32_t header_device;
|
||||
uint32_t _pad_0x08_0x10[2];
|
||||
|
||||
/* pinmux configuration - select */
|
||||
uint32_t pinmux_sel_magic;
|
||||
uint32_t pinmux_sel_length;
|
||||
uint32_t _pad_0x18_0x20[2];
|
||||
uint32_t pinmux_sel_array[96]; /* offset, value */
|
||||
|
||||
/* pinmux configuration - io control */
|
||||
uint32_t pinmux_io_magic;
|
||||
uint32_t pinmux_io_length;
|
||||
uint32_t _pad_0x1a8_0x1b0[2];
|
||||
uint32_t pinmux_io_array[96]; /* offset, value */
|
||||
|
||||
/* pinmux configuration - use fpga switch */
|
||||
uint32_t pinmux_fpga_magic;
|
||||
uint32_t pinmux_fpga_length;
|
||||
uint32_t _pad_0x338_0x340[2];
|
||||
uint32_t pinmux_fpga_array[42]; /* offset, value */
|
||||
uint32_t _pad_0x3e8_0x3f0[2];
|
||||
|
||||
/* pinmux configuration - io delay */
|
||||
uint32_t pinmux_delay_magic;
|
||||
uint32_t pinmux_delay_length;
|
||||
uint32_t _pad_0x3f8_0x400[2];
|
||||
uint32_t pinmux_iodelay_array[96]; /* offset, value */
|
||||
|
||||
/* clock configuration */
|
||||
|
||||
#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
|
||||
uint32_t clock_magic;
|
||||
uint32_t clock_length;
|
||||
uint32_t _pad_0x588_0x590[2];
|
||||
uint32_t main_pll_mpuclk;
|
||||
uint32_t main_pll_nocclk;
|
||||
uint32_t main_pll_cntr2clk;
|
||||
uint32_t main_pll_cntr3clk;
|
||||
uint32_t main_pll_cntr4clk;
|
||||
uint32_t main_pll_cntr5clk;
|
||||
uint32_t main_pll_cntr6clk;
|
||||
uint32_t main_pll_cntr7clk;
|
||||
uint32_t main_pll_cntr8clk;
|
||||
uint32_t main_pll_cntr9clk;
|
||||
uint32_t main_pll_nocdiv;
|
||||
uint32_t main_pll_pllglob;
|
||||
uint32_t main_pll_fdbck;
|
||||
uint32_t main_pll_pllc0;
|
||||
uint32_t main_pll_pllc1;
|
||||
uint32_t _pad_0x5cc_0x5d0[1];
|
||||
uint32_t per_pll_cntr2clk;
|
||||
uint32_t per_pll_cntr3clk;
|
||||
uint32_t per_pll_cntr4clk;
|
||||
uint32_t per_pll_cntr5clk;
|
||||
uint32_t per_pll_cntr6clk;
|
||||
uint32_t per_pll_cntr7clk;
|
||||
uint32_t per_pll_cntr8clk;
|
||||
uint32_t per_pll_cntr9clk;
|
||||
uint32_t per_pll_emacctl;
|
||||
uint32_t per_pll_gpiodiv;
|
||||
uint32_t per_pll_pllglob;
|
||||
uint32_t per_pll_fdbck;
|
||||
uint32_t per_pll_pllc0;
|
||||
uint32_t per_pll_pllc1;
|
||||
uint32_t hps_osc_clk_h;
|
||||
uint32_t fpga_clk_hz;
|
||||
#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
|
||||
uint32_t clock_magic;
|
||||
uint32_t clock_length;
|
||||
uint32_t _pad_0x588_0x590[2];
|
||||
uint32_t main_pll_mpuclk;
|
||||
uint32_t main_pll_nocclk;
|
||||
uint32_t main_pll_nocdiv;
|
||||
uint32_t main_pll_pllglob;
|
||||
uint32_t main_pll_fdbck;
|
||||
uint32_t main_pll_pllc0;
|
||||
uint32_t main_pll_pllc1;
|
||||
uint32_t main_pll_pllc2;
|
||||
uint32_t main_pll_pllc3;
|
||||
uint32_t main_pll_pllm;
|
||||
uint32_t per_pll_emacctl;
|
||||
uint32_t per_pll_gpiodiv;
|
||||
uint32_t per_pll_pllglob;
|
||||
uint32_t per_pll_fdbck;
|
||||
uint32_t per_pll_pllc0;
|
||||
uint32_t per_pll_pllc1;
|
||||
uint32_t per_pll_pllc2;
|
||||
uint32_t per_pll_pllc3;
|
||||
uint32_t per_pll_pllm;
|
||||
uint32_t alt_emacactr;
|
||||
uint32_t alt_emacbctr;
|
||||
uint32_t alt_emacptpctr;
|
||||
uint32_t alt_gpiodbctr;
|
||||
uint32_t alt_sdmmcctr;
|
||||
uint32_t alt_s2fuser0ctr;
|
||||
uint32_t alt_s2fuser1ctr;
|
||||
uint32_t alt_psirefctr;
|
||||
uint32_t hps_osc_clk_h;
|
||||
uint32_t fpga_clk_hz;
|
||||
uint32_t _pad_0x604_0x610[3];
|
||||
#endif
|
||||
/* misc configuration */
|
||||
uint32_t misc_magic;
|
||||
uint32_t misc_length;
|
||||
uint32_t _pad_0x618_0x620[2];
|
||||
} handoff;
|
||||
|
||||
int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
|
||||
int socfpga_get_handoff(handoff *hoff_ptr);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
+240
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOCFPGA_MBOX_H
|
||||
#define SOCFPGA_MBOX_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
|
||||
#define MBOX_OFFSET 0xffa30000
|
||||
|
||||
#define MBOX_ATF_CLIENT_ID 0x1U
|
||||
#define MBOX_MAX_JOB_ID 0xFU
|
||||
#define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U)
|
||||
#define MBOX_JOB_ID MBOX_MAX_JOB_ID
|
||||
#define MBOX_TEST_BIT BIT(31)
|
||||
|
||||
/* Mailbox Shared Memory Register Map */
|
||||
#define MBOX_CIN 0x00
|
||||
#define MBOX_ROUT 0x04
|
||||
#define MBOX_URG 0x08
|
||||
#define MBOX_INT 0x0C
|
||||
#define MBOX_COUT 0x20
|
||||
#define MBOX_RIN 0x24
|
||||
#define MBOX_STATUS 0x2C
|
||||
#define MBOX_CMD_BUFFER 0x40
|
||||
#define MBOX_RESP_BUFFER 0xC0
|
||||
|
||||
/* Mailbox SDM doorbell */
|
||||
#define MBOX_DOORBELL_TO_SDM 0x400
|
||||
#define MBOX_DOORBELL_FROM_SDM 0x480
|
||||
|
||||
|
||||
/* Mailbox commands */
|
||||
|
||||
#define MBOX_CMD_NOOP 0x00
|
||||
#define MBOX_CMD_SYNC 0x01
|
||||
#define MBOX_CMD_RESTART 0x02
|
||||
#define MBOX_CMD_CANCEL 0x03
|
||||
#define MBOX_CMD_VAB_SRC_CERT 0x0B
|
||||
#define MBOX_CMD_GET_IDCODE 0x10
|
||||
#define MBOX_CMD_GET_USERCODE 0x13
|
||||
#define MBOX_CMD_GET_CHIPID 0x12
|
||||
#define MBOX_CMD_REBOOT_HPS 0x47
|
||||
|
||||
/* Reconfiguration Commands */
|
||||
#define MBOX_CONFIG_STATUS 0x04
|
||||
#define MBOX_RECONFIG 0x06
|
||||
#define MBOX_RECONFIG_DATA 0x08
|
||||
#define MBOX_RECONFIG_STATUS 0x09
|
||||
|
||||
/* HWMON Commands */
|
||||
#define MBOX_HWMON_READVOLT 0x18
|
||||
#define MBOX_HWMON_READTEMP 0x19
|
||||
|
||||
|
||||
/* QSPI Commands */
|
||||
#define MBOX_CMD_QSPI_OPEN 0x32
|
||||
#define MBOX_CMD_QSPI_CLOSE 0x33
|
||||
#define MBOX_CMD_QSPI_SET_CS 0x34
|
||||
#define MBOX_CMD_QSPI_DIRECT 0x3B
|
||||
|
||||
/* RSU Commands */
|
||||
#define MBOX_GET_SUBPARTITION_TABLE 0x5A
|
||||
#define MBOX_RSU_STATUS 0x5B
|
||||
#define MBOX_RSU_UPDATE 0x5C
|
||||
#define MBOX_HPS_STAGE_NOTIFY 0x5D
|
||||
|
||||
/* FCS Command */
|
||||
#define MBOX_FCS_GET_PROVISION 0x7B
|
||||
#define MBOX_FCS_CNTR_SET_PREAUTH 0x7C
|
||||
#define MBOX_FCS_ENCRYPT_REQ 0x7E
|
||||
#define MBOX_FCS_DECRYPT_REQ 0x7F
|
||||
#define MBOX_FCS_RANDOM_GEN 0x80
|
||||
#define MBOX_FCS_AES_CRYPT_REQ 0x81
|
||||
#define MBOX_FCS_GET_DIGEST_REQ 0x82
|
||||
#define MBOX_FCS_MAC_VERIFY_REQ 0x83
|
||||
#define MBOX_FCS_ECDSA_HASH_SIGN_REQ 0x84
|
||||
#define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ 0x85
|
||||
#define MBOX_FCS_ECDSA_HASH_SIG_VERIFY 0x86
|
||||
#define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY 0x87
|
||||
#define MBOX_FCS_ECDSA_GET_PUBKEY 0x88
|
||||
#define MBOX_FCS_ECDH_REQUEST 0x89
|
||||
#define MBOX_FCS_OPEN_CS_SESSION 0xA0
|
||||
#define MBOX_FCS_CLOSE_CS_SESSION 0xA1
|
||||
#define MBOX_FCS_IMPORT_CS_KEY 0xA5
|
||||
#define MBOX_FCS_EXPORT_CS_KEY 0xA6
|
||||
#define MBOX_FCS_REMOVE_CS_KEY 0xA7
|
||||
#define MBOX_FCS_GET_CS_KEY_INFO 0xA8
|
||||
|
||||
/* PSG SIGMA Commands */
|
||||
#define MBOX_PSG_SIGMA_TEARDOWN 0xD5
|
||||
|
||||
/* Attestation Commands */
|
||||
#define MBOX_CREATE_CERT_ON_RELOAD 0x180
|
||||
#define MBOX_GET_ATTESTATION_CERT 0x181
|
||||
#define MBOX_ATTESTATION_SUBKEY 0x182
|
||||
#define MBOX_GET_MEASUREMENT 0x183
|
||||
|
||||
/* Miscellaneous commands */
|
||||
#define MBOX_GET_ROM_PATCH_SHA384 0x1B0
|
||||
|
||||
/* Mailbox Definitions */
|
||||
|
||||
#define CMD_DIRECT 0
|
||||
#define CMD_INDIRECT 1
|
||||
#define CMD_CASUAL 0
|
||||
#define CMD_URGENT 1
|
||||
|
||||
#define MBOX_WORD_BYTE 4U
|
||||
#define MBOX_RESP_BUFFER_SIZE 16
|
||||
#define MBOX_CMD_BUFFER_SIZE 32
|
||||
#define MBOX_INC_HEADER_MAX_WORD_SIZE 1024U
|
||||
|
||||
/* Execution states for HPS_STAGE_NOTIFY */
|
||||
#define HPS_EXECUTION_STATE_FSBL 0
|
||||
#define HPS_EXECUTION_STATE_SSBL 1
|
||||
#define HPS_EXECUTION_STATE_OS 2
|
||||
|
||||
/* Status Response */
|
||||
#define MBOX_RET_OK 0
|
||||
#define MBOX_RET_ERROR -1
|
||||
#define MBOX_NO_RESPONSE -2
|
||||
#define MBOX_WRONG_ID -3
|
||||
#define MBOX_BUFFER_FULL -4
|
||||
#define MBOX_BUSY -5
|
||||
#define MBOX_TIMEOUT -2047
|
||||
|
||||
/* Reconfig Status Response */
|
||||
#define RECONFIG_STATUS_STATE 0
|
||||
#define RECONFIG_STATUS_PIN_STATUS 2
|
||||
#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
|
||||
#define PIN_STATUS_NSTATUS (U(1) << 31)
|
||||
#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
|
||||
#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
|
||||
#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
|
||||
#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
|
||||
#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
|
||||
#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
|
||||
#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
|
||||
|
||||
|
||||
/* Mailbox Macros */
|
||||
|
||||
#define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \
|
||||
+ MBOX_WORD_BYTE * (ptr))
|
||||
|
||||
/* Mailbox interrupt flags and masks */
|
||||
#define MBOX_INT_FLAG_COE 0x1
|
||||
#define MBOX_INT_FLAG_RIE 0x2
|
||||
#define MBOX_INT_FLAG_UAE 0x100
|
||||
#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
|
||||
#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
|
||||
|
||||
/* Mailbox response and status */
|
||||
#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff)
|
||||
#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
|
||||
#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
|
||||
#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
|
||||
#define MBOX_STATUS_UA_MASK (1<<8)
|
||||
|
||||
/* Mailbox command and response */
|
||||
#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
|
||||
#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
|
||||
#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
|
||||
#define MBOX_INDIRECT(val) ((val) << 11)
|
||||
#define MBOX_CMD_MASK(header) ((header) & 0x7ff)
|
||||
|
||||
/* Mailbox payload */
|
||||
#define MBOX_DATA_MAX_LEN 0x3ff
|
||||
#define MBOX_PAYLOAD_FLAG_BUSY BIT(0)
|
||||
|
||||
/* RSU Macros */
|
||||
#define RSU_VERSION_ACMF BIT(8)
|
||||
#define RSU_VERSION_ACMF_MASK 0xff00
|
||||
|
||||
/* Config Status Macros */
|
||||
#define CONFIG_STATUS_WORD_SIZE 16U
|
||||
#define CONFIG_STATUS_FW_VER_OFFSET 1
|
||||
#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF
|
||||
|
||||
/* Data structure */
|
||||
|
||||
typedef struct mailbox_payload {
|
||||
uint32_t header;
|
||||
uint32_t data[MBOX_DATA_MAX_LEN];
|
||||
} mailbox_payload_t;
|
||||
|
||||
typedef struct mailbox_container {
|
||||
uint32_t flag;
|
||||
uint32_t index;
|
||||
mailbox_payload_t *payload;
|
||||
} mailbox_container_t;
|
||||
|
||||
/* Mailbox Function Definitions */
|
||||
|
||||
void mailbox_set_int(uint32_t interrupt_input);
|
||||
int mailbox_init(void);
|
||||
void mailbox_set_qspi_close(void);
|
||||
void mailbox_hps_qspi_enable(void);
|
||||
|
||||
int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
|
||||
unsigned int len, uint32_t urgent, uint32_t *response,
|
||||
unsigned int *resp_len);
|
||||
int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
|
||||
unsigned int len, unsigned int indirect);
|
||||
int mailbox_send_cmd_async_ext(uint32_t header_cmd, uint32_t *args,
|
||||
unsigned int len);
|
||||
int mailbox_read_response(uint32_t *job_id, uint32_t *response,
|
||||
unsigned int *resp_len);
|
||||
int mailbox_read_response_async(uint32_t *job_id, uint32_t *header,
|
||||
uint32_t *response, unsigned int *resp_len,
|
||||
uint8_t ignore_client_id);
|
||||
int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
|
||||
unsigned int *resp_len);
|
||||
|
||||
void mailbox_reset_cold(void);
|
||||
void mailbox_clear_response(void);
|
||||
|
||||
int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
|
||||
int intel_mailbox_is_fpga_not_ready(void);
|
||||
|
||||
int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
|
||||
int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
|
||||
int mailbox_rsu_update(uint32_t *flash_offset);
|
||||
int mailbox_hps_stage_notify(uint32_t execution_stage);
|
||||
int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
|
||||
int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
|
||||
|
||||
#endif /* SOCFPGA_MBOX_H */
|
||||
+95
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOCFPGA_NOC_H
|
||||
#define SOCFPGA_NOC_H
|
||||
|
||||
/* Macros */
|
||||
#define SCR_AXI_AP_MASK BIT(24)
|
||||
#define SCR_FPGA2SOC_MASK BIT(16)
|
||||
#define SCR_MPU_MASK BIT(0)
|
||||
#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
|
||||
| SCR_MPU_MASK)
|
||||
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
|
||||
|
||||
#define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \
|
||||
+ (SOCFPGA_CCU_NOC_##_ctrl##_##_dev))
|
||||
|
||||
#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
|
||||
+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
|
||||
|
||||
#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
|
||||
+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
|
||||
|
||||
/* L3 Interconnect Register Map */
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
|
||||
#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
|
||||
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
|
||||
#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
|
||||
|
||||
/* CCU NOC Register Map */
|
||||
|
||||
#define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688
|
||||
#define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628
|
||||
|
||||
#define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0)
|
||||
#define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1)
|
||||
|
||||
/* Function Definitions */
|
||||
|
||||
void enable_ns_peripheral_access(void);
|
||||
void enable_ns_bridge_access(void);
|
||||
void enable_ns_ocram_access(void);
|
||||
void enable_ocram_firewall(void);
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOCFPGA_PRIVATE_H
|
||||
#define SOCFPGA_PRIVATE_H
|
||||
|
||||
#include "socfpga_plat_def.h"
|
||||
|
||||
#define EMMC_DESC_SIZE (1<<20)
|
||||
|
||||
#define EMMC_INIT_PARAMS(base, clk) \
|
||||
{ .bus_width = MMC_BUS_WIDTH_4, \
|
||||
.clk_rate = (clk), \
|
||||
.desc_base = (base), \
|
||||
.desc_size = EMMC_DESC_SIZE, \
|
||||
.flags = 0, \
|
||||
.reg_base = SOCFPGA_MMC_REG_BASE \
|
||||
}
|
||||
|
||||
typedef enum {
|
||||
BOOT_SOURCE_FPGA = 0,
|
||||
BOOT_SOURCE_SDMMC,
|
||||
BOOT_SOURCE_NAND,
|
||||
BOOT_SOURCE_RSVD,
|
||||
BOOT_SOURCE_QSPI
|
||||
} boot_source_type;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
|
||||
void enable_nonsecure_access(void);
|
||||
|
||||
void socfpga_io_setup(int boot_source);
|
||||
|
||||
void socfgpa_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
|
||||
|
||||
void socfpga_configure_mmu_el1(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
|
||||
void socfpga_delay_timer_init(void);
|
||||
|
||||
void socfpga_gic_driver_init(void);
|
||||
|
||||
void socfpga_delay_timer_init_args(void);
|
||||
|
||||
uint32_t socfpga_get_spsr_for_bl32_entry(void);
|
||||
|
||||
uint32_t socfpga_get_spsr_for_bl33_entry(void);
|
||||
|
||||
unsigned long socfpga_get_ns_image_entrypoint(void);
|
||||
|
||||
void plat_secondary_cpus_bl31_entry(void);
|
||||
|
||||
#endif /* SOCFPGA_PRIVATE_H */
|
||||
+125
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOCFPGA_RESETMANAGER_H
|
||||
#define SOCFPGA_RESETMANAGER_H
|
||||
|
||||
#include "socfpga_plat_def.h"
|
||||
|
||||
#define SOCFPGA_BRIDGE_ENABLE BIT(0)
|
||||
#define SOCFPGA_BRIDGE_HAS_MASK BIT(1)
|
||||
|
||||
#define SOC2FPGA_MASK (1<<0)
|
||||
#define LWHPS2FPGA_MASK (1<<1)
|
||||
#define FPGA2SOC_MASK (1<<2)
|
||||
#define F2SDRAM0_MASK (1<<3)
|
||||
#define F2SDRAM1_MASK (1<<4)
|
||||
#define F2SDRAM2_MASK (1<<5)
|
||||
|
||||
/* Register Mapping */
|
||||
|
||||
#define SOCFPGA_RSTMGR_STAT 0x000
|
||||
#define SOCFPGA_RSTMGR_HDSKEN 0x010
|
||||
#define SOCFPGA_RSTMGR_HDSKREQ 0x014
|
||||
#define SOCFPGA_RSTMGR_HDSKACK 0x018
|
||||
#define SOCFPGA_RSTMGR_MPUMODRST 0x020
|
||||
#define SOCFPGA_RSTMGR_PER0MODRST 0x024
|
||||
#define SOCFPGA_RSTMGR_PER1MODRST 0x028
|
||||
#define SOCFPGA_RSTMGR_BRGMODRST 0x02c
|
||||
#define SOCFPGA_RSTMGR_COLDMODRST 0x034
|
||||
#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064
|
||||
|
||||
/* Field Mapping */
|
||||
|
||||
#define RSTMGR_PER0MODRST_EMAC0 0x00000001
|
||||
#define RSTMGR_PER0MODRST_EMAC1 0x00000002
|
||||
#define RSTMGR_PER0MODRST_EMAC2 0x00000004
|
||||
#define RSTMGR_PER0MODRST_USB0 0x00000008
|
||||
#define RSTMGR_PER0MODRST_USB1 0x00000010
|
||||
#define RSTMGR_PER0MODRST_NAND 0x00000020
|
||||
#define RSTMGR_PER0MODRST_SDMMC 0x00000080
|
||||
#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
|
||||
#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
|
||||
#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
|
||||
#define RSTMGR_PER0MODRST_USB0OCP 0x00000800
|
||||
#define RSTMGR_PER0MODRST_USB1OCP 0x00001000
|
||||
#define RSTMGR_PER0MODRST_NANDOCP 0x00002000
|
||||
#define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
|
||||
#define RSTMGR_PER0MODRST_DMA 0x00010000
|
||||
#define RSTMGR_PER0MODRST_SPIM0 0x00020000
|
||||
#define RSTMGR_PER0MODRST_SPIM1 0x00040000
|
||||
#define RSTMGR_PER0MODRST_SPIS0 0x00080000
|
||||
#define RSTMGR_PER0MODRST_SPIS1 0x00100000
|
||||
#define RSTMGR_PER0MODRST_DMAOCP 0x00200000
|
||||
#define RSTMGR_PER0MODRST_EMACPTP 0x00400000
|
||||
#define RSTMGR_PER0MODRST_DMAIF0 0x01000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF1 0x02000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF2 0x04000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF3 0x08000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF4 0x10000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF5 0x20000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF6 0x40000000
|
||||
#define RSTMGR_PER0MODRST_DMAIF7 0x80000000
|
||||
|
||||
#define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001
|
||||
#define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002
|
||||
#define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004
|
||||
#define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008
|
||||
#define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
|
||||
#define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
|
||||
#define RSTMGR_PER1MODRST_SPTIMER0 0x00000040
|
||||
#define RSTMGR_PER1MODRST_SPTIMER1 0x00000080
|
||||
#define RSTMGR_PER1MODRST_I2C0 0x00000100
|
||||
#define RSTMGR_PER1MODRST_I2C1 0x00000200
|
||||
#define RSTMGR_PER1MODRST_I2C2 0x00000400
|
||||
#define RSTMGR_PER1MODRST_I2C3 0x00000800
|
||||
#define RSTMGR_PER1MODRST_I2C4 0x00001000
|
||||
#define RSTMGR_PER1MODRST_UART0 0x00010000
|
||||
#define RSTMGR_PER1MODRST_UART1 0x00020000
|
||||
#define RSTMGR_PER1MODRST_GPIO0 0x01000000
|
||||
#define RSTMGR_PER1MODRST_GPIO1 0x02000000
|
||||
|
||||
#define RSTMGR_HDSKEN_FPGAHSEN 0x00000004
|
||||
#define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
|
||||
#define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
|
||||
#define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
|
||||
#define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
|
||||
#define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
|
||||
|
||||
#define RSTMGR_HDSKEQ_FPGAHSREQ 0x4
|
||||
|
||||
#define RSTMGR_BRGMODRST_SOC2FPGA 0x1
|
||||
#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2
|
||||
#define RSTMGR_BRGMODRST_FPGA2SOC 0x4
|
||||
#define RSTMGR_BRGMODRST_F2SSDRAM0 0x8
|
||||
#define RSTMGR_BRGMODRST_F2SSDRAM1 0x10
|
||||
#define RSTMGR_BRGMODRST_F2SSDRAM2 0x20
|
||||
#define RSTMGR_BRGMODRST_MPFE 0x40
|
||||
#define RSTMGR_BRGMODRST_DDRSCH 0x40
|
||||
|
||||
#define RSTMGR_HDSKREQ_FPGAHSREQ (BIT(2))
|
||||
#define RSTMGR_HDSKACK_FPGAHSACK_MASK (BIT(2))
|
||||
|
||||
/* Definitions */
|
||||
|
||||
#define RSTMGR_L2_MODRST 0x0100
|
||||
#define RSTMGR_HDSKEN_SET 0x010D
|
||||
|
||||
/* Macros */
|
||||
|
||||
#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \
|
||||
+ (SOCFPGA_RSTMGR_##_reg))
|
||||
#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field)
|
||||
|
||||
/* Function Declarations */
|
||||
|
||||
void deassert_peripheral_reset(void);
|
||||
void config_hps_hs_before_warm_reset(void);
|
||||
|
||||
int socfpga_bridges_enable(uint32_t mask);
|
||||
int socfpga_bridges_disable(uint32_t mask);
|
||||
|
||||
#endif /* SOCFPGA_RESETMANAGER_H */
|
||||
+217
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOCFPGA_SIP_SVC_H
|
||||
#define SOCFPGA_SIP_SVC_H
|
||||
|
||||
|
||||
/* SiP status response */
|
||||
#define INTEL_SIP_SMC_STATUS_OK 0
|
||||
#define INTEL_SIP_SMC_STATUS_BUSY 0x1
|
||||
#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
|
||||
#define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3
|
||||
#define INTEL_SIP_SMC_STATUS_ERROR 0x4
|
||||
#define INTEL_SIP_SMC_RSU_ERROR 0x7
|
||||
|
||||
/* SiP mailbox error code */
|
||||
#define GENERIC_RESPONSE_ERROR 0x3FF
|
||||
|
||||
/* SiP V2 command code range */
|
||||
#define INTEL_SIP_SMC_CMD_MASK 0xFFFF
|
||||
#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400
|
||||
#define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF
|
||||
|
||||
/* SiP V2 protocol header */
|
||||
#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF
|
||||
#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U
|
||||
#define INTEL_SIP_SMC_HEADER_CID_MASK 0xF
|
||||
#define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U
|
||||
#define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF
|
||||
#define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U
|
||||
|
||||
/* SMC SiP service function identifier for version 1 */
|
||||
|
||||
/* FPGA Reconfig */
|
||||
#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
|
||||
#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
|
||||
#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
|
||||
#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
|
||||
#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
|
||||
|
||||
/* FPGA Bitstream Flag */
|
||||
#define FLAG_PARTIAL_CONFIG BIT(0)
|
||||
#define FLAG_AUTHENTICATION BIT(1)
|
||||
#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
|
||||
== FLAG_##_type)
|
||||
|
||||
/* Secure Register Access */
|
||||
#define INTEL_SIP_SMC_REG_READ 0xC2000007
|
||||
#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
|
||||
#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
|
||||
|
||||
/* Remote System Update */
|
||||
#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
|
||||
#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
|
||||
#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
|
||||
#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
|
||||
#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
|
||||
#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
|
||||
#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
|
||||
#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
|
||||
#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
|
||||
#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
|
||||
|
||||
/* Hardware monitor */
|
||||
#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
|
||||
#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021
|
||||
#define TEMP_CHANNEL_MAX (1 << 15)
|
||||
#define VOLT_CHANNEL_MAX (1 << 15)
|
||||
|
||||
/* ECC */
|
||||
#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
|
||||
|
||||
/* Generic Command */
|
||||
#define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E
|
||||
#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F
|
||||
#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
|
||||
#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
|
||||
|
||||
#define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E
|
||||
|
||||
/* Mailbox Command */
|
||||
#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C
|
||||
#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
|
||||
|
||||
/* FPGA Crypto Services */
|
||||
#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A
|
||||
#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F
|
||||
#define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B
|
||||
#define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090
|
||||
#define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C
|
||||
#define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D
|
||||
#define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E
|
||||
#define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F
|
||||
#define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064
|
||||
#define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065
|
||||
#define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066
|
||||
#define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067
|
||||
#define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068
|
||||
#define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069
|
||||
#define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E
|
||||
#define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F
|
||||
#define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070
|
||||
#define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071
|
||||
#define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072
|
||||
#define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073
|
||||
#define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074
|
||||
#define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075
|
||||
#define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076
|
||||
#define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077
|
||||
#define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078
|
||||
#define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079
|
||||
#define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A
|
||||
#define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B
|
||||
#define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089
|
||||
#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B
|
||||
#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
|
||||
#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
|
||||
|
||||
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
|
||||
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
|
||||
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
|
||||
#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF
|
||||
|
||||
/* ECC DBE */
|
||||
#define WARM_RESET_WFI_FLAG BIT(31)
|
||||
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
|
||||
SYSMGR_ECC_DDR0_MASK |\
|
||||
SYSMGR_ECC_DDR1_MASK)
|
||||
|
||||
/* Non-mailbox SMC Call */
|
||||
#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
|
||||
|
||||
/**
|
||||
* SMC SiP service function identifier for version 2
|
||||
* Command code from 0x400 ~ 0x4FF
|
||||
*/
|
||||
|
||||
/* V2: Non-mailbox function identifier */
|
||||
#define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400
|
||||
#define INTEL_SIP_SMC_V2_REG_READ 0xC2000401
|
||||
#define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402
|
||||
#define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403
|
||||
#define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404
|
||||
|
||||
/* V2: Mailbox function identifier */
|
||||
#define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420
|
||||
#define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
#define SIP_SVC_CALL_COUNT 0x8200ff00
|
||||
#define SIP_SVC_UID 0x8200ff01
|
||||
#define SIP_SVC_VERSION 0x8200ff03
|
||||
|
||||
/* SiP Service Calls version numbers */
|
||||
#define SIP_SVC_VERSION_MAJOR 1
|
||||
#define SIP_SVC_VERSION_MINOR 0
|
||||
|
||||
|
||||
/* Structure Definitions */
|
||||
struct fpga_config_info {
|
||||
uint32_t addr;
|
||||
int size;
|
||||
int size_written;
|
||||
uint32_t write_requested;
|
||||
int subblocks_sent;
|
||||
int block_number;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NO_REQUEST = 0,
|
||||
RECONFIGURATION,
|
||||
BITSTREAM_AUTH
|
||||
} config_type;
|
||||
|
||||
/* Function Definitions */
|
||||
bool is_size_4_bytes_aligned(uint32_t size);
|
||||
bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
|
||||
|
||||
/* ECC DBE */
|
||||
bool cold_reset_for_ecc_dbe(void);
|
||||
uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
|
||||
|
||||
/* Secure register access */
|
||||
uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval);
|
||||
uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
|
||||
uint32_t *retval);
|
||||
uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
|
||||
uint32_t val, uint32_t *retval);
|
||||
|
||||
/* Miscellaneous HPS services */
|
||||
uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask);
|
||||
|
||||
/* SiP Service handler for version 2 */
|
||||
uintptr_t sip_smc_handler_v2(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags);
|
||||
|
||||
#endif /* SOCFPGA_SIP_SVC_H */
|
||||
+54
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOCFPGA_SYSTEMMANAGER_H
|
||||
#define SOCFPGA_SYSTEMMANAGER_H
|
||||
|
||||
#include "socfpga_plat_def.h"
|
||||
|
||||
/* System Manager Register Map */
|
||||
|
||||
#define SOCFPGA_SYSMGR_SDMMC 0x28
|
||||
|
||||
#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
|
||||
|
||||
#define SOCFPGA_SYSMGR_EMAC_0 0x44
|
||||
#define SOCFPGA_SYSMGR_EMAC_1 0x48
|
||||
#define SOCFPGA_SYSMGR_EMAC_2 0x4c
|
||||
#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
|
||||
|
||||
#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
|
||||
#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
|
||||
#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
|
||||
#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
|
||||
#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0
|
||||
#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4
|
||||
|
||||
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
|
||||
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
|
||||
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
|
||||
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
|
||||
#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
|
||||
|
||||
/* Field Masking */
|
||||
|
||||
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
|
||||
#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
|
||||
|
||||
#define IDLE_DATA_LWSOC2FPGA BIT(4)
|
||||
#define IDLE_DATA_SOC2FPGA BIT(0)
|
||||
#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
|
||||
|
||||
#define SYSMGR_ECC_OCRAM_MASK BIT(1)
|
||||
#define SYSMGR_ECC_DDR0_MASK BIT(16)
|
||||
#define SYSMGR_ECC_DDR1_MASK BIT(17)
|
||||
|
||||
/* Macros */
|
||||
|
||||
#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
|
||||
+ (SOCFPGA_SYSMGR_##_reg))
|
||||
|
||||
#endif /* SOCFPGA_SYSTEMMANAGER_H */
|
||||
Reference in New Issue
Block a user