GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
+15
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) Lotus. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
|
||||
.section .rodata.gic_reg_name, "aS"
|
||||
.macro plat_crash_print_regs
|
||||
nop
|
||||
.endm
|
||||
|
||||
Executable
+52
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (c) Lotus. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_PRIVATE_H__
|
||||
#define __PLAT_PRIVATE_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* For socs pm ops
|
||||
******************************************************************************/
|
||||
struct lotus_pm_ops_cb {
|
||||
int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint);
|
||||
int (*cores_pwr_dm_off)(void);
|
||||
int (*cores_pwr_dm_on_finish)(void);
|
||||
int (*cores_pwr_dm_suspend)(void);
|
||||
int (*cores_pwr_dm_resume)(void);
|
||||
int (*sys_pwr_dm_suspend)(void);
|
||||
int (*sys_pwr_dm_resume)(void);
|
||||
int (*sys_gbl_soft_reset)(void);
|
||||
void (*sys_gbl_standby)(void);
|
||||
void (*sys_gbl_poweroff)(void);
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long,
|
||||
unsigned long);
|
||||
|
||||
|
||||
void plat_delay_timer_init(void);
|
||||
|
||||
void plat_lotus_gic_driver_init(void);
|
||||
void plat_lotus_gic_init(void);
|
||||
void plat_lotus_gic_cpuif_enable(void);
|
||||
void plat_lotus_gic_cpuif_disable(void);
|
||||
void plat_lotus_gic_pcpu_init(void);
|
||||
|
||||
void plat_lotus_pmc_init(void);
|
||||
void plat_setup_lotus_pm_ops(struct lotus_pm_ops_cb *ops);
|
||||
void lotus_suspend_save_param(void);
|
||||
void lotus_cpu_suspend(void);
|
||||
void lotus_sys_suspend(void);
|
||||
void lotus_invalidate_icache(void);
|
||||
|
||||
extern unsigned int lotus_sys_suspend_size;
|
||||
#endif /* __PLAT_PRIVATE_H__ */
|
||||
Executable
+77
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) Lotus. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_DEF_H__
|
||||
#define __PLATFORM_DEF_H__
|
||||
|
||||
#include <common_def.h>
|
||||
#include <arch.h>
|
||||
#include <xmfalcon_def.h>
|
||||
|
||||
#define DEBUG_XLAT_TABLE 0
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform binary types for linking
|
||||
******************************************************************************/
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if DEBUG_XLAT_TABLE
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
#elif IMAGE_BL1
|
||||
#define PLATFORM_STACK_SIZE 0x440
|
||||
#elif IMAGE_BL2
|
||||
#define PLATFORM_STACK_SIZE 0x400
|
||||
#elif IMAGE_BL31
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
#elif IMAGE_BL32
|
||||
#define PLATFORM_STACK_SIZE 0x440
|
||||
#endif
|
||||
|
||||
|
||||
/* Cache line size */
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/* Power domain */
|
||||
#define PLATFORM_CLUSTER_COUNT 1
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER)
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER_COUNT + 1)
|
||||
/* Power states */
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
|
||||
/* BL31 specific defines. */
|
||||
#define BL31_SIZE 0x32000
|
||||
#define BL31_BASE 0x40008000
|
||||
#define BL31_LIMIT (BL31_BASE + BL31_SIZE - 1)
|
||||
|
||||
/* Platform specific page table and MMU setup */
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define MAX_XLAT_TABLES 6
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
|
||||
/* GICD and GICC and GICR base */
|
||||
#define PLAT_LOTUS_GICD_BASE XMFALCON_GICD_BASE
|
||||
#define PLAT_LOTUS_GICC_BASE XMFALCON_GICC_BASE
|
||||
|
||||
|
||||
#define PLAT_LOTUS_UART_BASE XMFALCON_UART0_BASE
|
||||
#define PLAT_LOTUS_UART_CLOCK XMFALCON_UART_CLK
|
||||
#define PLAT_LOTUS_UART_CLOCK_IN_HZ XMFALCON_UART_CLK_IN_HZ
|
||||
#define PLAT_LOTUS_UART_BAUDRATE XMFALCON_BAUDRATE
|
||||
|
||||
#define PLAT_LOTUS_PRIMARY_CPU 0x0
|
||||
|
||||
#endif /* __PLATFORM_DEF_H__ */
|
||||
Executable
+67
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) Lotus. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __XMFALCON_H__
|
||||
#define __XMFALCON_H__
|
||||
|
||||
|
||||
/* SRAM mem */
|
||||
#define SRAM_BASE 0x04010000
|
||||
#define SRAM_SIZE 0x10000
|
||||
|
||||
/* IO mem */
|
||||
#define DEVICE_BASE 0x04020000
|
||||
#define DEVICE_SIZE 0x10FE0000
|
||||
|
||||
/* DDR mem */
|
||||
#define DRAM_NS_BASE 0x40000000
|
||||
#define DRAM_NS_SIZE 0x80000000
|
||||
|
||||
/* UART */
|
||||
#define XMFALCON_UART0_BASE (0x12040000)
|
||||
#define XMFALCON_BAUDRATE (115200)
|
||||
#define XMFALCON_UART_CLK (24000000)
|
||||
#define XMFALCON_UART_CLK_IN_HZ (XMFALCON_UART_CLK / 1000000)
|
||||
|
||||
/* System counter */
|
||||
#ifdef CONFIG_FPGA
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS 30000000
|
||||
#else
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS 50000000
|
||||
#endif
|
||||
#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS / 1000000)
|
||||
|
||||
/* Timer */
|
||||
#define TIMER0_REG_BASE 0x12000000
|
||||
#define REG_TIMER_RELOAD 0x0
|
||||
#define REG_TIMER_VALUE 0x4
|
||||
#define REG_TIMER_CONTROL 0x8
|
||||
|
||||
#define LOTUS_TIMER_BASE TIMER0_REG_BASE
|
||||
#define LOTUS_TIMER_VALUE (LOTUS_TIMER_BASE + REG_TIMER_VALUE)
|
||||
#define LOTUS_TIMER_FREQ_IN_TICKS 24000000
|
||||
#define LOTUS_TIMER_FREQ_IN_MHZ (LOTUS_TIMER_FREQ_IN_TICKS / 1000000)
|
||||
|
||||
/* GIC-400 */
|
||||
#define XMFALCON_GICD_BASE (0x10401000)
|
||||
#define XMFALCON_GICC_BASE (0x10402000)
|
||||
|
||||
/* Acpu suspend firmware load address */
|
||||
#define LOTUS_PM_CODE_START SRAM_BASE
|
||||
#define LOTUS_PM_CODE_SIZE SRAM_SIZE
|
||||
|
||||
#define STR_FLAG_ADDR 0x120f0048
|
||||
#define STR_FLAG_VALUE 0xC3321142
|
||||
#define DRAM_SIZE_ADDR 0x120200C0
|
||||
|
||||
#define PWR_CTRL0_ADDRESS 0x120f0010
|
||||
#define PWM_CTRL0_STANDBY BIT(0)
|
||||
#define PWM_CTRL0_POWERDOWN BIT(1)
|
||||
|
||||
#define REG_MISC_CTRL129 0x12029108
|
||||
|
||||
#endif /* __XMFALCON_H__ */
|
||||
Reference in New Issue
Block a user