GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

source/trusted-firmware/trusted-firmware-a-2.8/plat/lotus/xmfalcon/resume_entry_32bit/Makefile

@@ -0,0 +1,67 @@
+#===============================================================================
+# export variables
+#===============================================================================
+
+TARGET := resume_entry_32bit
+LOAD_ADDR = 0x0
+
+#
+# Include the make variables (CC, etc...)
+#
+AS	= $(CROSS_COMPILE)as
+LD	= $(CROSS_COMPILE)ld
+CC	= $(CROSS_COMPILE)gcc
+CPP	= $(CC) -E
+AR	= $(CROSS_COMPILE)ar
+NM	= $(CROSS_COMPILE)nm
+LDR	= $(CROSS_COMPILE)ldr
+STRIP	= $(CROSS_COMPILE)strip
+OBJCOPY = $(CROSS_COMPILE)objcopy
+OBJDUMP = $(CROSS_COMPILE)objdump
+RANLIB	= $(CROSS_COMPILE)RANLIB
+
+PHONY: help
+
+GREEN="\e[32;1m"
+NORMAL="\e[39m"
+RED="\e[31m"
+
+LDSCRIPT := linker.lds
+LDFLAGS := -Bstatic -T $(LDSCRIPT) -Ttext $(LOAD_ADDR)
+
+CFLAGS += -march=armv7-a -Wall -g -c -fPIC -nostdinc -fno-builtin
+
+SFLAGS := $(CFLAGS)
+
+CSRC  = ${wildcard *.c lib/*.c}
+ASRC  = $(wildcard *.S lib/*.S)
+
+COBJS := $(patsubst %.c, %.o, $(CSRC))
+AOBJS += $(patsubst %.S, %.o, $(ASRC))
+
+COBJS:=$(COBJS:%.C=%.o)
+AOBJS:=$(AOBJS:%.S=%.o)
+
+
+all: $(AOBJS) $(COBJS)
+	$(LD) $^ $(LDFLAGS) -Map $(TARGET).map -o $(TARGET).elf
+	$(OBJCOPY) -O binary $(TARGET).elf $(TARGET).bin
+	$(OBJDUMP) $(TARGET).elf -S -D  >$(TARGET).dump
+
+help:
+	@echo -e ${GREEN}
+	@echo "make CROSS_COMPILE=arm-gcc12.2.0-linux- all    -- Build the bin, Use 32bit compiler"
+	@echo "make CROSS_COMPILE=arm-gcc12.2.0-linux- clean  -- Clean all"
+	@echo -e ${NORMAL}
+
+%.o:	%.S
+	$(CC)  $(SFLAGS) -o $@ $<
+
+%.o:	%.c
+	$(CC)  $(CFLAGS) -o $@ $<
+
+.PHONY : clean
+clean:
+	-rm -rf $(COBJS) $(AOBJS) $(TARGET).elf $(TARGET).bin $(TARGET).map $(LIBS)
+
+

source/trusted-firmware/trusted-firmware-a-2.8/plat/lotus/xmfalcon/resume_entry_32bit/linker.lds

@@ -0,0 +1,28 @@
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(main)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		start.o
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+
+	. = ALIGN(4);
+	.data :
+	{
+	  *(.data)
+	}
+
+}

source/trusted-firmware/trusted-firmware-a-2.8/plat/lotus/xmfalcon/resume_entry_32bit/start.S

@@ -0,0 +1,34 @@
+.balign 4
+
+#define ADDR_CEP64              (0x12120054)
+
+.globl atf_32bit_resume
+atf_32bit_resume:
+	/* Load 64bit resume address from TEE_GEN4 which is store in aux code */
+	ldr     r3, =ADDR_CEP64
+	ldr     r2, [r3]
+	lsr  r2, r2, #2
+
+	/* Set 64bit resume address to PERI_CPU_RVBARADDR */
+	mov	r3, #0x8000
+	movt	r3, #0x1202
+	str     r2, [r3, #0x10]
+
+	mov r2, #0
+	str r2, [r3, #0x14]
+
+	/* Set all cpus booting-up in 64bit mode */
+	ldr     r2, [r3, #0x0c]
+	orr     r2, r2, #0xc0
+	str     r2, [r3, #0x0c]
+
+	/* Warm reset */
+	isb
+	dsb
+	mrc     15, 0, r3, cr12, cr0, 2
+	orr     r3, r3, #0x3
+	mcr     15, 0, r3, cr12, cr0, 2
+	isb
+1:	wfi
+	b       1b
+