GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef A3700_PLAT_DEF_H
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#define A3700_PLAT_DEF_H
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#include <marvell_def.h>
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#define MVEBU_MAX_CPUS_PER_CLUSTER 2
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#define MVEBU_PRIMARY_CPU 0x0
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/*
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* The counter on A3700 is always fed from reference 25M clock (XTAL).
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* However minimal CPU counter prescaler is 2, so the counter
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* frequency will be divided by 2, the number is 12.5M
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*/
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#define COUNTER_FREQUENCY 12500000
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#define MVEBU_REGS_BASE 0xD0000000
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/*****************************************************************************
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* MVEBU memory map related constants
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*****************************************************************************
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*/
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE MVEBU_REGS_BASE
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#define DEVICE0_SIZE 0x10000000
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/*****************************************************************************
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* GIC-500 & interrupt handling related constants
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*****************************************************************************
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*/
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/* Base MVEBU compatible GIC memory map */
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#define MVEBU_GICD_BASE 0x1D00000
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#define MVEBU_GICR_BASE 0x1D40000
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#define MVEBU_GICC_BASE 0x1D80000
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/*
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* CCI-400 base address
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* This address is absolute, not relative to MVEBU_REGS_BASE.
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* This is not the default CCI base address (that would be 0xD8000000).
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* Rather we remap CCI to this address to better utilize the address space.
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* (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c)
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*/
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#define MVEBU_CCI_BASE 0xFE000000
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/*****************************************************************************
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* North and south bridge reset registers
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*****************************************************************************
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*/
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#define MVEBU_NB_RESET_REG (MVEBU_REGS_BASE + 0x12400)
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#define MVEBU_NB_RESET_I2C1_N (1 << 0)
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#define MVEBU_NB_RESET_1WIRE_N (1 << 1)
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#define MVEBU_NB_RESET_SPI_N (1 << 2)
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#define MVEBU_NB_RESET_UART_N (1 << 3)
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#define MVEBU_NB_RESET_XTL_N (1 << 4)
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#define MVEBU_NB_RESET_I2C2_N (1 << 5)
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#define MVEBU_NB_RESET_UART2_N (1 << 6)
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#define MVEBU_NB_RESET_AVS_N (1 << 7)
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#define MVEBU_NB_RESET_DDR_N (1 << 10)
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#define MVEBU_NB_RESET_SETM_N (1 << 11)
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#define MVEBU_NB_RESET_DMA_N (1 << 12)
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#define MVEBU_NB_RESET_TSECM_N (1 << 13)
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#define MVEBU_NB_RESET_SDIO_N (1 << 14)
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#define MVEBU_NB_RESET_SATA_N (1 << 15)
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#define MVEBU_NB_RESET_PWRMGT_N (1 << 16)
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#define MVEBU_NB_RESET_OTP_N (1 << 17)
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#define MVEBU_NB_RESET_EIP_N (1 << 18)
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#define MVEBU_SB_RESET_REG (MVEBU_REGS_BASE + 0x18600)
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#define MVEBU_SB_RESET_MCIPHY (1 << 1)
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#define MVEBU_SB_RESET_SDIO_N (1 << 2)
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#define MVEBU_SB_RESET_PCIE_N (1 << 3)
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#define MVEBU_SB_RESET_GBE1_N (1 << 4)
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#define MVEBU_SB_RESET_GBE0_N (1 << 5)
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#define MVEBU_SB_RESET_USB2PHY (1 << 6)
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#define MVEBU_SB_RESET_USB2HPHY (1 << 7)
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#define MVEBU_SB_RESET_MCI_N (1 << 8)
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#define MVEBU_SB_RESET_PWRMGT_N (1 << 9)
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#define MVEBU_SB_RESET_EBM_N (1 << 10)
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#define MVEBU_SB_RESET_OTP_N (1 << 11)
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/*****************************************************************************
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* North and south bridge register base
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*****************************************************************************
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*/
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#define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000)
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#define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000)
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/*****************************************************************************
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* GPIO registers related constants
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*****************************************************************************
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*/
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/* North and south bridge GPIO register base address */
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#define MVEBU_NB_GPIO_REG_BASE (MVEBU_NB_REGS_BASE + 0x800)
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#define MVEBU_NB_GPIO_IRQ_REG_BASE (MVEBU_NB_REGS_BASE + 0xC00)
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#define MVEBU_SB_GPIO_REG_BASE (MVEBU_SB_REGS_BASE + 0x800)
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#define MVEBU_SB_GPIO_IRQ_REG_BASE (MVEBU_SB_REGS_BASE + 0xC00)
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#define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00)
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/* North Bridge GPIO selection register */
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#define MVEBU_NB_GPIO_SEL_REG (MVEBU_NB_GPIO_REG_BASE + 0x30)
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#define MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG (MVEBU_NB_GPIO_REG_BASE + 0x04)
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/* I2C1 GPIO Enable bit offset */
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#define MVEBU_GPIO_TW1_GPIO_EN_OFF (10)
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/* SPI pins mode bit offset */
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#define MVEBU_GPIO_NB_SPI_PIN_MODE_OFF (28)
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/*****************************************************************************
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* DRAM registers related constants
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*****************************************************************************
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*/
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#define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE)
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/*****************************************************************************
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* SB wake-up registers related constants
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*****************************************************************************
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*/
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#define MVEBU_SB_WAKEUP_REG_BASE (MVEBU_REGS_BASE + 0x19000)
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/*****************************************************************************
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* PMSU registers related constants
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*****************************************************************************
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*/
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#define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000)
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/*****************************************************************************
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* North Bridge Step-Down Registers
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*****************************************************************************
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*/
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#define MVEBU_NB_STEP_DOWN_REG_BASE (MVEBU_REGS_BASE + 0x12800)
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/*****************************************************************************
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* DRAM CS memory map register base
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*****************************************************************************
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*/
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#define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200)
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/*****************************************************************************
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* CPU decoder window registers related constants
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*****************************************************************************
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*/
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#define MVEBU_CPU_DEC_WIN_REG_BASE (MVEBU_REGS_BASE + 0xCF00)
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/*****************************************************************************
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* AVS registers related constants
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*****************************************************************************
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*/
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#define MVEBU_AVS_REG_BASE (MVEBU_REGS_BASE + 0x11500)
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/*****************************************************************************
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* AVS registers related constants
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*****************************************************************************
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*/
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#define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
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/*****************************************************************************
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* Cortex-M3 Secure Processor Mailbox constants
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*****************************************************************************
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*/
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#define MVEBU_RWTM_REG_BASE (MVEBU_REGS_BASE + 0xB0000)
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#endif /* A3700_PLAT_DEF_H */
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+53
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/*
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* Copyright (C) 2016-2020 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef A3700_PM_H
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#define A3700_PM_H
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#include <stdint.h>
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/* supported wake up sources */
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enum pm_wake_up_src_type {
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WAKE_UP_SRC_GPIO,
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/* FOLLOWING SRC NOT SUPPORTED YET */
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WAKE_UP_SRC_TIMER,
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WAKE_UP_SRC_UART0,
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WAKE_UP_SRC_UART1,
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WAKE_UP_SRC_MAX,
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};
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struct pm_gpio_data {
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/*
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* bank 0: North bridge GPIO
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* bank 1: South bridge GPIO
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*/
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uint32_t bank_num;
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uint32_t gpio_num;
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};
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union pm_wake_up_src_data {
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struct pm_gpio_data gpio_data;
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/* delay in seconds */
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uint32_t timer_delay;
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};
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struct pm_wake_up_src {
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enum pm_wake_up_src_type wake_up_src_type;
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union pm_wake_up_src_data wake_up_data;
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};
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struct pm_wake_up_src_config {
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uint32_t wake_up_src_num;
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struct pm_wake_up_src wake_up_src[WAKE_UP_SRC_MAX];
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};
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struct pm_wake_up_src_config *mv_wake_up_src_config_get(void);
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void cm3_system_reset(void);
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#endif /* A3700_PM_H */
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+14
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef DDR_INFO_H
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#define DDR_INFO_H
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#define DRAM_MAX_IFACE 1
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#define DRAM_CH0_MMAP_LOW_OFFSET 0x200
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#endif /* DDR_INFO_H */
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+18
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef DRAM_WIN_H
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#define DRAM_WIN_H
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#include <common/bl_common.h>
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#include <io_addr_dec.h>
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void dram_win_map_build(struct dram_win_map *win_map);
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void cpu_wins_init(void);
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#endif /* DRAM_WIN_H */
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef IO_ADDR_DEC_H
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#define IO_ADDR_DEC_H
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#include <stdint.h>
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/* There are 5 configurable cpu decoder windows. */
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#define DRAM_WIN_MAP_NUM_MAX 5
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/* Target number for dram in cpu decoder windows. */
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#define DRAM_CPU_DEC_TARGET_NUM 0
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/*
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* Not all configurable decode windows could be used for dram, some units have
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* to reserve one decode window for other unit they have to communicate with;
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* for example, DMA engineer has 3 configurable windows, but only two could be
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* for dram while the last one has to be for pcie, so for DMA, its max_dram_win
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* is 2.
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*/
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struct dec_win_config {
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uint32_t dec_reg_base; /* IO address decoder register base address */
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uint32_t win_attr; /* IO address decoder windows attributes */
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/* How many configurable dram decoder windows that this unit has; */
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uint32_t max_dram_win;
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/* The decoder windows number including remapping that this unit has */
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uint32_t max_remap;
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/* The offset between continuous decode windows
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* within the same unit, typically 0x10
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*/
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uint32_t win_offset;
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};
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struct dram_win {
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uintptr_t base_addr;
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uintptr_t win_size;
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};
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struct dram_win_map {
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int dram_win_num;
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struct dram_win dram_windows[DRAM_WIN_MAP_NUM_MAX];
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};
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/*
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* init_io_addr_dec
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*
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* This function initializes io address decoder windows by
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* cpu dram window mapping information
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*
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* @input: N/A
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* - dram_wins_map: cpu dram windows mapping
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* - io_dec_config: io address decoder windows configuration
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* - io_unit_num: io address decoder unit number
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* @output: N/A
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*
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* @return: 0 on success and others on failure
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*/
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int init_io_addr_dec(struct dram_win_map *dram_wins_map,
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struct dec_win_config *io_dec_config,
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uint32_t io_unit_num);
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#endif /* IO_ADDR_DEC_H */
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+26
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <marvell_macros.S>
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/* ---------------------------------------------
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* The below macro prints out relevant GIC and
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* CCI registers registers whenever an unhandled
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* exception is taken in BL31.
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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mov_imm x17, MVEBU_GICC_BASE
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mov_imm x16, MVEBU_GICD_BASE
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marvell_print_gic_regs
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print_cci_regs
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.endm
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#endif /* PLAT_MACROS_S */
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+228
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/*
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* Copyright (C) 2016-2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#ifndef __ASSEMBLER__
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#include <stdio.h>
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#endif /* __ASSEMBLER__ */
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#include <board_marvell_def.h>
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#include <mvebu_def.h>
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/*
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* Most platform porting definitions provided by included headers
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*/
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/*
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* DRAM Memory layout:
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* +-----------------------+
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* : :
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* : Linux :
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* 0x04X00000-->+-----------------------+
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* | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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* |-----------------------| } |
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* | BL3-[0,1, 2] | }---------------------------------> |
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* |-----------------------| } || |
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* | BL2 | }->FIP (loaded by || |
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* |-----------------------| } BootROM to DRAM) || |
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* | FIP_TOC | } || |
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* 0x04120000-->|-----------------------| || |
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* | BL1 (RO) | || |
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* 0x04100000-->+-----------------------+ || |
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* : : || |
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* : Trusted SRAM section : \/ |
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* 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ |
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* | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | |
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* 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| |
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* | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | |
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* 0x04023000-->|-----------------------| +----------------+ |
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* | BL2 | |
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* |-----------------------| |
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* | | |
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* 0x04001000-->|-----------------------| |
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* | Shared | |
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* 0x04000000-->+-----------------------+ |
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* : : |
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* : Linux : |
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* : : |
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* |-----------------------| |
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* | | U-Boot(BL3-3) Loaded by BL2 |
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* | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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* 0x00000000-->+-----------------------+
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*
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* Trusted SRAM section 0x4000000..0x4200000:
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* ----------------------------------------
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* SRAM_BASE = 0x4001000
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* BL2_BASE = 0x4006000
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* BL2_LIMIT = BL31_BASE
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* BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000)
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* BL31_PROGBITS_LIMIT = BL1_RW_BASE
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* BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000)
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* BL1_RW_LIMIT = BL31_LIMIT = 0x4040000
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*
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*
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* PLAT_MARVELL_FIP_BASE = 0x4120000
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*/
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/*
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* Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0,
|
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* it is allowed to load/copy images to 'NULL' pointers
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*/
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#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
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#define PLAT_ALLOW_ZERO_ADDR_COPY
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#endif
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||||
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#define PLAT_MARVELL_ATF_BASE 0x4000000
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#define PLAT_MARVELL_ATF_LOAD_ADDR \
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(PLAT_MARVELL_ATF_BASE + 0x100000)
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#define PLAT_MARVELL_FIP_BASE \
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(PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000)
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#define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000
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||||
|
||||
#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2)
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/* DRAM[2MB..66MB] is used as Trusted ROM */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
|
||||
/* 4 MB for FIP image */
|
||||
#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000
|
||||
/* Reserve 12M for SCP (Secure PayLoad) Trusted RAM
|
||||
* OP-TEE SHMEM follows this region
|
||||
*/
|
||||
#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
|
||||
#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x00C00000 /* 12 MB DRAM */
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
|
||||
* plus a little space for growth.
|
||||
*/
|
||||
#define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#define PLAT_MARVELL_MAX_BL2_SIZE 0xF000
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000
|
||||
|
||||
#define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE
|
||||
|
||||
/* GIC related definitions */
|
||||
#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)
|
||||
#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE)
|
||||
#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)
|
||||
|
||||
#define PLAT_MARVELL_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
#define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, \
|
||||
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
|
||||
#define PLAT_MARVELL_SHARED_RAM_CACHED 1
|
||||
|
||||
/* CCI related constants */
|
||||
#define PLAT_MARVELL_CCI_BASE MVEBU_CCI_BASE
|
||||
#define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3
|
||||
#define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4
|
||||
|
||||
/*
|
||||
* Load address of BL3-3 for this platform port
|
||||
*/
|
||||
#define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0
|
||||
|
||||
/* System Reference Clock*/
|
||||
#define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY
|
||||
|
||||
/*
|
||||
* PL011 related constants
|
||||
*/
|
||||
#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
|
||||
|
||||
/* Required platform porting definitions */
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
|
||||
/* System timer related constants */
|
||||
#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
|
||||
|
||||
/* Mailbox base address */
|
||||
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400)
|
||||
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
|
||||
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
|
||||
|
||||
/* DRAM CS memory map registers related constants */
|
||||
#define MVEBU_CS_MMAP_LOW(cs_num) \
|
||||
(MVEBU_CS_MMAP_REG_BASE + (cs_num) * 0x8)
|
||||
#define MVEBU_CS_MMAP_ENABLE 0x1
|
||||
#define MVEBU_CS_MMAP_AREA_LEN_OFFS 16
|
||||
#define MVEBU_CS_MMAP_AREA_LEN_MASK \
|
||||
(0x1f << MVEBU_CS_MMAP_AREA_LEN_OFFS)
|
||||
#define MVEBU_CS_MMAP_START_ADDR_LOW_OFFS 23
|
||||
#define MVEBU_CS_MMAP_START_ADDR_LOW_MASK \
|
||||
(0x1ff << MVEBU_CS_MMAP_START_ADDR_LOW_OFFS)
|
||||
|
||||
#define MVEBU_CS_MMAP_HIGH(cs_num) \
|
||||
(MVEBU_CS_MMAP_REG_BASE + 0x4 + (cs_num) * 0x8)
|
||||
|
||||
/* DRAM max CS number */
|
||||
#define MVEBU_MAX_CS_MMAP_NUM (2)
|
||||
|
||||
/* CPU decoder window related constants */
|
||||
#define CPU_DEC_WIN_CTRL_REG(win_num) \
|
||||
(MVEBU_CPU_DEC_WIN_REG_BASE + (win_num) * 0x10)
|
||||
#define CPU_DEC_CR_WIN_ENABLE 0x1
|
||||
#define CPU_DEC_CR_WIN_TARGET_OFFS 4
|
||||
#define CPU_DEC_CR_WIN_TARGET_MASK \
|
||||
(0xf << CPU_DEC_CR_WIN_TARGET_OFFS)
|
||||
|
||||
#define CPU_DEC_WIN_SIZE_REG(win_num) \
|
||||
(MVEBU_CPU_DEC_WIN_REG_BASE + 0x4 + (win_num) * 0x10)
|
||||
#define CPU_DEC_CR_WIN_SIZE_OFFS 0
|
||||
#define CPU_DEC_CR_WIN_SIZE_MASK \
|
||||
(0xffff << CPU_DEC_CR_WIN_SIZE_OFFS)
|
||||
#define CPU_DEC_CR_WIN_SIZE_ALIGNMENT 0x10000
|
||||
|
||||
#define CPU_DEC_WIN_BASE_REG(win_num) \
|
||||
(MVEBU_CPU_DEC_WIN_REG_BASE + 0x8 + (win_num) * 0x10)
|
||||
#define CPU_DEC_BR_BASE_OFFS 0
|
||||
#define CPU_DEC_BR_BASE_MASK \
|
||||
(0xffff << CPU_DEC_BR_BASE_OFFS)
|
||||
|
||||
#define CPU_DEC_REMAP_LOW_REG(win_num) \
|
||||
(MVEBU_CPU_DEC_WIN_REG_BASE + 0xC + (win_num) * 0x10)
|
||||
#define CPU_DEC_RLR_REMAP_LOW_OFFS 0
|
||||
#define CPU_DEC_RLR_REMAP_LOW_MASK \
|
||||
(0xffff << CPU_DEC_BR_BASE_OFFS)
|
||||
|
||||
#define CPU_DEC_CCI_BASE_REG (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
|
||||
|
||||
/* Securities */
|
||||
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
Reference in New Issue
Block a user