GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <mv_ddr_if.h>
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#include <plat_marvell.h>
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/*
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* This function may modify the default DRAM parameters
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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void plat_marvell_dram_update_topology(void)
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{
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}
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/*
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* This struct provides the DRAM training code with
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* the appropriate board DRAM configuration
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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/* FIXME: MISL board 2CS 8Gb x8 devices of micron - 2133P */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400T, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#include <mvebu_def.h>
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win *amb_memory_map;
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int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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*win = amb_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(amb_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* IO WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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#ifndef IMAGE_BLE
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map[] = {
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/* PEX0_X4 window */
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{0x00000000f6000000, 0x6000000, PEX0_TID},
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{0x00000000c0000000, 0x30000000, PEX0_TID},
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{0x0000000800000000, 0x200000000, PEX0_TID},
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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*win = iob_memory_map;
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*size = ARRAY_SIZE(iob_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = {
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
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#else
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#if LLC_SRAM
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/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
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* and changes the window target to SRAM_TID.
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*/
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{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
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#endif
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{0x00000000f2000000, 0xe000000, IO_0_TID},
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000000800000000, 0x200000000, IO_0_TID}, /* IO window */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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#ifdef IMAGE_BLE
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struct pci_hw_cfg *plat_get_pcie_hw_data(void)
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{
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return NULL;
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}
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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#if PLAT_RECOVERY_IMAGE_ENABLE
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struct skip_image skip_im = {
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.detection_method = GPIO,
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.info.gpio.num = 33,
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.info.gpio.button_state = HIGH,
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.info.test.cp_ap = CP,
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.info.test.cp_index = 0,
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};
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void *plat_marvell_get_skip_image_data(void)
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{
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/* Return the skip_image configurations */
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return &skip_im;
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}
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#endif
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#endif
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+31
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef MVEBU_DEF_H
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#define MVEBU_DEF_H
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#include <a8k_plat_def.h>
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#define CP_COUNT 1 /* A70x0 has single CP0 */
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/***********************************************************************
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* Required platform porting definitions common to all
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* Management Compute SubSystems (MSS)
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***********************************************************************
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*/
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/*
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* Load address of SCP_BL2
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* SCP_BL2 is loaded to the same place as BL31.
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* Once SCP_BL2 is transferred to the SCP,
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* it is discarded and BL31 is loaded over the top.
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*/
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#ifdef SCP_IMAGE
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#define SCP_BL2_BASE BL31_BASE
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#endif
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#endif /* MVEBU_DEF_H */
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+20
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#
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# Copyright (C) 2018 Marvell International Ltd.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# https://spdx.org/licenses
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#
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PCI_EP_SUPPORT := 0
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CP_NUM := 1
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$(eval $(call add_define,CP_NUM))
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DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
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MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
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BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
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include plat/marvell/armada/a8k/common/a8k_common.mk
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include plat/marvell/armada/common/marvell_common.mk
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