GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/mentor/mi2cv.h>
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#include <lib/mmio.h>
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#include <mv_ddr_if.h>
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#include <mvebu_def.h>
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#include <plat_marvell.h>
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#define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0)
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#define MVEBU_AP_MPP_CTRL4_OFFS 16
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#define MVEBU_AP_MPP_CTRL5_OFFS 20
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#define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA 0x3
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#define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA 0x3
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#define MVEBU_CP_MPP_CTRL37_OFFS 20
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#define MVEBU_CP_MPP_CTRL38_OFFS 24
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#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
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#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
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#define MVEBU_MPP_CTRL_MASK 0xf
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/*
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* This struct provides the DRAM training code with
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* the appropriate board DRAM configuration
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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/* MISL board with 1CS 8Gb x4 devices of Micron 2400T */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0} },
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/* TODO: double check if the speed bin is 2400T */
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SPEED_BIN_DDR_2400T, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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#if DDR32
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MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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#else
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MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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#endif
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MV_DDR_CFG_SPD, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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static void mpp_config(void)
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{
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uintptr_t reg;
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uint32_t val;
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reg = MVEBU_CP_MPP_REGS(0, 4);
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/* configure CP0 MPP 37 and 38 to i2c */
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val = mmio_read_32(reg);
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val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
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(MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
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val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
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MVEBU_CP_MPP_CTRL37_OFFS) |
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(MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
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MVEBU_CP_MPP_CTRL38_OFFS);
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mmio_write_32(reg, val);
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}
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/*
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* This function may modify the default DRAM parameters
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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void plat_marvell_dram_update_topology(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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INFO("Gathering DRAM information\n");
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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/* configure MPPs to enable i2c */
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mpp_config();
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/* initialize i2c */
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i2c_init((void *)MVEBU_CP0_I2C_BASE);
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/* select SPD memory page 0 to access DRAM configuration */
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i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
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/* read data from spd */
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i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
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sizeof(tm->spd_data.all_bytes));
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}
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}
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+202
@@ -0,0 +1,202 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#include <mvebu_def.h>
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win amb_memory_map[] = {
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/* CP1 SPI1 CS0 Direct Mode access */
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{0xf900, 0x1000000, AMB_SPI1_CS0_ID},
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};
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int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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*win = amb_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(amb_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* IO WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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/* CP1 (MCI0) internal regs */
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{0x00000000f4000000, 0x2000000, MCI_0_TID},
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#ifndef IMAGE_BLE
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/* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/
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{0x00000000f9000000, 0x2000000, MCI_0_TID},
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/* PCIe1 on CP1*/
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{0x00000000fb000000, 0x1000000, MCI_0_TID},
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/* PCIe2 on CP1*/
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{0x00000000fc000000, 0x1000000, MCI_0_TID},
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map_cp0[] = {
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/* CP0 */
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/* PEX1_X1 window */
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{0x00000000f7000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000f8000000, 0x1000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000f6000000, 0x1000000, PEX0_TID},
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{0x00000000c0000000, 0x30000000, PEX0_TID},
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{0x0000000800000000, 0x100000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp1[] = {
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/* CP1 */
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000f9000000, 0x1000000, RUNIT_TID},
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/* PEX1_X1 window */
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{0x00000000fb000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000fc000000, 0x1000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000fa000000, 0x1000000, PEX0_TID}
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = iob_memory_map_cp0;
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*size = ARRAY_SIZE(iob_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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*win = iob_memory_map_cp1;
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*size = ARRAY_SIZE(iob_memory_map_cp1);
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return 0;
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = {
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
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#else
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#if LLC_SRAM
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/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
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* and changes the window target to SRAM_TID.
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*/
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{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
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#endif
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{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* SoC PM configuration
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*****************************************************************************
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*/
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/* CP GPIO should be used and the GPIOs should be within same GPIO register */
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struct power_off_method pm_cfg = {
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.type = PMIC_GPIO,
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.cfg.gpio.pin_count = 1,
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.cfg.gpio.info = {{0, 35} },
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.cfg.gpio.step_count = 7,
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.cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
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.cfg.gpio.delay_ms = 10,
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};
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void *plat_marvell_get_pm_cfg(void)
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{
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/* Return the PM configurations */
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return &pm_cfg;
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}
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/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
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#else
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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#if PLAT_RECOVERY_IMAGE_ENABLE
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struct skip_image skip_im = {
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.detection_method = GPIO,
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.info.gpio.num = 33,
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.info.gpio.button_state = HIGH,
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.info.test.cp_ap = CP,
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.info.test.cp_index = 0,
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};
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void *plat_marvell_get_skip_image_data(void)
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{
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/* Return the skip_image configurations */
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return &skip_im;
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}
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#endif
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#endif
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+192
@@ -0,0 +1,192 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PHY_PORTING_LAYER_H
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#define PHY_PORTING_LAYER_H
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#define MAX_LANE_NR 6
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static const struct xfi_params
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xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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/* AP0 */
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{
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/* CP 0 */
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{
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{ 0 }, /* Comphy0 */
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{ 0 }, /* Comphy1 */
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{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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.align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
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.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
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.valid = 0x1 }, /* Comphy2 */
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{ 0 }, /* Comphy3 */
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{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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.align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
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.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
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.valid = 0x1 }, /* Comphy4 */
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{ 0 }, /* Comphy5 */
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},
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/* CP 1 */
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{
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{ 0 }, /* Comphy0 */
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{ 0 }, /* Comphy1 */
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{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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.align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
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.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
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.valid = 0x1 }, /* Comphy2 */
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{ 0 }, /* Comphy3 */
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{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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.align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
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.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
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.valid = 0x1 }, /* Comphy4 */
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{ 0 }, /* Comphy5 */
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},
|
||||
},
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||||
};
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||||
|
||||
static const struct sata_params
|
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sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
|
||||
/* AP0 */
|
||||
{
|
||||
/* CP 0 */
|
||||
{
|
||||
{ 0 }, /* Comphy0 */
|
||||
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
|
||||
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
|
||||
.g3_emph_en = 0x1,
|
||||
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
|
||||
.g3_tx_amp_adj = 0x1,
|
||||
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
|
||||
.g3_tx_emph_en = 0x0,
|
||||
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
|
||||
.g3_tx_emph = 0x1,
|
||||
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
|
||||
.g3_ffe_cap_sel = 0xf,
|
||||
.align90 = 0x61,
|
||||
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
|
||||
.g3_rx_selmuff = 0x3,
|
||||
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
|
||||
.g3_rx_selmufi = 0x3,
|
||||
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
|
||||
.g3_rx_selmupf = 0x2,
|
||||
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
|
||||
.g3_rx_selmupi = 0x2,
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
|
||||
.valid = 0x1
|
||||
}, /* Comphy1 */
|
||||
{ 0 }, /* Comphy2 */
|
||||
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
|
||||
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
|
||||
.g3_emph_en = 0x1,
|
||||
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
|
||||
.g3_tx_amp_adj = 0x1,
|
||||
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
|
||||
.g3_tx_emph_en = 0x0,
|
||||
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
|
||||
.g3_tx_emph = 0x1,
|
||||
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
|
||||
.g3_ffe_cap_sel = 0xf,
|
||||
.align90 = 0x61,
|
||||
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
|
||||
.g3_rx_selmuff = 0x3,
|
||||
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
|
||||
.g3_rx_selmufi = 0x3,
|
||||
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
|
||||
.g3_rx_selmupf = 0x2,
|
||||
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
|
||||
.g3_rx_selmupi = 0x2,
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
|
||||
.valid = 0x1
|
||||
}, /* Comphy3 */
|
||||
{ 0 }, /* Comphy4 */
|
||||
{ 0 }, /* Comphy5 */
|
||||
},
|
||||
|
||||
/* CP 1 */
|
||||
{
|
||||
{ 0 }, /* Comphy0 */
|
||||
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
|
||||
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
|
||||
.g3_emph_en = 0x1,
|
||||
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
|
||||
.g3_tx_amp_adj = 0x1,
|
||||
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
|
||||
.g3_tx_emph_en = 0x0,
|
||||
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
|
||||
.g3_tx_emph = 0x1,
|
||||
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
|
||||
.g3_ffe_cap_sel = 0xf,
|
||||
.align90 = 0x61,
|
||||
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
|
||||
.g3_rx_selmuff = 0x3,
|
||||
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
|
||||
.g3_rx_selmufi = 0x3,
|
||||
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
|
||||
.g3_rx_selmupf = 0x2,
|
||||
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
|
||||
.g3_rx_selmupi = 0x2,
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
|
||||
.valid = 0x1
|
||||
}, /* Comphy1 */
|
||||
{ 0 }, /* Comphy2 */
|
||||
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
|
||||
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g2_emph_en = 0x1,
|
||||
.g3_emph_en = 0x1,
|
||||
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
|
||||
.g3_tx_amp_adj = 0x1,
|
||||
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
|
||||
.g3_tx_emph_en = 0x0,
|
||||
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
|
||||
.g3_tx_emph = 0x1,
|
||||
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
|
||||
.g3_ffe_cap_sel = 0xf,
|
||||
.align90 = 0x61,
|
||||
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
|
||||
.g3_rx_selmuff = 0x3,
|
||||
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
|
||||
.g3_rx_selmufi = 0x3,
|
||||
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
|
||||
.g3_rx_selmupf = 0x2,
|
||||
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
|
||||
.g3_rx_selmupi = 0x2,
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
|
||||
.valid = 0x1
|
||||
}, /* Comphy3 */
|
||||
{ 0 }, /* Comphy4 */
|
||||
{ 0 }, /* Comphy5 */
|
||||
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct usb_params
|
||||
usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
|
||||
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT
|
||||
},
|
||||
};
|
||||
#endif /* PHY_PORTING_LAYER_H */
|
||||
Reference in New Issue
Block a user