GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef A8K_PLAT_DEF_H
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#define A8K_PLAT_DEF_H
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#include <marvell_def.h>
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#define MVEBU_PRIMARY_CPU 0x0
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#define MVEBU_AP0 0x0
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/* APN806 revision ID */
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#define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC)
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#define GWD_IIDR2_REV_ID_OFFSET 12
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#define GWD_IIDR2_REV_ID_MASK 0xF
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#define GWD_IIDR2_CHIP_ID_OFFSET 20
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#define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET)
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#define CHIP_ID_AP806 0x806
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#define CHIP_ID_AP807 0x807
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#define COUNTER_FREQUENCY 25000000
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#define MVEBU_REGS_BASE 0xF0000000
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#define MVEBU_REGS_BASE_MASK 0xF0000000
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#define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE
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#define MVEBU_AP_IO_BASE(ap) 0xF2000000
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#define MVEBU_CP_OFFSET 0x2000000
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#define MVEBU_CP_REGS_BASE(cp_index) (MVEBU_AP_IO_BASE(0) + \
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(cp_index) * MVEBU_CP_OFFSET)
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#define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000)
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#define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE)
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#define MVEBU_IO_WIN_GCR_OFFSET (0x70)
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#define MVEBU_IO_WIN_MAX_WINS (7)
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/* Misc SoC configurations Base */
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#define MVEBU_MISC_SOC_BASE (MVEBU_REGS_BASE + 0x6F4300)
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#define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000)
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#define MVEBU_CCU_MAX_WINS (8)
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#define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000)
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#define MVEBU_DRAM_MAC_BASE (MVEBU_REGS_BASE + 0x20000)
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#define MVEBU_DRAM_PHY_BASE (MVEBU_REGS_BASE + 0x20000)
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#define MVEBU_SMMU_BASE (MVEBU_REGS_BASE + 0x100000)
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#define MVEBU_CP_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
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0x440000 + ((n) << 2))
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#define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
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0x440000 + ((n / 8) << 2))
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#define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \
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(MVEBU_CP_REGS_BASE(cp_index) + \
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0x440100 + ((n > 31) ? 0x40 : 0x00))
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#define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \
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(MVEBU_CP_REGS_BASE(cp_index) + \
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0x440104 + ((n > 31) ? 0x40 : 0x00))
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#define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
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0x440110 + ((n > 31) ? 0x40 : 0x00))
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#define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2))
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#define MVEBU_AP_GPIO_REGS (MVEBU_RFU_BASE + 0x5040)
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#define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10)
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#define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000)
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#define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000)
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#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000)
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#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_AP_GEN_MGMT_BASE + 0x84)
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#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \
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0x20080 + ((win) * 0x8))
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#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \
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0x20084 + ((win) * 0x8))
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/* MCI indirect access definitions */
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#define MCI_MAX_UNIT_ID 2
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/* SoC RFU / IHBx4 Control */
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#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \
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0x4218 + (unit_id * 0x20))
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#define MCI_REMAP_OFF_SHIFT 8
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#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \
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((index) * 0x1000000))
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#define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000)
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#define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000)
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#define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000)
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#define MVEBU_CP_DFX_OFFSET (0x400200)
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/*****************************************************************************
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* MVEBU memory map related constants
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*****************************************************************************
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*/
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE MVEBU_REGS_BASE
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#define DEVICE0_SIZE 0x10000000
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/*****************************************************************************
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* GIC-400 & interrupt handling related constants
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*****************************************************************************
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*/
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/* Base MVEBU compatible GIC memory map */
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#define MVEBU_GICD_BASE 0x210000
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#define MVEBU_GICC_BASE 0x220000
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/*****************************************************************************
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* AXI Configuration
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*****************************************************************************
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*/
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#define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4
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#define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \
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MVEBU_AXI_ATTR_ARCACHE_OFFSET)
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#define MVEBU_AXI_ATTR_ARDOMAIN_OFFSET 12
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#define MVEBU_AXI_ATTR_ARDOMAIN_MASK (0x3 << \
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MVEBU_AXI_ATTR_ARDOMAIN_OFFSET)
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#define MVEBU_AXI_ATTR_AWCACHE_OFFSET 20
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#define MVEBU_AXI_ATTR_AWCACHE_MASK (0xF << \
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MVEBU_AXI_ATTR_AWCACHE_OFFSET)
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#define MVEBU_AXI_ATTR_AWDOMAIN_OFFSET 28
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#define MVEBU_AXI_ATTR_AWDOMAIN_MASK (0x3 << \
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MVEBU_AXI_ATTR_AWDOMAIN_OFFSET)
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/* SATA MBUS to AXI configuration */
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#define MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET 1
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#define MVEBU_SATA_M2A_AXI_ARCACHE_MASK (0xF << \
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MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET)
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#define MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET 5
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#define MVEBU_SATA_M2A_AXI_AWCACHE_MASK (0xF << \
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MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET)
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/* ARM cache attributes */
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#define CACHE_ATTR_BUFFERABLE 0x1
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#define CACHE_ATTR_CACHEABLE 0x2
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#define CACHE_ATTR_READ_ALLOC 0x4
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#define CACHE_ATTR_WRITE_ALLOC 0x8
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/* Domain */
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#define DOMAIN_NON_SHAREABLE 0x0
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#define DOMAIN_INNER_SHAREABLE 0x1
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#define DOMAIN_OUTER_SHAREABLE 0x2
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#define DOMAIN_SYSTEM_SHAREABLE 0x3
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/************************************************************************
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* Required platform porting definitions common to all
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* Management Compute SubSystems (MSS)
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************************************************************************
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*/
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/*
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* Load address of SCP_BL2
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* SCP_BL2 is loaded to the same place as BL31.
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* Once SCP_BL2 is transferred to the SCP,
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* it is discarded and BL31 is loaded over the top.
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*/
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#ifdef SCP_IMAGE
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#define SCP_BL2_BASE BL31_BASE
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#define SCP_BL2_SIZE BL31_LIMIT
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#endif
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#ifndef __ASSEMBLER__
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enum ap806_sar_target_dev {
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SAR_PIDI_MCIX2 = 0x0,
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SAR_MCIX4 = 0x1,
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SAR_SPI = 0x2,
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SAR_SD = 0x3,
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SAR_PIDI_MCIX2_BD = 0x4, /* BootRom disabled */
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SAR_MCIX4_DB = 0x5, /* BootRom disabled */
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SAR_SPI_DB = 0x6, /* BootRom disabled */
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SAR_EMMC = 0x7
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};
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enum io_win_target_ids {
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MCI_0_TID = 0x0,
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MCI_1_TID = 0x1,
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MCI_2_TID = 0x2,
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PIDI_TID = 0x3,
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SPI_TID = 0x4,
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STM_TID = 0x5,
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BOOTROM_TID = 0x6,
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IO_WIN_MAX_TID
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};
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enum ccu_target_ids {
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IO_0_TID = 0x00,
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DRAM_0_TID = 0x03,
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IO_1_TID = 0x0F,
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CFG_REG_TID = 0x10,
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RAR_TID = 0x20,
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SRAM_TID = 0x40,
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DRAM_1_TID = 0xC0,
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CCU_MAX_TID,
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INVALID_TID = 0xFF
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};
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#endif /* __ASSEMBLER__ */
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#endif /* A8K_PLAT_DEF_H */
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+9
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#define DRAM_MAX_IFACE 1
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#define DRAM_CH0_MMAP_LOW_OFFSET 0x20200
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* This driver provides I2C support for Marvell A8K and compatible SoCs */
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#ifndef MENTOR_I2C_PLAT_H
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#define MENTOR_I2C_PLAT_H
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#define CONFIG_SYS_TCLK 250000000
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define I2C_CAN_UNSTUCK
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struct mentor_i2c_regs {
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uint32_t slave_address;
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uint32_t data;
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uint32_t control;
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union {
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uint32_t status; /* when reading */
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uint32_t baudrate; /* when writing */
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};
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uint32_t xtnd_slave_addr;
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uint32_t reserved[2];
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uint32_t soft_reset;
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uint8_t reserved2[0xa0 - 0x20];
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uint32_t unstuck;
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};
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#endif /* MENTOR_I2C_PLAT_H */
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+20
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <marvell_macros.S>
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/*
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* Required platform porting macros
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* (Provided by included headers)
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*/
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.macro plat_crash_print_regs
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.endm
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#endif /* PLAT_MACROS_S */
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+196
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#ifndef __ASSEMBLER__
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#include <stdio.h>
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#endif /* __ASSEMBLER__ */
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#include <common/interrupt_props.h>
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#include <drivers/arm/gic_common.h>
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#include <board_marvell_def.h>
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#include <mvebu_def.h>
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/*
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* Most platform porting definitions provided by included headers
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*/
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/*
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* DRAM Memory layout:
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* +-----------------------+
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* : :
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* : Linux :
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* 0x04X00000-->+-----------------------+
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* | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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* |-----------------------| } |
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* | BL3-[0,1, 2] | }---------------------------------> |
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* |-----------------------| } || |
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* | BL2 | }->FIP (loaded by || |
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* |-----------------------| } BootROM to DRAM) || |
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* | FIP_TOC | } || |
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* 0x04120000-->|-----------------------| || |
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* | BL1 (RO) | || |
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* 0x04100000-->+-----------------------+ || |
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* : : || |
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* : Trusted SRAM section : \/ |
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* 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ |
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* | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | |
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* 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| |
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* | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | |
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* 0x04023000-->|-----------------------| +----------------+ |
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* | BL2 | |
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* |-----------------------| |
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* | | |
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* 0x04001000-->|-----------------------| |
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* | Shared | |
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* 0x04000000-->+-----------------------+ |
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* : : |
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* : Linux : |
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* : : |
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* |-----------------------| |
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* | | U-Boot(BL3-3) Loaded by BL2 |
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* | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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* 0x00000000-->+-----------------------+
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*
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* Trusted SRAM section 0x4000000..0x4200000:
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* ----------------------------------------
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* SRAM_BASE = 0x4001000
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* BL2_BASE = 0x4006000
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* BL2_LIMIT = BL31_BASE
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* BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000)
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* BL31_PROGBITS_LIMIT = BL1_RW_BASE
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* BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000)
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* BL1_RW_LIMIT = BL31_LIMIT = 0x4040000
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*
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*
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* PLAT_MARVELL_FIP_BASE = 0x4120000
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*/
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#define PLAT_MARVELL_SRAM_BASE 0xFFE1C048
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#define PLAT_MARVELL_SRAM_END 0xFFE78000
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#define PLAT_MARVELL_ATF_BASE 0x4000000
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#define PLAT_MARVELL_ATF_LOAD_ADDR (PLAT_MARVELL_ATF_BASE + \
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0x100000)
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#define PLAT_MARVELL_FIP_BASE (PLAT_MARVELL_ATF_LOAD_ADDR + \
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0x20000)
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#define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000
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#define PLAT_MARVELL_NORTHB_COUNT 1
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#define PLAT_MARVELL_CLUSTER_COUNT U(2)
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#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2)
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#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
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PLAT_MARVELL_CLUSTER_CORE_COUNT)
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#define PLAT_MAX_CPUS_PER_CLUSTER PLAT_MARVELL_CLUSTER_CORE_COUNT
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/* Part of DRAM that is used as Trusted ROM */
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#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
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/* 4 MB for FIP image */
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#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000
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/* Reserve 12MB for SCP (Secure PayLoad) Trusted RAM
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* OP-TEE 4MB SHMEM follows this region
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*/
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#define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000
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#define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x00C00000 /* 12 MB DRAM */
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#define PLAT_MARVELL_LLC_SRAM_BASE 0x05400000
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#define PLAT_MARVELL_LLC_SRAM_SIZE 0x00100000 /* 1 MB SRAM */
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#define PLAT_MARVELL_MAX_BL2_SIZE 0xF000
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/*
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000
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#define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE
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/* GIC related definitions */
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#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)
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#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)
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#define PLAT_MARVELL_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_PIC0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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||||
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||||
#define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
#define PLAT_MARVELL_SHARED_RAM_CACHED 1
|
||||
|
||||
/*
|
||||
* Load address of BL3-3 for this platform port
|
||||
*/
|
||||
#define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0
|
||||
|
||||
/* System Reference Clock*/
|
||||
#define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY
|
||||
|
||||
/*
|
||||
* PL011 related constants
|
||||
*/
|
||||
#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x512000)
|
||||
#define PLAT_MARVELL_UART_CLK_IN_HZ 200000000
|
||||
|
||||
/* Recovery image enable */
|
||||
#define PLAT_RECOVERY_IMAGE_ENABLE 0
|
||||
|
||||
/* Required platform porting definitions */
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
|
||||
/* System timer related constants */
|
||||
#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
|
||||
|
||||
/* Mailbox base address (note the lower memory space
|
||||
* is reserved for BLE data)
|
||||
*/
|
||||
#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE \
|
||||
+ 0x400)
|
||||
#define PLAT_MARVELL_MAILBOX_SIZE 0x100
|
||||
#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
|
||||
|
||||
/* Securities */
|
||||
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
|
||||
|
||||
#define MVEBU_PMU_IRQ_WA
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
Reference in New Issue
Block a user