GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <marvell_def.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef SCP_BL2_BASE
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/* Fill SCP_BL2 related information if it exists */
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{
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = SCP_BL2_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* SCP_BL2_BASE */
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#ifdef EL3_PAYLOAD_BASE
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/* Fill EL3 payload related information (BL31 is EL3 payload)*/
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = EL3_PAYLOAD_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#else /* EL3_PAYLOAD_BASE */
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/* Fill BL31 related information */
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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#if DEBUG
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.ep_info.args.arg3 = MARVELL_BL31_PLAT_PARAM_VAL,
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#endif
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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# ifdef BL32_BASE
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.next_handoff_image_id = BL32_IMAGE_ID,
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# else
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.next_handoff_image_id = BL33_IMAGE_ID,
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# endif
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},
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# ifdef BL32_BASE
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/* Fill BL32 related information */
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{
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.image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
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.ep_info.pc = BL32_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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/*
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* Fill BL32 external 1 related information.
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* A typical use for extra1 image is with OP-TEE
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* where it is the pager image.
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*/
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{
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.image_id = BL32_EXTRA1_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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/*
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* Fill BL32 external 2 related information.
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* A typical use for extra2 image is with OP-TEE,
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* where it is the paged image.
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*/
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{
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.image_id = BL32_EXTRA2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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#ifdef SPD_opteed
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.image_info.image_base = MARVELL_OPTEE_PAGEABLE_LOAD_BASE,
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.image_info.image_max_size = MARVELL_OPTEE_PAGEABLE_LOAD_SIZE,
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#endif
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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# endif /* BL32_BASE */
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/* Fill BL33 related information */
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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# ifdef PRELOADED_BL33_BASE
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.ep_info.pc = PRELOADED_BL33_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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# else
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.ep_info.pc = MARVELL_DRAM_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = MARVELL_DRAM_BASE,
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.image_info.image_max_size = MARVELL_DRAM_SIZE,
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# endif /* PRELOADED_BL33_BASE */
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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#endif /* EL3_PAYLOAD_BASE */
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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+137
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat_marvell.h>
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak plat_get_ns_image_entrypoint
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#pragma weak plat_marvell_get_mmap
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/*
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* Set up the page tables for the generic and platform-specific memory regions.
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* The extents of the generic memory regions are specified by the function
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* arguments and consist of:
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* - Trusted SRAM seen by the BL image;
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* - Code section;
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* - Read-only data section;
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* - Coherent memory region, if applicable.
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*/
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void marvell_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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,
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uintptr_t coh_start,
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uintptr_t coh_limit
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#endif
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)
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{
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/*
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* Map the Trusted SRAM with appropriate memory attributes.
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* Subsequent mappings will adjust the attributes for specific regions.
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*/
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VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
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(void *) total_base, (void *) (total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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/* Re-map the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *) code_start, (void *) code_limit);
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mmap_add_region(code_start, code_start,
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code_limit - code_start,
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MT_CODE | MT_SECURE);
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/* Re-map the read-only data section */
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VERBOSE("Read-only data region: %p - %p\n",
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(void *) rodata_start, (void *) rodata_limit);
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mmap_add_region(rodata_start, rodata_start,
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rodata_limit - rodata_start,
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MT_RO_DATA | MT_SECURE);
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#if USE_COHERENT_MEM
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/* Re-map the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *) coh_start, (void *) coh_limit);
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mmap_add_region(coh_start, coh_start,
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coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* Now (re-)map the platform-specific memory regions */
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mmap_add(plat_marvell_get_mmap());
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/* Create the page tables to reflect the above mappings */
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init_xlat_tables();
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return PLAT_MARVELL_NS_IMAGE_OFFSET;
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}
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/*****************************************************************************
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* Gets SPSR for BL32 entry
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*****************************************************************************
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*/
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uint32_t marvell_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/*****************************************************************************
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* Gets SPSR for BL33 entry
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*****************************************************************************
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*/
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uint32_t marvell_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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/*****************************************************************************
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* Returns ARM platform specific memory map regions.
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*****************************************************************************
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*/
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const mmap_region_t *plat_marvell_get_mmap(void)
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{
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return plat_marvell_mmap;
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}
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+259
@@ -0,0 +1,259 @@
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/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <asm_macros.S>
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#include <cortex_a72.h>
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#ifndef PLAT_a3700
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#include <drivers/marvell/ccu.h>
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#include <drivers/marvell/cache_llc.h>
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#endif
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#include <marvell_def.h>
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#include <platform_def.h>
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.weak plat_marvell_calc_core_pos
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.weak plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl disable_mmu_dcache
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.globl invalidate_tlb_all
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.globl platform_unmap_sram
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.globl disable_sram
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.globl disable_icache
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.globl invalidate_icache_all
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.globl marvell_exit_bootrom
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.globl ca72_l2_enable_unique_clean
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_marvell_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_marvell_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_marvell_calc_core_pos(uint64_t mpidr)
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* Helper function to calculate the core position.
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* With this function: CorePos = (ClusterId * 2) +
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* CoreId
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* -----------------------------------------------------
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*/
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func plat_marvell_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #7
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ret
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endfunc plat_marvell_calc_core_pos
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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#ifdef PLAT_a3700
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mov x1, x30
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bl get_ref_clk
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mov x30, x1
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mov_imm x1, 1000000
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mul x1, x0, x1
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#else
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mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
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#endif
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mov_imm x0, PLAT_MARVELL_UART_BASE
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mov_imm x2, MARVELL_CONSOLE_BAUDRATE
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#ifdef PLAT_a3700
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b console_a3700_core_init
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#else
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b console_16550_core_init
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#endif
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_MARVELL_UART_BASE
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#ifdef PLAT_a3700
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b console_a3700_core_putc
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#else
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b console_16550_core_putc
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#endif
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : r0
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_MARVELL_UART_BASE
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#ifdef PLAT_a3700
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b console_a3700_core_flush
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#else
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b console_16550_core_flush
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#endif
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endfunc plat_crash_console_flush
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on ARM
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* platforms. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* -----------------------------------------------------
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* Disable icache, dcache, and MMU
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* -----------------------------------------------------
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*/
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func disable_mmu_dcache
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mrs x0, sctlr_el3
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bic x0, x0, 0x1 /* M bit - MMU */
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bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */
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msr sctlr_el3, x0
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isb
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b mmu_off
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mmu_off:
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ret
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endfunc disable_mmu_dcache
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/* -----------------------------------------------------
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* Disable all TLB entries
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* -----------------------------------------------------
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*/
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func invalidate_tlb_all
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tlbi alle3
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dsb sy
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isb
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ret
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endfunc invalidate_tlb_all
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/* -----------------------------------------------------
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* Disable the i cache
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* -----------------------------------------------------
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*/
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func disable_icache
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mrs x0, sctlr_el3
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bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */
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msr sctlr_el3, x0
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isb
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ret
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endfunc disable_icache
|
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/* -----------------------------------------------------
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||||
* Disable all of the i caches
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func invalidate_icache_all
|
||||
ic ialluis
|
||||
isb sy
|
||||
ret
|
||||
endfunc invalidate_icache_all
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Clear the SRAM enabling bit to unmap SRAM
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func platform_unmap_sram
|
||||
ldr x0, =CCU_SRAM_WIN_CR
|
||||
str wzr, [x0]
|
||||
ret
|
||||
endfunc platform_unmap_sram
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Disable the SRAM
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func disable_sram
|
||||
/* Disable the line lockings. They must be disabled expictly
|
||||
* or the OS will have problems using the cache */
|
||||
ldr x1, =MASTER_LLC_TC0_LOCK
|
||||
str wzr, [x1]
|
||||
|
||||
/* Invalidate all ways */
|
||||
ldr w1, =LLC_WAY_MASK
|
||||
ldr x0, =MASTER_LLC_INV_WAY
|
||||
str w1, [x0]
|
||||
|
||||
/* Finally disable LLC */
|
||||
ldr x0, =MASTER_LLC_CTRL
|
||||
str wzr, [x0]
|
||||
|
||||
ret
|
||||
endfunc disable_sram
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Operation when exit bootROM:
|
||||
* Disable the MMU
|
||||
* Disable and invalidate the dcache
|
||||
* Unmap and disable the SRAM
|
||||
* Disable and invalidate the icache
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func marvell_exit_bootrom
|
||||
/* Save the system restore address */
|
||||
mov x28, x0
|
||||
|
||||
/* Close the caches and MMU */
|
||||
bl disable_mmu_dcache
|
||||
|
||||
/*
|
||||
* There is nothing important in the caches now,
|
||||
* so invalidate them instead of cleaning.
|
||||
*/
|
||||
adr x0, __RW_START__
|
||||
adr x1, __RW_END__
|
||||
sub x1, x1, x0
|
||||
bl inv_dcache_range
|
||||
bl invalidate_tlb_all
|
||||
|
||||
/*
|
||||
* Clean the memory mapping of SRAM
|
||||
* the DDR mapping will remain to enable boot image to execute
|
||||
*/
|
||||
bl platform_unmap_sram
|
||||
|
||||
/* Disable the SRAM */
|
||||
bl disable_sram
|
||||
|
||||
/* Disable and invalidate icache */
|
||||
bl disable_icache
|
||||
bl invalidate_icache_all
|
||||
|
||||
mov x0, x28
|
||||
br x0
|
||||
endfunc marvell_exit_bootrom
|
||||
|
||||
/*
|
||||
* Enable L2 UniqueClean evictions with data
|
||||
*/
|
||||
func ca72_l2_enable_unique_clean
|
||||
|
||||
mrs x0, CORTEX_A72_L2ACTLR_EL1
|
||||
orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
|
||||
msr CORTEX_A72_L2ACTLR_EL1, x0
|
||||
|
||||
ret
|
||||
endfunc ca72_l2_enable_unique_clean
|
||||
Reference in New Issue
Block a user