GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <uart8250.h>
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.globl console_core_init
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.globl console_core_putc
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.globl console_core_getc
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.globl console_core_flush
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by console_init and
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* crash reporting.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* Out: return 1 on success else 0 on error
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* Clobber list : x1, x2, x3
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* -----------------------------------------------
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*/
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func console_core_init
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/* Check the input base address */
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cbz x0, core_init_fail
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/* Check baud rate and uart clock for sanity */
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cbz w1, core_init_fail
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cbz w2, core_init_fail
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/* Disable interrupt */
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str wzr, [x0, #UART_IER]
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/* Force DTR and RTS to high */
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mov w3, #(UART_MCR_DTR | UART_MCR_RTS)
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str w3, [x0, #UART_MCR]
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/* Check high speed */
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movz w3, #:abs_g1:115200
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movk w3, #:abs_g0_nc:115200
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cmp w2, w3
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b.hi 1f
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/* Non high speed */
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lsl w2, w2, #4
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mov w3, wzr
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b 2f
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/* High speed */
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1: lsl w2, w2, #2
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mov w3, #2
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/* Set high speed UART register */
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2: str w3, [x0, #UART_HIGHSPEED]
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/* Calculate divisor */
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udiv w3, w1, w2 /* divisor = uartclk / (quot * baudrate) */
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msub w1, w3, w2, w1 /* remainder = uartclk % (quot * baudrate) */
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lsr w2, w2, #1
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cmp w1, w2
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cinc w3, w3, hs
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/* Set line configuration, access divisor latches */
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mov w1, #(UART_LCR_DLAB | UART_LCR_WLS_8)
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str w1, [x0, #UART_LCR]
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/* Set the divisor */
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and w1, w3, #0xff
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str w1, [x0, #UART_DLL]
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lsr w1, w3, #8
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and w1, w1, #0xff
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str w1, [x0, #UART_DLH]
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/* Hide the divisor latches */
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mov w1, #UART_LCR_WLS_8
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str w1, [x0, #UART_LCR]
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/* Enable FIFOs, and clear receive and transmit */
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mov w1, #(UART_FCR_FIFO_EN | UART_FCR_CLEAR_RCVR | \
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UART_FCR_CLEAR_XMIT)
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str w1, [x0, #UART_FCR]
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mov w0, #1
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ret
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core_init_fail:
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mov w0, wzr
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ret
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endfunc console_core_init
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned long base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : w0 - character to be printed
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* x1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_core_putc
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/* Check the input parameter */
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cbz x1, putc_error
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/* Prepend '\r' to '\n' */
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cmp w0, #0xA
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b.ne 2f
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/* Check if the transmit FIFO is full */
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1: ldr w2, [x1, #UART_LSR]
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and w2, w2, #UART_LSR_THRE
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cbz w2, 1b
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mov w2, #0xD
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str w2, [x1, #UART_THR]
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/* Check if the transmit FIFO is full */
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2: ldr w2, [x1, #UART_LSR]
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and w2, w2, #UART_LSR_THRE
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cbz w2, 2b
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str w0, [x1, #UART_THR]
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ret
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putc_error:
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mov w0, #-1
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ret
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endfunc console_core_putc
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/* ---------------------------------------------
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* int console_core_getc(unsigned long base_addr)
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : x0 - console base address
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_core_getc
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cbz x0, getc_error
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/* Check if the receive FIFO is empty */
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1: ldr w1, [x0, #UART_LSR]
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tbz w1, #UART_LSR_DR, 1b
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ldr w0, [x0, #UART_RBR]
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ret
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getc_error:
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mov w0, #-1
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ret
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endfunc console_core_getc
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/* ---------------------------------------------
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* void console_core_flush(uintptr_t base_addr)
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* Function to force a write of all buffered
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* data that hasn't been output.
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* In : x0 - console base address
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* Out : void.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_core_flush
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/* Placeholder */
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ret
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endfunc console_core_flush
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@@ -0,0 +1,112 @@
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/*
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* Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <uart.h>
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static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS];
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static const uint32_t uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
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UART0_BASE,
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UART1_BASE
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};
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void mt_uart_restore(void)
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{
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int uart_idx = UART_PORT0;
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struct mt_uart *uart;
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unsigned long base;
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/* Must NOT print any debug log before UART restore */
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for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS;
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uart_idx++) {
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uart = &uart_save_addr[uart_idx];
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base = uart->base;
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mmio_write_32(UART_LCR(base), UART_LCR_MODE_B);
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mmio_write_32(UART_EFR(base), uart->registers.efr);
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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mmio_write_32(UART_FCR(base), uart->registers.fcr);
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/* baudrate */
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mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed);
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mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l);
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mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m);
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mmio_write_32(UART_LCR(base),
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uart->registers.lcr | UART_LCR_DLAB);
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mmio_write_32(UART_DLL(base), uart->registers.dll);
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mmio_write_32(UART_DLH(base), uart->registers.dlh);
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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mmio_write_32(UART_SAMPLE_COUNT(base),
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uart->registers.sample_count);
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mmio_write_32(UART_SAMPLE_POINT(base),
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uart->registers.sample_point);
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mmio_write_32(UART_GUARD(base), uart->registers.guard);
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/* flow control */
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mmio_write_32(UART_ESCAPE_EN(base), uart->registers.escape_en);
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mmio_write_32(UART_MCR(base), uart->registers.mcr);
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mmio_write_32(UART_IER(base), uart->registers.ier);
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mmio_write_32(UART_SCR(base), uart->registers.scr);
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}
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}
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void mt_uart_save(void)
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{
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int uart_idx = UART_PORT0;
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struct mt_uart *uart;
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unsigned long base;
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for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS;
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uart_idx++) {
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uart_save_addr[uart_idx].base = uart_base_addr[uart_idx];
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base = uart_base_addr[uart_idx];
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uart = &uart_save_addr[uart_idx];
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uart->registers.lcr = mmio_read_32(UART_LCR(base));
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mmio_write_32(UART_LCR(base), UART_LCR_MODE_B);
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uart->registers.efr = mmio_read_32(UART_EFR(base));
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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uart->registers.fcr = mmio_read_32(UART_FCR_RD(base));
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/* baudrate */
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uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base));
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uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base));
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uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base));
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mmio_write_32(UART_LCR(base),
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uart->registers.lcr | UART_LCR_DLAB);
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uart->registers.dll = mmio_read_32(UART_DLL(base));
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uart->registers.dlh = mmio_read_32(UART_DLH(base));
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mmio_write_32(UART_LCR(base), uart->registers.lcr);
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uart->registers.sample_count = mmio_read_32(
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UART_SAMPLE_COUNT(base));
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uart->registers.sample_point = mmio_read_32(
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UART_SAMPLE_POINT(base));
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uart->registers.guard = mmio_read_32(UART_GUARD(base));
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/* flow control */
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uart->registers.escape_en = mmio_read_32(UART_ESCAPE_EN(base));
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uart->registers.mcr = mmio_read_32(UART_MCR(base));
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uart->registers.ier = mmio_read_32(UART_IER(base));
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uart->registers.scr = mmio_read_32(UART_SCR(base));
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}
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}
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void mt_console_uart_cg(int on)
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{
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if (on == 1) {
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mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT);
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} else {
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mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT);
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}
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}
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uint32_t mt_console_uart_cg_status(void)
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{
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return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT;
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}
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@@ -0,0 +1,100 @@
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/*
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* Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef UART_H
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#define UART_H
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#include <platform_def.h>
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/* UART HW information */
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#define HW_SUPPORT_UART_PORTS 2
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#define DRV_SUPPORT_UART_PORTS 2
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/* console UART clock cg */
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#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80)
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#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84)
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#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90)
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#define UART0_CLOCK_GATE_BIT (1U<<22)
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#define UART1_CLOCK_GATE_BIT (1U<<23)
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/* UART registers */
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#define UART_RBR(_baseaddr) (_baseaddr + 0x0)
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#define UART_THR(_baseaddr) (_baseaddr + 0x0)
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#define UART_IER(_baseaddr) (_baseaddr + 0x4)
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#define UART_IIR(_baseaddr) (_baseaddr + 0x8)
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#define UART_FCR(_baseaddr) (_baseaddr + 0x8)
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#define UART_LCR(_baseaddr) (_baseaddr + 0xc)
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#define UART_MCR(_baseaddr) (_baseaddr + 0x10)
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#define UART_LSR(_baseaddr) (_baseaddr + 0x14)
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#define UART_MSR(_baseaddr) (_baseaddr + 0x18)
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#define UART_SCR(_baseaddr) (_baseaddr + 0x1c)
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#define UART_DLL(_baseaddr) (_baseaddr + 0x0)
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#define UART_DLH(_baseaddr) (_baseaddr + 0x4)
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#define UART_EFR(_baseaddr) (_baseaddr + 0x8)
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#define UART_XON1(_baseaddr) (_baseaddr + 0x10)
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#define UART_XON2(_baseaddr) (_baseaddr + 0x14)
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#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18)
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#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c)
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#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20)
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#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24)
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#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28)
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#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c)
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#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30)
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#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34)
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#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38)
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#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c)
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#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40)
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#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44)
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#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48)
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#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c)
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#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50)
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#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54)
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#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58)
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#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C)
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#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0)
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#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4)
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#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8)
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#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC)
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#define UART_LCR_DLAB 0x0080
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#define UART_LCR_MODE_B 0x00bf
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enum uart_port_ID {
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UART_PORT0 = 0,
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UART_PORT1
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};
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struct mt_uart_register {
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uint32_t dll;
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uint32_t dlh;
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uint32_t ier;
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uint32_t lcr;
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uint32_t mcr;
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uint32_t fcr;
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uint32_t lsr;
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uint32_t scr;
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uint32_t efr;
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uint32_t highspeed;
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uint32_t sample_count;
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uint32_t sample_point;
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uint32_t fracdiv_l;
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uint32_t fracdiv_m;
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uint32_t escape_en;
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uint32_t guard;
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uint32_t rx_sel;
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};
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struct mt_uart {
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unsigned long base;
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struct mt_uart_register registers;
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};
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/* external API */
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void mt_uart_save(void);
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void mt_uart_restore(void);
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void mt_console_uart_cg(int on);
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uint32_t mt_console_uart_cg_status(void);
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#endif /* __UART_H__ */
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@@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef UART8250_H
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#define UART8250_H
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/* UART register */
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#define UART_RBR 0x00 /* Receive buffer register */
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#define UART_DLL 0x00 /* Divisor latch lsb */
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#define UART_THR 0x00 /* Transmit holding register */
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#define UART_DLH 0x04 /* Divisor latch msb */
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#define UART_IER 0x04 /* Interrupt enable register */
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#define UART_FCR 0x08 /* FIFO control register */
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#define UART_LCR 0x0c /* Line control register */
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#define UART_MCR 0x10 /* Modem control register */
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#define UART_LSR 0x14 /* Line status register */
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#define UART_HIGHSPEED 0x24 /* High speed UART */
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/* FCR */
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#define UART_FCR_FIFO_EN 0x01 /* enable FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */
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/* LCR */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_DLAB 0x80 /* divisor latch access bit */
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/* MCR */
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#define UART_MCR_DTR 0x01
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#define UART_MCR_RTS 0x02
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/* LSR */
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#endif /* UART8250_H */
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