GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2022, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/psci/psci.h>
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#include <lib/utils.h>
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#ifdef MTK_PUBEVENT_ENABLE
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#include <vendor_pubsub_events.h>
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#endif
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <dfd.h>
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#include <lib/mtk_init/mtk_init.h>
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#include <lib/pm/mtk_pm.h>
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#include <mt_gic_v3.h>
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#include <platform_def.h>
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#define IS_AFFLV_PUBEVENT(_pstate) \
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((_pstate & (MT_CPUPM_PWR_DOMAIN_MCUSYS | MT_CPUPM_PWR_DOMAIN_CLUSTER)) != 0)
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#ifdef MTK_PUBEVENT_ENABLE
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#define MT_CPUPM_EVENT_PWR_ON(x) ({ \
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PUBLISH_EVENT_ARG(mt_cpupm_publish_pwr_on, (const void *)(x)); })
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#define MT_CPUPM_EVENT_PWR_OFF(x) ({ \
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PUBLISH_EVENT_ARG(mt_cpupm_publish_pwr_off, (const void *)(x)); })
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#define MT_CPUPM_EVENT_AFFLV_PWR_ON(x) ({ \
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PUBLISH_EVENT_ARG(mt_cpupm_publish_afflv_pwr_on, (const void *)(x)); })
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#define MT_CPUPM_EVENT_AFFLV_PWR_OFF(x) ({ \
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PUBLISH_EVENT_ARG(mt_cpupm_publish_afflv_pwr_off, (const void *)(x)); })
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#else
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#define MT_CPUPM_EVENT_PWR_ON(x) ({ (void)x; })
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#define MT_CPUPM_EVENT_PWR_OFF(x) ({ (void)x; })
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#define MT_CPUPM_EVENT_AFFLV_PWR_ON(x) ({ (void)x; })
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#define MT_CPUPM_EVENT_AFFLV_PWR_OFF(x) ({ (void)x; })
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#endif
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/*
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* The cpu require to cluster power stattus
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* [0] : The cpu require cluster power down
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* [1] : The cpu require cluster power on
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*/
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#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
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#define coordinate_cluster_pwron() coordinate_cluster(1)
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#define coordinate_cluster_pwroff() coordinate_cluster(0)
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/* defaultly disable all functions */
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#define MTK_CPUPM_FN_MASK_DEFAULT (0)
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struct mtk_cpu_pwr_ctrl {
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unsigned int fn_mask;
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struct mtk_cpu_pm_ops *ops;
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struct mtk_cpu_smp_ops *smp;
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};
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static struct mtk_cpu_pwr_ctrl mtk_cpu_pwr = {
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.fn_mask = MTK_CPUPM_FN_MASK_DEFAULT,
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.ops = NULL,
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};
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#define IS_CPUIDLE_FN_ENABLE(x) ((mtk_cpu_pwr.ops != NULL) && ((mtk_cpu_pwr.fn_mask & x) != 0))
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#define IS_CPUSMP_FN_ENABLE(x) ((mtk_cpu_pwr.smp != NULL) && ((mtk_cpu_pwr.fn_mask & x) != 0))
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/* per-cpu power state */
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static unsigned int armv8_2_power_state[PLATFORM_CORE_COUNT];
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#define armv8_2_get_pwr_stateid(cpu) psci_get_pstate_id(armv8_2_power_state[cpu])
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static unsigned int get_mediatek_pstate(unsigned int domain, unsigned int psci_state,
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struct mtk_cpupm_pwrstate *state)
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{
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_CPUPM_GET_PWR_STATE)) {
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return mtk_cpu_pwr.ops->get_pstate(domain, psci_state, state);
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}
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return 0;
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}
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unsigned int armv8_2_get_pwr_afflv(const psci_power_state_t *state_info)
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{
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int i;
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for (i = (int)PLAT_MAX_PWR_LVL; i >= (int)PSCI_CPU_PWR_LVL; i--) {
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if (is_local_state_run(state_info->pwr_domain_state[i]) == 0) {
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return (unsigned int) i;
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}
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}
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return PSCI_INVALID_PWR_LVL;
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}
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/* MediaTek mcusys power on control interface */
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static void armv8_2_mcusys_pwr_on_common(const struct mtk_cpupm_pwrstate *state)
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{
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gicv3_distif_init();
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mt_gic_distif_restore();
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gic_sgi_restore_all();
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dfd_resume();
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/* Add code here that behavior before system enter mcusys'on */
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_MCUSYS)) {
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mtk_cpu_pwr.ops->mcusys_resume(state);
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}
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}
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/* MediaTek mcusys power down control interface */
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static void armv8_2_mcusys_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state)
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{
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mt_gic_distif_save();
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gic_sgi_save_all();
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/* Add code here that behaves before entering mcusys off */
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_MCUSYS)) {
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mtk_cpu_pwr.ops->mcusys_suspend(state);
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}
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}
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/* MediaTek Cluster power on control interface */
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static void armv8_2_cluster_pwr_on_common(const struct mtk_cpupm_pwrstate *state)
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{
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/* Add code here that behavior before system enter cluster'on */
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#if defined(MTK_CM_MGR) && !defined(MTK_FPGA_EARLY_PORTING)
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/* init cpu stall counter */
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init_cpu_stall_counter_all();
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#endif
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_CLUSTER)) {
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mtk_cpu_pwr.ops->cluster_resume(state);
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}
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}
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/* MediaTek Cluster power down control interface */
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static void armv8_2_cluster_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state)
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{
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_CLUSTER)) {
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mtk_cpu_pwr.ops->cluster_suspend(state);
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}
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}
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/* MediaTek CPU power on control interface */
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static void armv8_2_cpu_pwr_on_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
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{
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coordinate_cluster_pwron();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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/* If MCUSYS has been powered down then restore GIC redistributor for all CPUs. */
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if (IS_PLAT_SYSTEM_RETENTION(state->pwr.afflv)) {
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mt_gic_rdistif_restore_all();
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} else {
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mt_gic_rdistif_restore();
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}
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}
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/* MediaTek CPU power down control interface */
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static void armv8_2_cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
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{
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if ((pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU) != 0) {
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coordinate_cluster_pwroff();
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}
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mt_gic_rdistif_save();
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gicv3_cpuif_disable(plat_my_core_pos());
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gicv3_rdistif_off(plat_my_core_pos());
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}
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static void armv8_2_cpu_pwr_resume(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
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{
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armv8_2_cpu_pwr_on_common(state, pstate);
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_CORE)) {
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mtk_cpu_pwr.ops->cpu_resume(state);
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}
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}
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static void armv8_2_cpu_pwr_suspend(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
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{
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_CORE)) {
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mtk_cpu_pwr.ops->cpu_suspend(state);
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}
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armv8_2_cpu_pwr_dwn_common(state, pstate);
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}
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static void armv8_2_cpu_pwr_on(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
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{
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armv8_2_cpu_pwr_on_common(state, pstate);
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if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_SMP_CORE_ON)) {
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mtk_cpu_pwr.smp->cpu_on(state);
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}
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}
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static void armv8_2_cpu_pwr_off(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
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{
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if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_SMP_CORE_OFF)) {
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mtk_cpu_pwr.smp->cpu_off(state);
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}
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armv8_2_cpu_pwr_dwn_common(state, pstate);
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}
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/* MediaTek PSCI power domain */
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static int armv8_2_power_domain_on(u_register_t mpidr)
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{
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int ret = PSCI_E_SUCCESS;
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int cpu = plat_core_pos_by_mpidr(mpidr);
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uintptr_t entry = plat_pm_get_warm_entry();
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if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_PWR_ON_CORE_PREPARE)) {
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if (mtk_cpu_pwr.smp->cpu_pwr_on_prepare(cpu, entry) != 0) {
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ret = PSCI_E_DENIED;
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}
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}
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INFO("CPU %u power domain prepare on\n", cpu);
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return ret;
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}
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/* MediaTek PSCI power domain */
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static void armv8_2_power_domain_on_finish(const psci_power_state_t *state)
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{
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struct mt_cpupm_event_data nb;
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unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU);
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struct mtk_cpupm_pwrstate pm_state = {
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.info = {
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.cpuid = plat_my_core_pos(),
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.mode = MTK_CPU_PM_SMP,
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},
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.pwr = {
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.afflv = armv8_2_get_pwr_afflv(state),
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.state_id = 0x0,
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},
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};
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armv8_2_cpu_pwr_on(&pm_state, pstate);
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nb.cpuid = pm_state.info.cpuid;
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nb.pwr_domain = pstate;
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MT_CPUPM_EVENT_PWR_ON(&nb);
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INFO("CPU %u power domain on finished\n", pm_state.info.cpuid);
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}
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/* MediaTek PSCI power domain */
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static void armv8_2_power_domain_off(const psci_power_state_t *state)
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{
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struct mt_cpupm_event_data nb;
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unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU);
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struct mtk_cpupm_pwrstate pm_state = {
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.info = {
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.cpuid = plat_my_core_pos(),
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.mode = MTK_CPU_PM_SMP,
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},
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.pwr = {
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.afflv = armv8_2_get_pwr_afflv(state),
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.state_id = 0x0,
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},
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};
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armv8_2_cpu_pwr_off(&pm_state, pstate);
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nb.cpuid = pm_state.info.cpuid;
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nb.pwr_domain = pstate;
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MT_CPUPM_EVENT_PWR_OFF(&nb);
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INFO("CPU %u power domain off\n", pm_state.info.cpuid);
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}
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/* MediaTek PSCI power domain */
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static void armv8_2_power_domain_suspend(const psci_power_state_t *state)
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{
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unsigned int pstate = 0;
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struct mt_cpupm_event_data nb;
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struct mtk_cpupm_pwrstate pm_state = {
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.info = {
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.cpuid = plat_my_core_pos(),
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.mode = MTK_CPU_PM_CPUIDLE,
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},
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};
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pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid);
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pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state);
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pm_state.pwr.raw = state;
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pstate = get_mediatek_pstate(CPUPM_PWR_OFF,
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armv8_2_power_state[pm_state.info.cpuid], &pm_state);
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armv8_2_cpu_pwr_suspend(&pm_state, pstate);
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if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) {
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armv8_2_cluster_pwr_dwn_common(&pm_state);
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}
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if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) {
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armv8_2_mcusys_pwr_dwn_common(&pm_state);
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}
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nb.cpuid = pm_state.info.cpuid;
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nb.pwr_domain = pstate;
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MT_CPUPM_EVENT_PWR_OFF(&nb);
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if (IS_AFFLV_PUBEVENT(pstate)) {
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MT_CPUPM_EVENT_AFFLV_PWR_OFF(&nb);
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}
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}
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/* MediaTek PSCI power domain */
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static void armv8_2_power_domain_suspend_finish(const psci_power_state_t *state)
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{
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unsigned int pstate = 0;
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struct mt_cpupm_event_data nb;
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struct mtk_cpupm_pwrstate pm_state = {
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.info = {
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.cpuid = plat_my_core_pos(),
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.mode = MTK_CPU_PM_CPUIDLE,
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},
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};
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pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid);
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pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state);
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pm_state.pwr.raw = state;
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pstate = get_mediatek_pstate(CPUPM_PWR_ON,
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armv8_2_power_state[pm_state.info.cpuid], &pm_state);
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if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) {
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armv8_2_mcusys_pwr_on_common(&pm_state);
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}
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if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) {
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armv8_2_cluster_pwr_on_common(&pm_state);
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}
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armv8_2_cpu_pwr_resume(&pm_state, pstate);
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nb.cpuid = pm_state.info.cpuid;
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nb.pwr_domain = pstate;
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MT_CPUPM_EVENT_PWR_ON(&nb);
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if (IS_AFFLV_PUBEVENT(pstate)) {
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MT_CPUPM_EVENT_AFFLV_PWR_ON(&nb);
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}
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}
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/* MediaTek PSCI power domain */
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static int armv8_2_validate_power_state(unsigned int power_state, psci_power_state_t *req_state)
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{
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unsigned int i;
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unsigned int pstate = psci_get_pstate_type(power_state);
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unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
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unsigned int my_core_pos = plat_my_core_pos();
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if (mtk_cpu_pwr.ops == NULL) {
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return PSCI_E_INVALID_PARAMS;
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}
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if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_PWR_STATE_VALID)) {
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if (mtk_cpu_pwr.ops->pwr_state_valid(aff_lvl, pstate) != 0) {
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return PSCI_E_INVALID_PARAMS;
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}
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}
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if (pstate == PSTATE_TYPE_STANDBY) {
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req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
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} else {
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for (i = PSCI_CPU_PWR_LVL; i <= aff_lvl; i++) {
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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}
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armv8_2_power_state[my_core_pos] = power_state;
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return PSCI_E_SUCCESS;
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}
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/* MediaTek PSCI power domain */
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#if CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND
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static void armv8_2_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int i;
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int ret;
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unsigned int power_state;
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unsigned int my_core_pos = plat_my_core_pos();
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ret = mtk_cpu_pwr.ops->pwr_state_valid(PLAT_MAX_PWR_LVL,
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PSTATE_TYPE_POWERDOWN);
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if (ret != MTK_CPUPM_E_OK) {
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/* Avoid suspend due to platform is not ready. */
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req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] =
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PLAT_MAX_RET_STATE;
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for (i = PSCI_CPU_PWR_LVL + 1; i <= PLAT_MAX_PWR_LVL; i++) {
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req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
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}
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power_state = psci_make_powerstate(0, PSTATE_TYPE_STANDBY, PSCI_CPU_PWR_LVL);
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} else {
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for (i = PSCI_CPU_PWR_LVL; i <= PLAT_MAX_PWR_LVL; i++) {
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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power_state = psci_make_powerstate(MT_PLAT_PWR_STATE_SUSPEND,
|
||||
PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
|
||||
}
|
||||
|
||||
armv8_2_power_state[my_core_pos] = power_state;
|
||||
flush_dcache_range((uintptr_t)&armv8_2_power_state[my_core_pos],
|
||||
sizeof(armv8_2_power_state[my_core_pos]));
|
||||
}
|
||||
#endif
|
||||
static void armv8_2_pm_smp_init(unsigned int cpu_id, uintptr_t entry_point)
|
||||
{
|
||||
if (entry_point == 0) {
|
||||
ERROR("%s, warm_entry_point is null\n", __func__);
|
||||
panic();
|
||||
}
|
||||
if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_SMP_INIT)) {
|
||||
mtk_cpu_pwr.smp->init(cpu_id, entry_point);
|
||||
}
|
||||
INFO("[%s:%d] - Initialize finished\n", __func__, __LINE__);
|
||||
}
|
||||
|
||||
static struct plat_pm_pwr_ctrl armv8_2_pwr_ops = {
|
||||
.pwr_domain_suspend = armv8_2_power_domain_suspend,
|
||||
.pwr_domain_suspend_finish = armv8_2_power_domain_suspend_finish,
|
||||
.validate_power_state = armv8_2_validate_power_state,
|
||||
#if CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND
|
||||
.get_sys_suspend_power_state = armv8_2_get_sys_suspend_power_state,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct plat_pm_smp_ctrl armv8_2_smp_ops = {
|
||||
.init = armv8_2_pm_smp_init,
|
||||
.pwr_domain_on = armv8_2_power_domain_on,
|
||||
.pwr_domain_off = armv8_2_power_domain_off,
|
||||
.pwr_domain_on_finish = armv8_2_power_domain_on_finish,
|
||||
};
|
||||
|
||||
#define ISSUE_CPU_PM_REG_FAIL(_success) ({ _success = false; assert(0); })
|
||||
|
||||
#define CPM_PM_FN_CHECK(_fns, _ops, _id, _func, _result, _flag) ({ \
|
||||
if ((_fns & _id)) { \
|
||||
if (_ops->_func) \
|
||||
_flag |= _id; \
|
||||
else { \
|
||||
ISSUE_CPU_PM_REG_FAIL(_result); \
|
||||
} \
|
||||
} })
|
||||
|
||||
int register_cpu_pm_ops(unsigned int fn_flags, struct mtk_cpu_pm_ops *ops)
|
||||
{
|
||||
bool success = true;
|
||||
unsigned int fns = 0;
|
||||
|
||||
if ((ops == NULL) || (mtk_cpu_pwr.ops != NULL)) {
|
||||
ERROR("[%s:%d] register cpu_pm fail !!\n", __FILE__, __LINE__);
|
||||
return MTK_CPUPM_E_ERR;
|
||||
}
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_RESUME_CORE,
|
||||
cpu_resume, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SUSPEND_CORE,
|
||||
cpu_suspend, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_RESUME_CLUSTER,
|
||||
cluster_resume, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SUSPEND_CLUSTER,
|
||||
cluster_suspend, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_RESUME_MCUSYS,
|
||||
mcusys_resume, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SUSPEND_MCUSYS,
|
||||
mcusys_suspend, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_CPUPM_GET_PWR_STATE,
|
||||
get_pstate, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_PWR_STATE_VALID,
|
||||
pwr_state_valid, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_INIT,
|
||||
init, success, fns);
|
||||
|
||||
if (success) {
|
||||
mtk_cpu_pwr.ops = ops;
|
||||
mtk_cpu_pwr.fn_mask |= fns;
|
||||
plat_pm_ops_setup_pwr(&armv8_2_pwr_ops);
|
||||
INFO("[%s:%d] CPU pwr ops register success, support:0x%x\n",
|
||||
__func__, __LINE__, fns);
|
||||
} else {
|
||||
ERROR("[%s:%d] register cpu_pm ops fail !, fn:0x%x\n",
|
||||
__func__, __LINE__, fn_flags);
|
||||
assert(0);
|
||||
}
|
||||
return MTK_CPUPM_E_OK;
|
||||
}
|
||||
|
||||
int register_cpu_smp_ops(unsigned int fn_flags, struct mtk_cpu_smp_ops *ops)
|
||||
{
|
||||
bool success = true;
|
||||
unsigned int fns = 0;
|
||||
|
||||
if ((ops == NULL) || (mtk_cpu_pwr.smp != NULL)) {
|
||||
ERROR("[%s:%d] register cpu_smp fail !!\n", __FILE__, __LINE__);
|
||||
return MTK_CPUPM_E_ERR;
|
||||
}
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SMP_INIT,
|
||||
init, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_PWR_ON_CORE_PREPARE,
|
||||
cpu_pwr_on_prepare, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SMP_CORE_ON,
|
||||
cpu_on, success, fns);
|
||||
|
||||
CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SMP_CORE_OFF,
|
||||
cpu_off, success, fns);
|
||||
|
||||
if (success == true) {
|
||||
mtk_cpu_pwr.smp = ops;
|
||||
mtk_cpu_pwr.fn_mask |= fns;
|
||||
plat_pm_ops_setup_smp(&armv8_2_smp_ops);
|
||||
INFO("[%s:%d] CPU smp ops register success, support:0x%x\n",
|
||||
__func__, __LINE__, fns);
|
||||
} else {
|
||||
ERROR("[%s:%d] register cpu_smp ops fail !, fn:0x%x\n",
|
||||
__func__, __LINE__, fn_flags);
|
||||
assert(0);
|
||||
}
|
||||
return MTK_CPUPM_E_OK;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright (c) 2022, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
LOCAL_DIR := $(call GET_LOCAL_DIR)
|
||||
|
||||
MODULE := armv${CONFIG_MTK_PM_ARCH}
|
||||
LOCAL_SRCS-y := ${LOCAL_DIR}/pwr_ctrl.c
|
||||
|
||||
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
|
||||
Reference in New Issue
Block a user