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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/crypt/crypt.c
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <mt8173_def.h>
#include <mtk_sip_svc.h>
#define crypt_read32(offset) \
mmio_read_32((uintptr_t)(CRYPT_BASE+((offset) * 4)))
#define crypt_write32(offset, value) \
mmio_write_32((uintptr_t)(CRYPT_BASE + ((offset) * 4)), (uint32_t)value)
#define GET_L32(x) ((uint32_t)(x & 0xffffffff))
#define GET_H32(x) ((uint32_t)((x >> 32) & 0xffffffff))
#define REG_INIT 0
#define REG_MSC 4
#define REG_TRIG 256
#define REG_STAT 512
#define REG_CLR 513
#define REG_INT 514
#define REG_P68 768
#define REG_P69 769
#define REG_P70 770
#define REG_P71 771
#define REG_P72 772
#define REG_D20 820
#define KEY_SIZE 160
#define KEY_LEN 40
/* Wait until crypt is completed */
uint64_t crypt_wait(void)
{
crypt_write32(REG_TRIG, 0);
while (crypt_read32(REG_STAT) == 0)
;
udelay(100);
crypt_write32(REG_CLR, crypt_read32(REG_STAT));
crypt_write32(REG_INT, 0);
return MTK_SIP_E_SUCCESS;
}
static uint32_t record[4];
/* Copy encrypted key to crypt engine */
uint64_t crypt_set_hdcp_key_ex(uint64_t x1, uint64_t x2, uint64_t x3)
{
uint32_t i = (uint32_t)x1;
uint32_t j = 0;
if (i > KEY_LEN)
return MTK_SIP_E_INVALID_PARAM;
if (i < KEY_LEN) {
crypt_write32(REG_MSC, 0x80ff3800);
crypt_write32(REG_INIT, 0);
crypt_write32(REG_INIT, 0xF);
crypt_write32(REG_CLR, 1);
crypt_write32(REG_INT, 0);
crypt_write32(REG_P68, 0x70);
crypt_write32(REG_P69, 0x1C0);
crypt_write32(REG_P70, 0x30);
crypt_write32(REG_P71, 0x4);
crypt_wait();
crypt_write32(REG_D20 + 4 * i, GET_L32(x2));
crypt_write32(REG_D20 + 4 * i + 1, GET_H32(x2));
crypt_write32(REG_D20 + 4 * i + 2, GET_L32(x3));
crypt_write32(REG_D20 + 4 * i + 3, GET_H32(x3));
crypt_write32(REG_P69, 0);
crypt_write32(REG_P68, 0x20);
crypt_write32(REG_P71, 0x34 + 4 * i);
crypt_write32(REG_P72, 0x34 + 4 * i);
crypt_wait();
for (j = 0; j < 4; j++) {
crypt_write32(REG_P68, 0x71);
crypt_write32(REG_P69, 0x34 + 4 * i + j);
crypt_write32(REG_P70, record[j]);
crypt_wait();
}
}
/* Prepare data for next iteration */
record[0] = GET_L32(x2);
record[1] = GET_H32(x2);
record[2] = GET_L32(x3);
record[3] = GET_H32(x3);
return MTK_SIP_E_SUCCESS;
}
/* Set key to hdcp */
uint64_t crypt_set_hdcp_key_num(uint32_t num)
{
if (num > KEY_LEN)
return MTK_SIP_E_INVALID_PARAM;
crypt_write32(REG_P68, 0x6A);
crypt_write32(REG_P69, 0x34 + 4 * num);
crypt_wait();
return MTK_SIP_E_SUCCESS;
}
/* Clear key in crypt engine */
uint64_t crypt_clear_hdcp_key(void)
{
uint32_t i;
for (i = 0; i < KEY_SIZE; i++)
crypt_write32(REG_D20 + i, 0);
return MTK_SIP_E_SUCCESS;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/crypt/crypt.h
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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CRYPT_H
#define CRYPT_H
#include <stdint.h>
/* crypt function prototype */
uint64_t crypt_set_hdcp_key_ex(uint64_t x1, uint64_t x2, uint64_t x3);
uint64_t crypt_set_hdcp_key_num(uint32_t num);
uint64_t crypt_clear_hdcp_key(void);
#endif /* CRYPT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <mt8173_def.h>
#include <mtcmos.h>
#include <spm.h>
#include <spm_mcdi.h>
enum {
SRAM_ISOINT_B = 1U << 6,
SRAM_CKISO = 1U << 5,
PWR_CLK_DIS = 1U << 4,
PWR_ON_2ND = 1U << 3,
PWR_ON = 1U << 2,
PWR_ISO = 1U << 1,
PWR_RST_B = 1U << 0
};
enum {
L1_PDN_ACK = 1U << 8,
L1_PDN = 1U << 0
};
enum {
LITTLE_CPU3 = 1U << 12,
LITTLE_CPU2 = 1U << 11,
LITTLE_CPU1 = 1U << 10,
};
enum {
SRAM_PDN = 0xf << 8,
DIS_SRAM_ACK = 0x1 << 12,
AUD_SRAM_ACK = 0xf << 12,
};
enum {
DIS_PWR_STA_MASK = 0x1 << 3,
AUD_PWR_STA_MASK = 0x1 << 24,
};
#define SPM_VDE_PWR_CON 0x0210
#define SPM_MFG_PWR_CON 0x0214
#define SPM_VEN_PWR_CON 0x0230
#define SPM_ISP_PWR_CON 0x0238
#define SPM_DIS_PWR_CON 0x023c
#define SPM_VEN2_PWR_CON 0x0298
#define SPM_AUDIO_PWR_CON 0x029c
#define SPM_MFG_2D_PWR_CON 0x02c0
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
#define SPM_USB_PWR_CON 0x02cc
#define MTCMOS_CTRL_SUCCESS 0
#define MTCMOS_CTRL_ERROR -1
#define MTCMOS_CTRL_EN (0x1 << 18)
#define VDE_PWR_ON 0
#define VEN_PWR_ON 1
#define ISP_PWR_ON 2
#define DIS_PWR_ON 3
#define VEN2_PWR_ON 4
#define AUDIO_PWR_ON 5
#define MFG_ASYNC_PWR_ON 6
#define MFG_2D_PWR_ON 7
#define MFG_PWR_ON 8
#define USB_PWR_ON 9
#define VDE_PWR_OFF 10
#define VEN_PWR_OFF 11
#define ISP_PWR_OFF 12
#define DIS_PWR_OFF 13
#define VEN2_PWR_OFF 14
#define AUDIO_PWR_OFF 15
#define MFG_ASYNC_PWR_OFF 16
#define MFG_2D_PWR_OFF 17
#define MFG_PWR_OFF 18
#define USB_PWR_OFF 19
#define VDE_PWR_CON_PWR_STA 7
#define VEN_PWR_CON_PWR_STA 21
#define ISP_PWR_CON_PWR_STA 5
#define DIS_PWR_CON_PWR_STA 3
#define VEN2_PWR_CON_PWR_STA 20
#define AUDIO_PWR_CON_PWR_STA 24
#define MFG_ASYNC_PWR_CON_PWR_STA 23
#define MFG_2D_PWR_CON_PWR_STA 22
#define MFG_PWR_CON_PWR_STA 4
#define USB_PWR_CON_PWR_STA 25
/*
* Timeout if the ack is not signled after 1 second.
* According to designer, one mtcmos operation should be done
* around 10us.
*/
#define MTCMOS_ACK_POLLING_MAX_COUNT 10000
#define MTCMOS_ACK_POLLING_INTERVAL 10
static void mtcmos_ctrl_little_off(unsigned int linear_id)
{
uint32_t reg_pwr_con;
uint32_t reg_l1_pdn;
uint32_t bit_cpu;
switch (linear_id) {
case 1:
reg_pwr_con = SPM_CA7_CPU1_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU1_L1_PDN;
bit_cpu = LITTLE_CPU1;
break;
case 2:
reg_pwr_con = SPM_CA7_CPU2_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU2_L1_PDN;
bit_cpu = LITTLE_CPU2;
break;
case 3:
reg_pwr_con = SPM_CA7_CPU3_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU3_L1_PDN;
bit_cpu = LITTLE_CPU3;
break;
default:
/* should never come to here */
return;
}
/* enable register control */
mmio_write_32(SPM_POWERON_CONFIG_SET,
(SPM_PROJECT_CODE << 16) | (1U << 0));
mmio_setbits_32(reg_pwr_con, PWR_ISO);
mmio_setbits_32(reg_pwr_con, SRAM_CKISO);
mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B);
mmio_setbits_32(reg_l1_pdn, L1_PDN);
while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK))
continue;
mmio_clrbits_32(reg_pwr_con, PWR_RST_B);
mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS);
mmio_clrbits_32(reg_pwr_con, PWR_ON);
mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND);
while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) ||
(mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu))
continue;
}
void mtcmos_little_cpu_off(void)
{
/* turn off little cpu 1 - 3 */
mtcmos_ctrl_little_off(1);
mtcmos_ctrl_little_off(2);
mtcmos_ctrl_little_off(3);
}
uint32_t wait_mtcmos_ack(uint32_t on, uint32_t pwr_ctrl, uint32_t spm_pwr_sta)
{
int i = 0;
uint32_t cmp, pwr_sta, pwr_sta_2nd;
while (1) {
cmp = mmio_read_32(SPM_PCM_PASR_DPD_3) & pwr_ctrl;
pwr_sta = (mmio_read_32(SPM_PWR_STATUS) >> spm_pwr_sta) & 1;
pwr_sta_2nd =
(mmio_read_32(SPM_PWR_STATUS_2ND) >> spm_pwr_sta) & 1;
if (cmp && (pwr_sta == on) && (pwr_sta_2nd == on)) {
mmio_write_32(SPM_PCM_RESERVE2, 0);
return MTCMOS_CTRL_SUCCESS;
}
udelay(MTCMOS_ACK_POLLING_INTERVAL);
i++;
if (i > MTCMOS_ACK_POLLING_MAX_COUNT) {
INFO("MTCMOS control failed(%d), SPM_PWR_STA(%d),\n"
"SPM_PCM_RESERVE=0x%x,SPM_PCM_RESERVE2=0x%x,\n"
"SPM_PWR_STATUS=0x%x,SPM_PWR_STATUS_2ND=0x%x\n"
"SPM_PCM_PASR_DPD_3 = 0x%x\n",
on, spm_pwr_sta, mmio_read_32(SPM_PCM_RESERVE),
mmio_read_32(SPM_PCM_RESERVE2),
mmio_read_32(SPM_PWR_STATUS),
mmio_read_32(SPM_PWR_STATUS_2ND),
mmio_read_32(SPM_PCM_PASR_DPD_3));
mmio_write_32(SPM_PCM_RESERVE2, 0);
return MTCMOS_CTRL_ERROR;
}
}
}
uint32_t mtcmos_non_cpu_ctrl(uint32_t on, uint32_t mtcmos_num)
{
uint32_t ret = MTCMOS_CTRL_SUCCESS;
uint32_t power_on;
uint32_t power_off;
uint32_t power_ctrl;
uint32_t power_status;
spm_lock_get();
spm_mcdi_prepare_for_mtcmos();
mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
switch (mtcmos_num) {
case SPM_VDE_PWR_CON:
power_on = VDE_PWR_ON;
power_off = VDE_PWR_OFF;
power_status = VDE_PWR_CON_PWR_STA;
break;
case SPM_MFG_PWR_CON:
power_on = MFG_PWR_ON;
power_off = MFG_PWR_OFF;
power_status = MFG_PWR_CON_PWR_STA;
break;
case SPM_VEN_PWR_CON:
power_on = VEN_PWR_ON;
power_off = VEN_PWR_OFF;
power_status = VEN_PWR_CON_PWR_STA;
break;
case SPM_ISP_PWR_CON:
power_on = ISP_PWR_ON;
power_off = ISP_PWR_OFF;
power_status = ISP_PWR_CON_PWR_STA;
break;
case SPM_DIS_PWR_CON:
power_on = DIS_PWR_ON;
power_off = DIS_PWR_OFF;
power_status = DIS_PWR_CON_PWR_STA;
break;
case SPM_VEN2_PWR_CON:
power_on = VEN2_PWR_ON;
power_off = VEN2_PWR_OFF;
power_status = VEN2_PWR_CON_PWR_STA;
break;
case SPM_AUDIO_PWR_CON:
power_on = AUDIO_PWR_ON;
power_off = AUDIO_PWR_OFF;
power_status = AUDIO_PWR_CON_PWR_STA;
break;
case SPM_MFG_2D_PWR_CON:
power_on = MFG_2D_PWR_ON;
power_off = MFG_2D_PWR_OFF;
power_status = MFG_2D_PWR_CON_PWR_STA;
break;
case SPM_MFG_ASYNC_PWR_CON:
power_on = MFG_ASYNC_PWR_ON;
power_off = MFG_ASYNC_PWR_OFF;
power_status = MFG_ASYNC_PWR_CON_PWR_STA;
break;
case SPM_USB_PWR_CON:
power_on = USB_PWR_ON;
power_off = USB_PWR_OFF;
power_status = USB_PWR_CON_PWR_STA;
break;
default:
ret = MTCMOS_CTRL_ERROR;
INFO("No mapping MTCMOS(%d), ret = %d\n", mtcmos_num, ret);
break;
}
if (ret == MTCMOS_CTRL_SUCCESS) {
power_ctrl = on ? (1 << power_on) : (1 << power_off);
mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl);
ret = wait_mtcmos_ack(on, power_ctrl, power_status);
VERBOSE("0x%x(%d), PWR_STATUS(0x%x), ret(%d)\n",
power_ctrl, on, mmio_read_32(SPM_PWR_STATUS), ret);
}
mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
spm_lock_release();
return ret;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTCMOS_H
#define MTCMOS_H
/*
* This function will turn off all the little core's power except cpu 0. The
* cores in cluster 0 are all powered when the system power on. The System
* Power Manager (SPM) will do nothing if it found the core's power was on
* during CPU_ON psci call.
*/
void mtcmos_little_cpu_off(void);
uint32_t mtcmos_non_cpu_ctrl(uint32_t on, uint32_t mtcmos_num);
#endif /* MTCMOS_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PMIC_WRAP_INIT_H
#define PMIC_WRAP_INIT_H
#include <platform_def.h>
/* external API */
int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
int32_t pwrap_write(uint32_t adr, uint32_t wdata);
static struct mt8173_pmic_wrap_regs *const mtk_pwrap =
(void *)PMIC_WRAP_BASE;
/* timeout setting */
enum {
TIMEOUT_RESET = 50, /* us */
TIMEOUT_READ = 50, /* us */
TIMEOUT_WAIT_IDLE = 50 /* us */
};
/* PMIC_WRAP registers */
struct mt8173_pmic_wrap_regs {
uint32_t mux_sel;
uint32_t wrap_en;
uint32_t dio_en;
uint32_t sidly;
uint32_t rddmy;
uint32_t si_ck_con;
uint32_t cshext_write;
uint32_t cshext_read;
uint32_t cslext_start;
uint32_t cslext_end;
uint32_t staupd_prd;
uint32_t staupd_grpen;
uint32_t reserved[4];
uint32_t staupd_man_trig;
uint32_t staupd_sta;
uint32_t wrap_sta;
uint32_t harb_init;
uint32_t harb_hprio;
uint32_t hiprio_arb_en;
uint32_t harb_sta0;
uint32_t harb_sta1;
uint32_t man_en;
uint32_t man_cmd;
uint32_t man_rdata;
uint32_t man_vldclr;
uint32_t wacs0_en;
uint32_t init_done0;
uint32_t wacs0_cmd;
uint32_t wacs0_rdata;
uint32_t wacs0_vldclr;
uint32_t wacs1_en;
uint32_t init_done1;
uint32_t wacs1_cmd;
uint32_t wacs1_rdata;
uint32_t wacs1_vldclr;
uint32_t wacs2_en;
uint32_t init_done2;
uint32_t wacs2_cmd;
uint32_t wacs2_rdata;
uint32_t wacs2_vldclr;
uint32_t int_en;
uint32_t int_flg_raw;
uint32_t int_flg;
uint32_t int_clr;
uint32_t sig_adr;
uint32_t sig_mode;
uint32_t sig_value;
uint32_t sig_errval;
uint32_t crc_en;
uint32_t timer_en;
uint32_t timer_sta;
uint32_t wdt_unit;
uint32_t wdt_src_en;
uint32_t wdt_flg;
uint32_t debug_int_sel;
uint32_t dvfs_adr0;
uint32_t dvfs_wdata0;
uint32_t dvfs_adr1;
uint32_t dvfs_wdata1;
uint32_t dvfs_adr2;
uint32_t dvfs_wdata2;
uint32_t dvfs_adr3;
uint32_t dvfs_wdata3;
uint32_t dvfs_adr4;
uint32_t dvfs_wdata4;
uint32_t dvfs_adr5;
uint32_t dvfs_wdata5;
uint32_t dvfs_adr6;
uint32_t dvfs_wdata6;
uint32_t dvfs_adr7;
uint32_t dvfs_wdata7;
uint32_t spminf_sta;
uint32_t cipher_key_sel;
uint32_t cipher_iv_sel;
uint32_t cipher_en;
uint32_t cipher_rdy;
uint32_t cipher_mode;
uint32_t cipher_swrst;
uint32_t dcm_en;
uint32_t dcm_dbc_prd;
};
enum {
RDATA_WACS_RDATA_SHIFT = 0,
RDATA_WACS_FSM_SHIFT = 16,
RDATA_WACS_REQ_SHIFT = 19,
RDATA_SYNC_IDLE_SHIFT,
RDATA_INIT_DONE_SHIFT,
RDATA_SYS_IDLE_SHIFT,
};
enum {
RDATA_WACS_RDATA_MASK = 0xffff,
RDATA_WACS_FSM_MASK = 0x7,
RDATA_WACS_REQ_MASK = 0x1,
RDATA_SYNC_IDLE_MASK = 0x1,
RDATA_INIT_DONE_MASK = 0x1,
RDATA_SYS_IDLE_MASK = 0x1,
};
/* WACS_FSM */
enum {
WACS_FSM_IDLE = 0x00,
WACS_FSM_REQ = 0x02,
WACS_FSM_WFDLE = 0x04,
WACS_FSM_WFVLDCLR = 0x06,
WACS_INIT_DONE = 0x01,
WACS_SYNC_IDLE = 0x01,
WACS_SYNC_BUSY = 0x00
};
/* error information flag */
enum {
E_PWR_INVALID_ARG = 1,
E_PWR_INVALID_RW = 2,
E_PWR_INVALID_ADDR = 3,
E_PWR_INVALID_WDAT = 4,
E_PWR_INVALID_OP_MANUAL = 5,
E_PWR_NOT_IDLE_STATE = 6,
E_PWR_NOT_INIT_DONE = 7,
E_PWR_NOT_INIT_DONE_READ = 8,
E_PWR_WAIT_IDLE_TIMEOUT = 9,
E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
E_PWR_INIT_SIDLY_FAIL = 11,
E_PWR_RESET_TIMEOUT = 12,
E_PWR_TIMEOUT = 13,
E_PWR_INIT_RESET_SPI = 20,
E_PWR_INIT_SIDLY = 21,
E_PWR_INIT_REG_CLOCK = 22,
E_PWR_INIT_ENABLE_PMIC = 23,
E_PWR_INIT_DIO = 24,
E_PWR_INIT_CIPHER = 25,
E_PWR_INIT_WRITE_TEST = 26,
E_PWR_INIT_ENABLE_CRC = 27,
E_PWR_INIT_ENABLE_DEWRAP = 28,
E_PWR_INIT_ENABLE_EVENT = 29,
E_PWR_READ_TEST_FAIL = 30,
E_PWR_WRITE_TEST_FAIL = 31,
E_PWR_SWITCH_DIO = 32
};
#endif /* PMIC_WRAP_INIT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/rtc/rtc.c
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
#include <mt8173_def.h>
#include <rtc.h>
void rtc_bbpu_power_down(void)
{
uint16_t bbpu;
/* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN;
if (Writeif_unlock()) {
RTC_Write(RTC_BBPU, bbpu);
if (!RTC_Write_Trigger())
assert(0);
} else {
assert(0);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/rtc/rtc.h
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RTC_H
#define RTC_H
/* RTC registers */
enum {
RTC_BBPU = 0xE000,
RTC_IRQ_STA = 0xE002,
RTC_IRQ_EN = 0xE004,
RTC_CII_EN = 0xE006
};
enum {
RTC_OSC32CON = 0xE026,
RTC_CON = 0xE03E,
RTC_WRTGR = 0xE03C
};
enum {
RTC_PDN1 = 0xE02C,
RTC_PDN2 = 0xE02E,
RTC_SPAR0 = 0xE030,
RTC_SPAR1 = 0xE032,
RTC_PROT = 0xE036,
RTC_DIFF = 0xE038,
RTC_CALI = 0xE03A
};
enum {
RTC_PROT_UNLOCK1 = 0x586A,
RTC_PROT_UNLOCK2 = 0x9136
};
enum {
RTC_BBPU_PWREN = 1U << 0,
RTC_BBPU_BBPU = 1U << 2,
RTC_BBPU_AUTO = 1U << 3,
RTC_BBPU_CLRPKY = 1U << 4,
RTC_BBPU_RELOAD = 1U << 5,
RTC_BBPU_CBUSY = 1U << 6
};
enum {
RTC_BBPU_KEY = 0x43 << 8
};
/* external API */
uint16_t RTC_Read(uint32_t addr);
void RTC_Write(uint32_t addr, uint16_t data);
int32_t rtc_busy_wait(void);
int32_t RTC_Write_Trigger(void);
int32_t Writeif_unlock(void);
void rtc_bbpu_power_down(void);
#endif /* RTC_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm.c
+370
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <mt8173_def.h>
#include <spm.h>
#include <spm_suspend.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware, i.e.,
* - spm_hotplug.c for cpu power control in cpu hotplug flow.
* - spm_mcdi.c for cpu power control in cpu idle power saving state.
* - spm_suspend.c for system power control in system suspend scenario.
*
* This file provide utility functions common to hotplug, mcdi(idle), suspend
* power scenarios. A bakery lock (software lock) is incoporated to protect
* certain critical sections to avoid kicking different SPM firmware
* concurrently.
*/
#define SPM_SYSCLK_SETTLE 128 /* 3.9ms */
DEFINE_BAKERY_LOCK(spm_lock);
static int spm_hotplug_ready __section("tzfw_coherent_mem");
static int spm_mcdi_ready __section("tzfw_coherent_mem");
static int spm_suspend_ready __section("tzfw_coherent_mem");
void spm_lock_init(void)
{
bakery_lock_init(&spm_lock);
}
void spm_lock_get(void)
{
bakery_lock_get(&spm_lock);
}
void spm_lock_release(void)
{
bakery_lock_release(&spm_lock);
}
int is_mcdi_ready(void)
{
return spm_mcdi_ready;
}
int is_hotplug_ready(void)
{
return spm_hotplug_ready;
}
int is_suspend_ready(void)
{
return spm_suspend_ready;
}
void set_mcdi_ready(void)
{
spm_mcdi_ready = 1;
spm_hotplug_ready = 0;
spm_suspend_ready = 0;
}
void set_hotplug_ready(void)
{
spm_mcdi_ready = 0;
spm_hotplug_ready = 1;
spm_suspend_ready = 0;
}
void set_suspend_ready(void)
{
spm_mcdi_ready = 0;
spm_hotplug_ready = 0;
spm_suspend_ready = 1;
}
void clear_all_ready(void)
{
spm_mcdi_ready = 0;
spm_hotplug_ready = 0;
spm_suspend_ready = 0;
}
void spm_register_init(void)
{
mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN);
mmio_write_32(SPM_POWER_ON_VAL0, 0);
mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET);
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY);
if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF)
WARN("PCM reset failed\n");
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS);
mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN |
CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN);
mmio_write_32(SPM_PCM_IM_PTR, 0);
mmio_write_32(SPM_PCM_IM_LEN, 0);
mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 |
CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL |
CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c);
mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff);
mmio_write_32(SPM_MD32_SRAM_CON, 0xff0);
}
void spm_reset_and_init_pcm(void)
{
unsigned int con1;
int i = 0;
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET);
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY);
while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) {
i++;
if (i > 1000) {
i = 0;
WARN("PCM reset failed\n");
break;
}
}
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS);
con1 = mmio_read_32(SPM_PCM_CON1) &
(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN |
CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B |
CON1_IM_NONRP_EN | CON1_MIF_APBEN);
}
void spm_init_pcm_register(void)
{
mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0));
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1));
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
}
void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) |
(!pwrctrl->mfg_req_mask << 17) |
(!pwrctrl->disp_req_mask << 16) |
(!!pwrctrl->mcusys_idle_mask << 7) |
(!!pwrctrl->ca15top_idle_mask << 6) |
(!!pwrctrl->ca7top_idle_mask << 5) |
(!!pwrctrl->wfi_op << 4));
mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0));
mmio_write_32(SPM_PCM_PASR_DPD_2, 0);
mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0,
(pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0));
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en);
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en);
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en);
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en);
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en);
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en);
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en);
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en);
}
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
unsigned int val, mask;
if (pwrctrl->timer_val_cust == 0)
val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
else
val = pwrctrl->timer_val_cust;
mmio_write_32(SPM_PCM_TIMER_VAL, val);
mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY);
if (pwrctrl->wake_src_cust == 0)
mask = pwrctrl->wake_src;
else
mask = pwrctrl->wake_src_cust;
if (pwrctrl->syspwreq_mask)
mask &= ~WAKE_SRC_SYSPWREQ;
mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04);
}
void spm_get_wakeup_status(struct wake_status *wakesta)
{
wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI);
wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA);
wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA);
wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC);
wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT);
wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA);
wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA);
wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3);
wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA);
wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS);
}
void spm_init_event_vector(const struct pcm_desc *pcmdesc)
{
/* init event vector register */
mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0);
mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1);
mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2);
mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3);
mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4);
mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5);
mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6);
mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7);
/* event vector will be enabled by PCM itself */
}
void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc)
{
unsigned int ptr = 0, len, con0;
ptr = (unsigned int)(unsigned long)(pcmdesc->base);
len = pcmdesc->size - 1;
if (mmio_read_32(SPM_PCM_IM_PTR) != ptr ||
mmio_read_32(SPM_PCM_IM_LEN) != len ||
pcmdesc->sess > 2) {
mmio_write_32(SPM_PCM_IM_PTR, ptr);
mmio_write_32(SPM_PCM_IM_LEN, len);
} else {
mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE);
}
/* kick IM to fetch (only toggle IM_KICK) */
con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY);
/* kick IM to fetch (only toggle PCM_KICK) */
con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY);
}
void spm_set_sysclk_settle(void)
{
mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE));
}
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
{
unsigned int con1;
con1 = mmio_read_32(SPM_PCM_CON1) &
~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1);
if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX)
mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX);
mmio_write_32(SPM_PCM_WDT_TIMER_VAL,
mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_PASR_DPD_0, 0);
mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff);
mmio_write_32(SPM_PCM_REG_DATA_INI, 0);
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags);
mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM,
(pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0));
mmio_write_32(SPM_PCM_PWR_IO_EN,
(pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) |
(pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0));
}
void spm_clean_after_wakeup(void)
{
mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0);
mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY);
mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C);
mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF);
}
enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta)
{
enum wake_reason_t wr;
int i;
wr = WR_UNKNOWN;
if (wakesta->assert_pc != 0) {
ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n",
wakesta->assert_pc, wakesta->r12, wakesta->r13,
wakesta->debug_flag);
return WR_PCM_ASSERT;
}
if (wakesta->r12 & WAKE_SRC_SPM_MERGE) {
if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER)
wr = WR_PCM_TIMER;
if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE)
wr = WR_WAKE_SRC;
}
for (i = 1; i < 32; i++) {
if (wakesta->r12 & (1U << i))
wr = WR_WAKE_SRC;
}
if ((wakesta->event_reg & 0x100000) == 0) {
INFO("pcm sleep abort!\n");
wr = WR_PCM_ABORT;
}
INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n",
wakesta->timer_out, wakesta->r12, wakesta->r13,
wakesta->debug_flag);
INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n",
wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg,
wakesta->isr);
return wr;
}
void spm_boot_init(void)
{
/* set spm transaction to secure mode */
mmio_write_32(DEVAPC0_APC_CON, 0x0);
mmio_write_32(DEVAPC0_MAS_SEC_0, 0x200);
/* Only CPU0 is online during boot, initialize cpu online reserve bit */
mmio_write_32(SPM_PCM_RESERVE, 0xFE);
mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF);
mmio_clrbits_32(AP_PLL_CON4, 0xF);
spm_lock_init();
spm_register_init();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm.h
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_H
#define SPM_H
#define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
#define SPM_CLK_SETTLE (SPM_BASE + 0x100)
#define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
#define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
#define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
#define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
#define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
#define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
#define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8)
#define SPM_PCM_CON0 (SPM_BASE + 0x310)
#define SPM_PCM_CON1 (SPM_BASE + 0x314)
#define SPM_PCM_IM_PTR (SPM_BASE + 0x318)
#define SPM_PCM_IM_LEN (SPM_BASE + 0x31c)
#define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320)
#define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340)
#define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344)
#define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348)
#define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c)
#define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354)
#define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358)
#define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c)
#define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360)
#define SPM_PCM_REG0_DATA (SPM_BASE + 0x380)
#define SPM_PCM_REG1_DATA (SPM_BASE + 0x384)
#define SPM_PCM_REG2_DATA (SPM_BASE + 0x388)
#define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c)
#define SPM_PCM_REG4_DATA (SPM_BASE + 0x390)
#define SPM_PCM_REG5_DATA (SPM_BASE + 0x394)
#define SPM_PCM_REG6_DATA (SPM_BASE + 0x398)
#define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c)
#define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0)
#define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4)
#define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8)
#define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac)
#define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0)
#define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4)
#define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8)
#define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc)
#define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0)
#define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4)
#define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8)
#define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc)
#define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0)
#define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4)
#define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8)
#define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc)
#define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0)
#define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4)
#define SPM_CLK_CON (SPM_BASE + 0x400)
#define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408)
#define SPM_APMCU_PWRCTL (SPM_BASE + 0x600)
#define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604)
#define SPM_AP_STANBY_CON (SPM_BASE + 0x608)
#define SPM_PWR_STATUS (SPM_BASE + 0x60c)
#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610)
#define SPM_AP_BSI_REQ (SPM_BASE + 0x614)
#define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720)
#define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810)
#define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814)
#define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818)
#define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824)
#define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828)
#define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830)
#define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834)
#define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900)
#define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904)
#define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910)
#define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914)
#define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918)
#define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c)
#define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920)
#define SPM_PCM_RESERVE (SPM_BASE + 0xb00)
#define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04)
#define SPM_PCM_FLAGS (SPM_BASE + 0xb08)
#define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c)
#define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20)
#define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30)
#define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34)
#define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38)
#define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c)
#define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40)
#define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44)
#define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48)
#define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c)
#define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60)
#define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64)
#define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68)
#define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c)
#define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00)
#define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04)
#define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08)
#define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c)
#define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10)
#define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14)
#define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18)
#define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c)
#define AP_PLL_CON3 0x1020900c
#define AP_PLL_CON4 0x10209010
#define SPM_PROJECT_CODE 0xb16
#define SPM_REGWR_EN (1U << 0)
#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
#define SPM_CPU_PDN_DIS (1U << 0)
#define SPM_INFRA_PDN_DIS (1U << 1)
#define SPM_DDRPHY_PDN_DIS (1U << 2)
#define SPM_DUALVCORE_PDN_DIS (1U << 3)
#define SPM_PASR_DIS (1U << 4)
#define SPM_DPD_DIS (1U << 5)
#define SPM_SODI_DIS (1U << 6)
#define SPM_MEMPLL_RESET (1U << 7)
#define SPM_MAINPLL_PDN_DIS (1U << 8)
#define SPM_CPU_DVS_DIS (1U << 9)
#define SPM_CPU_DORMANT (1U << 10)
#define SPM_EXT_VSEL_GPIO103 (1U << 11)
#define SPM_DDR_HIGH_SPEED (1U << 12)
#define SPM_OPT (1U << 13)
#define POWER_ON_VAL1_DEF 0x01011820
#define PCM_FSM_STA_DEF 0x48490
#define PCM_END_FSM_STA_DEF 0x08490
#define PCM_END_FSM_STA_MASK 0x3fff0
#define PCM_HANDSHAKE_SEND1 0xbeefbeef
#define PCM_WDT_TIMEOUT (30 * 32768)
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
#define CON0_PCM_KICK (1U << 0)
#define CON0_IM_KICK (1U << 1)
#define CON0_IM_SLEEP_DVS (1U << 3)
#define CON0_PCM_SW_RESET (1U << 15)
#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16)
#define CON1_IM_SLAVE (1U << 0)
#define CON1_MIF_APBEN (1U << 3)
#define CON1_PCM_TIMER_EN (1U << 5)
#define CON1_IM_NONRP_EN (1U << 6)
#define CON1_PCM_WDT_EN (1U << 8)
#define CON1_PCM_WDT_WAKE_MODE (1U << 9)
#define CON1_SPM_SRAM_SLP_B (1U << 10)
#define CON1_SPM_SRAM_ISO_B (1U << 11)
#define CON1_EVENT_LOCK_EN (1U << 12)
#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16)
#define PCM_PWRIO_EN_R0 (1U << 0)
#define PCM_PWRIO_EN_R7 (1U << 7)
#define PCM_RF_SYNC_R0 (1U << 16)
#define PCM_RF_SYNC_R2 (1U << 18)
#define PCM_RF_SYNC_R6 (1U << 22)
#define PCM_RF_SYNC_R7 (1U << 23)
#define CC_SYSCLK0_EN_0 (1U << 0)
#define CC_SYSCLK0_EN_1 (1U << 1)
#define CC_SYSCLK1_EN_0 (1U << 2)
#define CC_SYSCLK1_EN_1 (1U << 3)
#define CC_SYSSETTLE_SEL (1U << 4)
#define CC_LOCK_INFRA_DCM (1U << 5)
#define CC_SRCLKENA_MASK_0 (1U << 6)
#define CC_CXO32K_RM_EN_MD1 (1U << 9)
#define CC_CXO32K_RM_EN_MD2 (1U << 10)
#define CC_CLKSQ1_SEL (1U << 12)
#define CC_DISABLE_DORM_PWR (1U << 14)
#define CC_MD32_DCM_EN (1U << 18)
#define WFI_OP_AND 1
#define WFI_OP_OR 0
#define WAKE_MISC_PCM_TIMER (1U << 19)
#define WAKE_MISC_CPU_WAKE (1U << 20)
/* define WAKE_SRC_XXX */
#define WAKE_SRC_SPM_MERGE (1 << 0)
#define WAKE_SRC_KP (1 << 2)
#define WAKE_SRC_WDT (1 << 3)
#define WAKE_SRC_GPT (1 << 4)
#define WAKE_SRC_EINT (1 << 6)
#define WAKE_SRC_LOW_BAT (1 << 9)
#define WAKE_SRC_MD32 (1 << 10)
#define WAKE_SRC_USB_CD (1 << 14)
#define WAKE_SRC_USB_PDN (1 << 15)
#define WAKE_SRC_AFE (1 << 20)
#define WAKE_SRC_THERM (1 << 21)
#define WAKE_SRC_CIRQ (1 << 22)
#define WAKE_SRC_SYSPWREQ (1 << 24)
#define WAKE_SRC_SEJ (1 << 27)
#define WAKE_SRC_ALL_MD32 (1 << 28)
#define WAKE_SRC_CPU_IRQ (1 << 29)
enum wake_reason_t {
WR_NONE = 0,
WR_UART_BUSY = 1,
WR_PCM_ASSERT = 2,
WR_PCM_TIMER = 3,
WR_PCM_ABORT = 4,
WR_WAKE_SRC = 5,
WR_UNKNOWN = 6,
};
struct pwr_ctrl {
unsigned int pcm_flags;
unsigned int pcm_flags_cust;
unsigned int pcm_reserve;
unsigned int timer_val;
unsigned int timer_val_cust;
unsigned int wake_src;
unsigned int wake_src_cust;
unsigned int wake_src_md32;
unsigned short r0_ctrl_en;
unsigned short r7_ctrl_en;
unsigned short infra_dcm_lock;
unsigned short pcm_apsrc_req;
unsigned short mcusys_idle_mask;
unsigned short ca15top_idle_mask;
unsigned short ca7top_idle_mask;
unsigned short wfi_op;
unsigned short ca15_wfi0_en;
unsigned short ca15_wfi1_en;
unsigned short ca15_wfi2_en;
unsigned short ca15_wfi3_en;
unsigned short ca7_wfi0_en;
unsigned short ca7_wfi1_en;
unsigned short ca7_wfi2_en;
unsigned short ca7_wfi3_en;
unsigned short disp_req_mask;
unsigned short mfg_req_mask;
unsigned short md32_req_mask;
unsigned short syspwreq_mask;
unsigned short srclkenai_mask;
};
struct wake_status {
unsigned int assert_pc;
unsigned int r12;
unsigned int raw_sta;
unsigned int wake_misc;
unsigned int timer_out;
unsigned int r13;
unsigned int idle_sta;
unsigned int debug_flag;
unsigned int event_reg;
unsigned int isr;
};
struct pcm_desc {
const char *version; /* PCM code version */
const unsigned int *base; /* binary array base */
const unsigned int size; /* binary array size */
const unsigned char sess; /* session number */
const unsigned char replace; /* replace mode */
unsigned int vec0; /* event vector 0 config */
unsigned int vec1; /* event vector 1 config */
unsigned int vec2; /* event vector 2 config */
unsigned int vec3; /* event vector 3 config */
unsigned int vec4; /* event vector 4 config */
unsigned int vec5; /* event vector 5 config */
unsigned int vec6; /* event vector 6 config */
unsigned int vec7; /* event vector 7 config */
};
struct spm_lp_scen {
const struct pcm_desc *pcmdesc;
struct pwr_ctrl *pwrctrl;
};
#define EVENT_VEC(event, resume, imme, pc) \
(((pc) << 16) | \
(!!(imme) << 6) | \
(!!(resume) << 5) | \
((event) & 0x1f))
#define spm_read(addr) mmio_read_32(addr)
#define spm_write(addr, val) mmio_write_32(addr, val)
#define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS))
#define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS))
#define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS))
static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
unsigned int flags)
{
flags &= ~SPM_EXT_VSEL_GPIO103;
if (pwrctrl->pcm_flags_cust == 0)
pwrctrl->pcm_flags = flags;
else
pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
}
static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl,
unsigned int data)
{
pwrctrl->pcm_reserve = data;
}
void spm_reset_and_init_pcm(void);
void spm_init_pcm_register(void); /* init r0 and r7 */
void spm_set_power_control(const struct pwr_ctrl *pwrctrl);
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
void spm_get_wakeup_status(struct wake_status *wakesta);
void spm_set_sysclk_settle(void);
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
void spm_clean_after_wakeup(void);
enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta);
void spm_register_init(void);
void spm_go_to_hotplug(void);
void spm_init_event_vector(const struct pcm_desc *pcmdesc);
void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
int is_mcdi_ready(void);
int is_hotplug_ready(void);
int is_suspend_ready(void);
void set_mcdi_ready(void);
void set_hotplug_ready(void);
void set_suspend_ready(void);
void clear_all_ready(void);
void spm_lock_init(void);
void spm_lock_get(void);
void spm_lock_release(void);
void spm_boot_init(void);
#endif /* SPM_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
+275
View File
@@ -0,0 +1,275 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <lib/mmio.h>
#include <mt8173_def.h>
#include <plat/common/platform.h>
#include <spm.h>
#include <spm_hotplug.h>
#include <spm_mcdi.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware.
* This driver controls the cpu power in cpu hotplug flow.
*/
#define PCM_HOTPLUG_VALID_MASK 0x0000ff00
#define PCM_HOTPLUG_VALID_SHIFT 0x8
/**********************************************************
* PCM sequence for CPU hotplug
**********************************************************/
static const unsigned int hotplug_binary[] = {
0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c, 0xa9400005, 0x00000001,
0xe1000005, 0x1910001f, 0x10006720, 0x814c9001, 0xd82000e5, 0x17c07c1f,
0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0xa15f0405, 0xe1000005,
0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401, 0xd8200244,
0x17c07c1f, 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f,
0x100062b8, 0xa9000004, 0x00000001, 0xe2000004, 0x1910001f, 0x100062b8,
0x81142804, 0xd8200444, 0x17c07c1f, 0xe2e0002c, 0xe2e0003c, 0xe2e0003e,
0xe2e0003a, 0xe2e00032, 0x1910001f, 0x1000660c, 0x81079001, 0x1950001f,
0x10006610, 0x81479401, 0xa1001404, 0xd8000584, 0x17c07c1f, 0x1900001f,
0x10006404, 0x1950001f, 0x10006404, 0xa1568405, 0xe1000005, 0xf0000000,
0x17c07c1f, 0x1900001f, 0x10006404, 0x1950001f, 0x10006404, 0x89400005,
0x0000dfff, 0xe1000005, 0xe2e00036, 0xe2e0003e, 0x1910001f, 0x1000660c,
0x81079001, 0x1950001f, 0x10006610, 0x81479401, 0x81001404, 0xd82008c4,
0x17c07c1f, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8,
0x89000004, 0x0000fffe, 0xe2000004, 0x1910001f, 0x100062b8, 0x81142804,
0xd8000ae4, 0x17c07c1f, 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d,
0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0x89400005, 0xbfffffff,
0xe1000005, 0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401,
0xd8000ce4, 0x17c07c1f, 0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c,
0x89400005, 0xfffffffe, 0xe1000005, 0xf0000000, 0x17c07c1f, 0x1212841f,
0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000, 0x1b80001f,
0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c,
0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f,
0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e00032,
0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e, 0x1380201f,
0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804, 0xe2000004,
0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f, 0x100062b4,
0x81142804, 0xd8001404, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c, 0xe2e0000d,
0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4, 0x1910001f,
0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004, 0x1b80001f,
0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82016a4, 0x17c07c1f,
0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022, 0xf0000000,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x1840001f, 0x00000001,
0x1840001f, 0x00000001, 0xa1d48407, 0x1b00001f, 0x2f7be75f, 0xe8208000,
0x10006354, 0xfffe7b47, 0xa1d10407, 0x1b80001f, 0x20000020, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x81461001, 0xb14690a1, 0xd82044e5, 0x17c07c1f,
0x1910001f, 0x10006610, 0x81079001, 0xd80044e4, 0x17c07c1f, 0x1990001f,
0x10006b00, 0x81421801, 0x82429801, 0x81402405, 0xd80044e5, 0x17c07c1f,
0x1a40001f, 0x100062b0, 0x1280041f, 0xc24007a0, 0x17c07c1f, 0x1910001f,
0x10006b00, 0x81449001, 0xd8204be5, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x81009001, 0xd8204984, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001,
0xd8204be4, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81489001, 0xd82046c5,
0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24010e0,
0x17c07c1f, 0x1910001f, 0x1000660c, 0x81051001, 0x1950001f, 0x10006610,
0x81451401, 0xa1001404, 0xd8004824, 0x17c07c1f, 0xd0004b00, 0x17c07c1f,
0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001, 0xd8004be4, 0x17c07c1f,
0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400ee0, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x89000004, 0xfffffdff, 0x1940001f, 0x10006b00,
0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81451001, 0xd8205305,
0x17c07c1f, 0x1910001f, 0x10006b00, 0x81011001, 0xd82050a4, 0x17c07c1f,
0x1910001f, 0x10006610, 0x81059001, 0xd8205304, 0x17c07c1f, 0x1910001f,
0x10006720, 0x81491001, 0xd8204de5, 0x17c07c1f, 0x1a40001f, 0x1000621c,
0x1a80001f, 0x1000626c, 0xc24010e0, 0x17c07c1f, 0x1910001f, 0x1000660c,
0x81059001, 0x1950001f, 0x10006610, 0x81459401, 0xa1001404, 0xd8004f44,
0x17c07c1f, 0xd0005220, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610,
0x81059001, 0xd8005304, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f,
0x1000626c, 0xc2400ee0, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x89000004,
0xfffffbff, 0x1940001f, 0x10006b00, 0xe1400004, 0x17c07c1f, 0x1910001f,
0x10006b00, 0x81459001, 0xd8205a25, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x81019001, 0xd82057c4, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001,
0xd8205a24, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81499001, 0xd8205505,
0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc24010e0,
0x17c07c1f, 0x1910001f, 0x1000660c, 0x81061001, 0x1950001f, 0x10006610,
0x81461401, 0xa1001404, 0xd8005664, 0x17c07c1f, 0xd0005940, 0x17c07c1f,
0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001, 0xd8005a24, 0x17c07c1f,
0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc2400ee0, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x89000004, 0xfffff7ff, 0x1940001f, 0x10006b00,
0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81461001, 0xd8206185,
0x17c07c1f, 0x1910001f, 0x10006b00, 0x81021001, 0xd8205ec4, 0x17c07c1f,
0x1910001f, 0x10006610, 0x81081001, 0xd8206184, 0x17c07c1f, 0x1910001f,
0x10006720, 0x814a1001, 0xd8205c25, 0x17c07c1f, 0x1a40001f, 0x100062a0,
0x1280041f, 0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81081001,
0x1950001f, 0x10006610, 0x81481401, 0xa1001404, 0xd8005d64, 0x17c07c1f,
0xd00060a0, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001,
0x81881001, 0x69a00006, 0x00000000, 0x81401805, 0xd8206185, 0x17c07c1f,
0x1a40001f, 0x100062a0, 0x1280041f, 0xc2401240, 0x17c07c1f, 0x1910001f,
0x10006b00, 0x89000004, 0xffffefff, 0x1940001f, 0x10006b00, 0xe1400004,
0x17c07c1f, 0x1910001f, 0x10006b00, 0x81469001, 0xd82068e5, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x81029001, 0xd8206624, 0x17c07c1f, 0x1910001f,
0x10006610, 0x81089001, 0xd82068e4, 0x17c07c1f, 0x1910001f, 0x10006720,
0x814a9001, 0xd8206385, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f,
0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81089001, 0x1950001f,
0x10006610, 0x81489401, 0xa1001404, 0xd80064c4, 0x17c07c1f, 0xd0006800,
0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001, 0x81889001,
0x69a00006, 0x00000000, 0x81401805, 0xd82068e5, 0x17c07c1f, 0x1a40001f,
0x100062a4, 0x1290841f, 0xc2401240, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x89000004, 0xffffdfff, 0x1940001f, 0x10006b00, 0xe1400004, 0x1910001f,
0x10006610, 0x81479001, 0x81881001, 0x69600005, 0x00000000, 0xa1401805,
0x81889001, 0xa1401805, 0xd8006bc5, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x81421001, 0x82429001, 0x82802405, 0xd8206bca, 0x17c07c1f, 0x1a40001f,
0x100062b0, 0x1280041f, 0xc2400000, 0x17c07c1f, 0x1990001f, 0x10006b00,
0x89800006, 0x00003f00, 0x69200006, 0x00000000, 0xd82041e4, 0x17c07c1f,
0x1990001f, 0x10006320, 0x69200006, 0xbeefbeef, 0xd8006dc4, 0x17c07c1f,
0xd00041e0, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8006dc4,
0x17c07c1f, 0x1980001f, 0xdeaddead, 0x19c0001f, 0x01411820, 0xf0000000
};
static const struct pcm_desc hotplug_pcm = {
.version = "pcm_power_down_mt8173_V37",
.base = hotplug_binary,
.size = 888,
.sess = 2,
.replace = 0,
};
static struct pwr_ctrl hotplug_ctrl = {
.wake_src = 0,
.wake_src_md32 = 0,
.wfi_op = WFI_OP_OR,
.mcusys_idle_mask = 1,
.ca7top_idle_mask = 1,
.ca15top_idle_mask = 1,
.disp_req_mask = 1,
.mfg_req_mask = 1,
.md32_req_mask = 1,
.syspwreq_mask = 1,
.pcm_flags = 0,
};
static const struct spm_lp_scen spm_hotplug = {
.pcmdesc = &hotplug_pcm,
.pwrctrl = &hotplug_ctrl,
};
void spm_go_to_hotplug(void)
{
const struct pcm_desc *pcmdesc = spm_hotplug.pcmdesc;
struct pwr_ctrl *pwrctrl = spm_hotplug.pwrctrl;
set_pwrctrl_pcm_flags(pwrctrl, 0);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcmdesc);
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
}
void spm_clear_hotplug(void)
{
/* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and
* DISABLE_CPU_DROM */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_HANDSHAKE_SEND1);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
/* Wait SPM's response, can't use sleep api */
while ((mmio_read_32(SPM_PCM_FSM_STA) & PCM_END_FSM_STA_MASK)
!= PCM_END_FSM_STA_DEF)
;
/* no hotplug pcm running */
clear_all_ready();
}
void spm_hotplug_on(unsigned long mpidr)
{
unsigned long linear_id;
linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) |
(mpidr & MPIDR_CPU_MASK);
spm_lock_get();
if (is_hotplug_ready() == 0) {
spm_mcdi_wakeup_all_cores();
mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
spm_go_to_hotplug();
set_hotplug_ready();
}
/* turn on CPUx */
mmio_clrsetbits_32(SPM_PCM_RESERVE,
PCM_HOTPLUG_VALID_MASK | (1 << linear_id),
1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT));
spm_lock_release();
}
void spm_hotplug_off(unsigned long mpidr)
{
unsigned long linear_id;
linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) |
(mpidr & MPIDR_CPU_MASK);
spm_lock_get();
if (is_hotplug_ready() == 0) {
spm_mcdi_wakeup_all_cores();
mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
spm_go_to_hotplug();
set_hotplug_ready();
}
mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK,
(1 << linear_id) |
(1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT)));
spm_lock_release();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h
+13
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@@ -0,0 +1,13 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_HOTPLUG_H
#define SPM_HOTPLUG_H
void spm_clear_hotplug(void);
void spm_hotplug_off(unsigned long mpidr);
void spm_hotplug_on(unsigned long mpidr);
#endif /* SPM_HOTPLUG_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
+503
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@@ -0,0 +1,503 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <arch.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
#include <mt8173_def.h>
#include <spm.h>
#include <spm_hotplug.h>
#include <spm_mcdi.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware.
* This driver controls the cpu power in cpu idle power saving state.
*/
#define WAKE_SRC_FOR_MCDI \
(WAKE_SRC_KP | WAKE_SRC_GPT | WAKE_SRC_EINT | \
WAKE_SRC_MD32 | WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | \
WAKE_SRC_AFE | WAKE_SRC_THERM | WAKE_SRC_CIRQ | \
WAKE_SRC_SYSPWREQ | WAKE_SRC_CPU_IRQ)
#define PCM_MCDI_HANDSHAKE_SYNC 0xbeefbeef
#define PCM_MCDI_HANDSHAKE_ACK 0xdeaddead
#define PCM_MCDI_UPDATE_INFORM 0xabcdabcd
#define PCM_MCDI_CKECK_DONE 0x12345678
#define PCM_MCDI_ALL_CORE_AWAKE 0x0
#define PCM_MCDI_OFFLOADED 0xaa55aa55
#define PCM_MCDI_CA72_CPUTOP_PWRCTL (0x1 << 16)
#define PCM_MCDI_CA53_CPUTOP_PWRCTL (0x1 << 17)
#define PCM_MCDI_CA72_PWRSTA_SHIFT 16
#define PCM_MCDI_CA53_PWRSTA_SHIFT 9
static const unsigned int mcdi_binary[] = {
0x1a10001f, 0x10006b04, 0x1890001f, 0x10006b6c, 0x1a40001f, 0x10006210,
0x18d0001f, 0x10006210, 0x81002001, 0xd82001c4, 0x17c07c1f, 0xa0900402,
0xc2401540, 0x17c07c1f, 0x81052001, 0xd8200284, 0x17c07c1f, 0xa0950402,
0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x10006230, 0x18d0001f, 0x10006230,
0x8100a001, 0xd82003c4, 0x17c07c1f, 0xa0908402, 0xc2401540, 0x17c07c1f,
0x8105a001, 0xd8200484, 0x17c07c1f, 0xa0958402, 0xc2401b80, 0x17c07c1f,
0x1a40001f, 0x10006238, 0x18d0001f, 0x10006238, 0x81012001, 0xd82005c4,
0x17c07c1f, 0xa0910402, 0xc2401540, 0x17c07c1f, 0x81062001, 0xd8200684,
0x17c07c1f, 0xa0960402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x1000623c,
0x18d0001f, 0x1000623c, 0x8101a001, 0xd82007c4, 0x17c07c1f, 0xa0918402,
0xc2401540, 0x17c07c1f, 0x8106a001, 0xd8200884, 0x17c07c1f, 0xa0968402,
0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x10006298, 0x18d0001f, 0x10006298,
0x81022001, 0xd82009c4, 0x17c07c1f, 0xa0920402, 0xc2401540, 0x17c07c1f,
0x81072001, 0xd8200a84, 0x17c07c1f, 0xa0970402, 0xc2401b80, 0x17c07c1f,
0x1a40001f, 0x1000629c, 0x18d0001f, 0x1000629c, 0x8102a001, 0xd8200bc4,
0x17c07c1f, 0xa0928402, 0xc2401540, 0x17c07c1f, 0x8107a001, 0xd8200c84,
0x17c07c1f, 0xa0978402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062c4,
0x18d0001f, 0x100062c4, 0x81032001, 0xd8200dc4, 0x17c07c1f, 0xa0930402,
0xc2401540, 0x17c07c1f, 0x81082001, 0xd8200e84, 0x17c07c1f, 0xa0980402,
0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062c0, 0x18d0001f, 0x100062c0,
0x8103a001, 0xd8200fc4, 0x17c07c1f, 0xa0938402, 0xc2401540, 0x17c07c1f,
0x8108a001, 0xd8201084, 0x17c07c1f, 0xa0988402, 0xc2401b80, 0x17c07c1f,
0x1a40001f, 0x10006214, 0x18d0001f, 0x10006214, 0x81042001, 0xd82011c4,
0x17c07c1f, 0xa0940402, 0xc2401540, 0x17c07c1f, 0x81092001, 0xd8201284,
0x17c07c1f, 0xa0990402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062cc,
0x18d0001f, 0x100062cc, 0x8104a001, 0xd82013c4, 0x17c07c1f, 0xa0948402,
0xc2401540, 0x17c07c1f, 0x8109a001, 0xd8201484, 0x17c07c1f, 0xa0998402,
0xc2401b80, 0x17c07c1f, 0x1900001f, 0x10006b6c, 0x80802002, 0xe1000002,
0xf0000000, 0x17c07c1f, 0xa8c00003, 0x00000004, 0xe2400003, 0xa8c00003,
0x00000008, 0xe2400003, 0x1b80001f, 0x00000020, 0x88c00003, 0xffffffef,
0xe2400003, 0x88c00003, 0xfffffffd, 0xe2400003, 0xa8c00003, 0x00000001,
0xe2400003, 0x88c00003, 0xfffff0ff, 0xe2400003, 0x1b80001f, 0x20000080,
0x1a90001f, 0x10001220, 0x69200009, 0x1000623c, 0xd8001984, 0x17c07c1f,
0x69200009, 0x10006214, 0xd8001a64, 0x17c07c1f, 0xd0001b00, 0x17c07c1f,
0x1900001f, 0x10001220, 0x8a80000a, 0xfffffff9, 0xe100000a, 0xd0001b00,
0x17c07c1f, 0x1900001f, 0x10001220, 0x8a80000a, 0xff1fbfff, 0xe100000a,
0x1b80001f, 0x20000080, 0xf0000000, 0x17c07c1f, 0x1a90001f, 0x10001220,
0x69200009, 0x1000623c, 0xd8001d04, 0x17c07c1f, 0x69200009, 0x10006214,
0xd8001de4, 0x17c07c1f, 0xd0001e80, 0x17c07c1f, 0x1900001f, 0x10001220,
0xaa80000a, 0x00000006, 0xe100000a, 0xd0001e80, 0x17c07c1f, 0x1900001f,
0x10001220, 0xaa80000a, 0x00e04000, 0xe100000a, 0x1b80001f, 0x20000080,
0x69200009, 0x10006214, 0xd8001fe4, 0x17c07c1f, 0xa8c00003, 0x00000f00,
0xe2400003, 0xd0002040, 0x17c07c1f, 0xa8c00003, 0x00003f00, 0xe2400003,
0x1b80001f, 0x20000080, 0xa8c00003, 0x00000002, 0xe2400003, 0x88c00003,
0xfffffffe, 0xe2400003, 0xa8c00003, 0x00000010, 0xe2400003, 0x88c00003,
0xfffffffb, 0xe2400003, 0x88c00003, 0xfffffff7, 0xe2400003, 0xf0000000,
0x17c07c1f, 0xe2e00036, 0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c,
0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xe2e0007c,
0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d, 0xf0000000,
0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, 0xe8208000, 0x10006244,
0x00000001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e0003a,
0xe2e00032, 0x1b80001f, 0x00000020, 0xf0000000, 0x17c07c1f, 0xe2e00036,
0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c, 0xe2a00000, 0x1b80001f,
0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c,
0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f,
0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e0003a,
0xe2e00032, 0xf0000000, 0x17c07c1f, 0xe2e00026, 0xe2e0002e, 0x1b80001f,
0x00000020, 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804,
0xe2000004, 0x81202804, 0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0000e,
0xe2e0000c, 0xe2e0000d, 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f,
0x100062b4, 0x1910001f, 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804,
0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0002f, 0xe2e0002b, 0xe2e00023,
0x1b80001f, 0x00000020, 0xe2e00022, 0xf0000000, 0x17c07c1f, 0x1910001f,
0x1000660c, 0x1a10001f, 0x10006610, 0xa2002004, 0x89000008, 0x00030000,
0xd80036c4, 0x17c07c1f, 0x8207a001, 0xd82036c8, 0x17c07c1f, 0x1900001f,
0x1020020c, 0x1a10001f, 0x1020020c, 0xaa000008, 0x00000001, 0xe1000008,
0x1910001f, 0x1020020c, 0x81001001, 0xd8203184, 0x17c07c1f, 0x1910001f,
0x10006720, 0x820c9001, 0xd8203228, 0x17c07c1f, 0x1900001f, 0x10001220,
0x1a10001f, 0x10001220, 0xa21f0408, 0xe1000008, 0x1b80001f, 0x20000080,
0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8,
0xa9000004, 0x00000001, 0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0002c,
0xe2e0003c, 0xe2e0003e, 0xe2e0003a, 0xe2e00032, 0x1b80001f, 0x00000020,
0x1900001f, 0x10006404, 0x1a10001f, 0x10006404, 0xa2168408, 0xe1000008,
0xf0000000, 0x17c07c1f, 0x1a10001f, 0x10006610, 0x8207a001, 0xd8003e68,
0x17c07c1f, 0x1a10001f, 0x10006918, 0x8a000008, 0x00003030, 0xb900010c,
0x01000001, 0xd8203e64, 0x17c07c1f, 0x1900001f, 0x10006404, 0x1a10001f,
0x10006404, 0x8a000008, 0x0000dfff, 0xe1000008, 0xe2e00036, 0xe2e0003e,
0x1b80001f, 0x00000020, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f,
0x100062b8, 0x89000004, 0x0000fffe, 0xe2000004, 0x1b80001f, 0x20000080,
0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d, 0x1900001f, 0x10001220,
0x1a10001f, 0x10001220, 0x8a000008, 0xbfffffff, 0xe1000008, 0x1b80001f,
0x20000080, 0x1900001f, 0x1020020c, 0x1a10001f, 0x1020020c, 0x8a000008,
0xfffffffe, 0xe1000008, 0x1910001f, 0x1020020c, 0x81001001, 0xd8003dc4,
0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x11407c1f, 0xe8208000,
0x10006310, 0x0b160008, 0x1900001f, 0x000f7bde, 0x1a00001f, 0x10200268,
0xe2000004, 0xe8208000, 0x10006600, 0x00000000, 0x69200006, 0xbeefbeef,
0xd8204584, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8004244,
0x17c07c1f, 0x1980001f, 0xdeaddead, 0x69200006, 0xabcdabcd, 0xd8204324,
0x17c07c1f, 0x88900001, 0x10006814, 0x1910001f, 0x10006400, 0x81271002,
0x1880001f, 0x10006600, 0xe0800004, 0x1910001f, 0x10006358, 0x810b1001,
0xd80044a4, 0x17c07c1f, 0x1980001f, 0x12345678, 0x60a07c05, 0x89100002,
0x10006600, 0x80801001, 0xd8007bc2, 0x17c07c1f, 0x1890001f, 0x10006b00,
0x82090801, 0xc8800008, 0x17c07c1f, 0x1b00001f, 0x3fffe7ff, 0x8a00000c,
0x3fffe7ff, 0xd82041c8, 0x17c07c1f, 0x1b80001f, 0xd0010000, 0x1a10001f,
0x10006720, 0x82002001, 0x82201408, 0xd8204988, 0x17c07c1f, 0x1a40001f,
0x10006200, 0x1a80001f, 0x1000625c, 0xc24028e0, 0x17c07c1f, 0xa1400405,
0x1a10001f, 0x10006720, 0x8200a001, 0x82209408, 0xd8204b28, 0x17c07c1f,
0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24028e0, 0x17c07c1f,
0xa1508405, 0x1a10001f, 0x10006720, 0x82012001, 0x82211408, 0xd8204cc8,
0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24028e0,
0x17c07c1f, 0xa1510405, 0x1a10001f, 0x10006720, 0x8201a001, 0x82219408,
0xd8204e68, 0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274,
0xc24028e0, 0x17c07c1f, 0xa1518405, 0x1a10001f, 0x10006720, 0x82022001,
0x82221408, 0xd8204fe8, 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f,
0xc2402cc0, 0x17c07c1f, 0xa1520405, 0x1a10001f, 0x10006720, 0x8202a001,
0x82229408, 0xd8205168, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f,
0xc2402cc0, 0x17c07c1f, 0xa1528405, 0x1a10001f, 0x10006720, 0x82032001,
0x82231408, 0xd8205248, 0x17c07c1f, 0xa1530405, 0x1a10001f, 0x10006720,
0x8203a001, 0x82239408, 0xd8205328, 0x17c07c1f, 0xa1538405, 0x1a10001f,
0x10006b00, 0x8108a001, 0xd8205e84, 0x17c07c1f, 0x1910001f, 0x1000660c,
0x1a10001f, 0x10006610, 0xa2002004, 0x89000008, 0x00001e00, 0xd8005944,
0x17c07c1f, 0x82042001, 0xd8205948, 0x17c07c1f, 0x1900001f, 0x1020002c,
0x1a10001f, 0x1020002c, 0xaa000008, 0x00000010, 0xe1000008, 0x1910001f,
0x10006720, 0x820c1001, 0xd8205628, 0x17c07c1f, 0x1900001f, 0x10001250,
0x1a10001f, 0x10001250, 0xa2110408, 0xe1000008, 0x1b80001f, 0x20000080,
0x1900001f, 0x10001220, 0x1a10001f, 0x10001220, 0xa21e8408, 0xe1000008,
0x1b80001f, 0x20000080, 0x1a40001f, 0x10006208, 0xc24024e0, 0x17c07c1f,
0x1a10001f, 0x10006610, 0x82042001, 0xd8005e88, 0x17c07c1f, 0x1a10001f,
0x10006918, 0x8a000008, 0x00000f0f, 0xba00010c, 0x1fffe7ff, 0xd8205e88,
0x17c07c1f, 0x1a40001f, 0x10006208, 0xc24022a0, 0x17c07c1f, 0x1900001f,
0x10001250, 0x1a10001f, 0x10001250, 0x8a000008, 0xfffffffb, 0xe1000008,
0x1b80001f, 0x20000080, 0x1900001f, 0x10001220, 0x1a10001f, 0x10001220,
0x8a000008, 0xdfffffff, 0xe1000008, 0x1b80001f, 0x20000080, 0x1900001f,
0x1020002c, 0x1a10001f, 0x1020002c, 0x8a000008, 0xffffffef, 0xe1000008,
0x1a10001f, 0x10006b00, 0x81082001, 0xd8205fa4, 0x17c07c1f, 0x1a40001f,
0x100062b0, 0xc2402f20, 0x17c07c1f, 0x1b80001f, 0x20000208, 0xd8207b8c,
0x17c07c1f, 0x1a40001f, 0x100062b0, 0xc2403700, 0x17c07c1f, 0x81001401,
0xd8206424, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x81002001, 0xb1042081,
0xb900008c, 0x1fffe7ff, 0xd8206424, 0x17c07c1f, 0x1a40001f, 0x10006200,
0x1a80001f, 0x1000625c, 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffffe,
0xe8208000, 0x10006f00, 0x00000000, 0xe8208000, 0x10006b30, 0x00000000,
0xe8208000, 0x100063e0, 0x00000001, 0x81009401, 0xd82067a4, 0x17c07c1f,
0x1a10001f, 0x10006918, 0x8100a001, 0xb104a081, 0xb900008c, 0x01000001,
0xd82067a4, 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264,
0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffffd, 0xe8208000, 0x10006f04,
0x00000000, 0xe8208000, 0x10006b34, 0x00000000, 0xe8208000, 0x100063e0,
0x00000002, 0x81011401, 0xd8206b24, 0x17c07c1f, 0x1a10001f, 0x10006918,
0x81012001, 0xb1052081, 0xb900008c, 0x01000001, 0xd8206b24, 0x17c07c1f,
0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24026e0, 0x17c07c1f,
0x89400005, 0xfffffffb, 0xe8208000, 0x10006f08, 0x00000000, 0xe8208000,
0x10006b38, 0x00000000, 0xe8208000, 0x100063e0, 0x00000004, 0x81019401,
0xd8206ea4, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8101a001, 0xb105a081,
0xb900008c, 0x01000001, 0xd8206ea4, 0x17c07c1f, 0x1a40001f, 0x10006220,
0x1a80001f, 0x10006274, 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffff7,
0xe8208000, 0x10006f0c, 0x00000000, 0xe8208000, 0x10006b3c, 0x00000000,
0xe8208000, 0x100063e0, 0x00000008, 0x1a10001f, 0x10006610, 0x8207a001,
0xd8207608, 0x17c07c1f, 0x81021401, 0xd82072a4, 0x17c07c1f, 0x1a10001f,
0x10006918, 0x81022001, 0xb1062081, 0xb900008c, 0x01000001, 0xd82072a4,
0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2402a60, 0x17c07c1f,
0x89400005, 0xffffffef, 0xe8208000, 0x10006f10, 0x00000000, 0xe8208000,
0x10006b40, 0x00000000, 0xe8208000, 0x100063e0, 0x00000010, 0x81029401,
0xd8207604, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001, 0xb106a081,
0xb900008c, 0x01000001, 0xd8207604, 0x17c07c1f, 0x1a40001f, 0x100062a4,
0x1290841f, 0xc2402a60, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000,
0x10006f14, 0x00000000, 0xe8208000, 0x10006b44, 0x00000000, 0xe8208000,
0x100063e0, 0x00000020, 0x81031401, 0xd82078c4, 0x17c07c1f, 0x1a10001f,
0x10006918, 0x81032001, 0xb1072081, 0xb900008c, 0x01000001, 0xd82078c4,
0x17c07c1f, 0x89400005, 0xffffffbf, 0xe8208000, 0x10006f18, 0x00000000,
0xe8208000, 0x10006b48, 0x00000000, 0xe8208000, 0x100063e0, 0x00000040,
0x81039401, 0xd8207b84, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001,
0xb107a081, 0xb900008c, 0x01000001, 0xd8207b84, 0x17c07c1f, 0x89400005,
0xffffff7f, 0xe8208000, 0x10006f1c, 0x00000000, 0xe8208000, 0x10006b4c,
0x00000000, 0xe8208000, 0x100063e0, 0x00000080, 0xd00041c0, 0x17c07c1f,
0xe8208000, 0x10006600, 0x00000000, 0x1ac0001f, 0x55aa55aa, 0x1940001f,
0xaa55aa55, 0x1b80001f, 0x00001000, 0xf0000000, 0x17c07c1f
};
static const struct pcm_desc mcdi_pcm = {
.version = "pcm_mcdi_mt8173_20160401_v1",
.base = mcdi_binary,
.size = 1001,
.sess = 2,
.replace = 0,
};
static struct pwr_ctrl mcdi_ctrl = {
.wake_src = WAKE_SRC_FOR_MCDI,
.wake_src_md32 = 0,
.wfi_op = WFI_OP_OR,
.mcusys_idle_mask = 1,
.ca7top_idle_mask = 1,
.ca15top_idle_mask = 1,
.disp_req_mask = 1,
.mfg_req_mask = 1,
.md32_req_mask = 1,
};
static const struct spm_lp_scen spm_mcdi = {
.pcmdesc = &mcdi_pcm,
.pwrctrl = &mcdi_ctrl,
};
void spm_mcdi_cpu_wake_up_event(int wake_up_event, int disable_dormant_power)
{
if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1)
&& ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) {
/* MCDI is offload? */
INFO("%s: SPM_SLEEP_CPU_WAKEUP_EVENT:%x, SPM_CLK_CON %x",
__func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT),
mmio_read_32(SPM_CLK_CON));
return;
}
/* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and
* DISABLE_CPU_DROM */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
/* Wait SPM's response, can't use sleep api */
while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK)
;
if (disable_dormant_power) {
mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
while (mmio_read_32(SPM_CLK_CON) !=
(mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR))
;
} else {
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
while (mmio_read_32(SPM_CLK_CON) !=
(mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR))
;
}
mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event);
while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event)
;
/* Inform SPM to see updated setting */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_CKECK_DONE)
;
/* END OF sequence */
mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
}
void spm_mcdi_wakeup_all_cores(void)
{
if (is_mcdi_ready() == 0)
return;
spm_mcdi_cpu_wake_up_event(1, 1);
while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_ALL_CORE_AWAKE)
;
spm_mcdi_cpu_wake_up_event(1, 0);
while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_OFFLOADED)
;
spm_clean_after_wakeup();
clear_all_ready();
}
static void spm_mcdi_wfi_sel_enter(unsigned long mpidr)
{
int core_id_val = mpidr & MPIDR_CPU_MASK;
int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
/* SPM WFI Select by core number */
if (cluster_id) {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 1);
break;
case 1:
mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 1);
break;
case 2:
mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 1);
break;
case 3:
mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 1);
break;
default:
break;
}
} else {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 1);
break;
case 1:
mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 1);
break;
case 2:
mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 1);
break;
case 3:
mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 1);
break;
default:
break;
}
}
}
static void spm_mcdi_wfi_sel_leave(unsigned long mpidr)
{
int core_id_val = mpidr & MPIDR_CPU_MASK;
int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
/* SPM WFI Select by core number */
if (cluster_id) {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 0);
mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 0);
break;
case 1:
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 0);
mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 0);
break;
case 2:
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 0);
mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 0);
break;
case 3:
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 0);
mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 0);
break;
default:
break;
}
} else {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 0);
mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 0);
break;
case 1:
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 0);
mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 0);
break;
case 2:
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 0);
mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 0);
break;
case 3:
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 0);
mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 0);
break;
default:
break;
}
}
}
static void spm_mcdi_set_cputop_pwrctrl_for_cluster_off(unsigned long mpidr)
{
unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK;
unsigned long cpu_id = mpidr & MPIDR_CPU_MASK;
unsigned int pwr_status, shift, i, flag = 0;
pwr_status = mmio_read_32(SPM_PWR_STATUS) |
mmio_read_32(SPM_PWR_STATUS_2ND);
if (cluster_id) {
for (i = 0; i < PLATFORM_CLUSTER1_CORE_COUNT; i++) {
if (i == cpu_id)
continue;
shift = i + PCM_MCDI_CA72_PWRSTA_SHIFT;
flag |= (pwr_status & (1 << shift)) >> shift;
}
if (!flag)
mmio_setbits_32(SPM_PCM_RESERVE,
PCM_MCDI_CA72_CPUTOP_PWRCTL);
} else {
for (i = 0; i < PLATFORM_CLUSTER0_CORE_COUNT; i++) {
if (i == cpu_id)
continue;
shift = i + PCM_MCDI_CA53_PWRSTA_SHIFT;
flag |= (pwr_status & (1 << shift)) >> shift;
}
if (!flag)
mmio_setbits_32(SPM_PCM_RESERVE,
PCM_MCDI_CA53_CPUTOP_PWRCTL);
}
}
static void spm_mcdi_clear_cputop_pwrctrl_for_cluster_on(unsigned long mpidr)
{
unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK;
if (cluster_id)
mmio_clrbits_32(SPM_PCM_RESERVE,
PCM_MCDI_CA72_CPUTOP_PWRCTL);
else
mmio_clrbits_32(SPM_PCM_RESERVE,
PCM_MCDI_CA53_CPUTOP_PWRCTL);
}
void spm_mcdi_prepare_for_mtcmos(void)
{
const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc;
struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl;
if (is_mcdi_ready() == 0) {
if (is_hotplug_ready() == 1)
spm_clear_hotplug();
set_pwrctrl_pcm_flags(pwrctrl, 0);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcmdesc);
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
set_mcdi_ready();
}
}
void spm_mcdi_prepare_for_off_state(unsigned long mpidr, unsigned int afflvl)
{
const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc;
struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl;
spm_lock_get();
if (is_mcdi_ready() == 0) {
if (is_hotplug_ready() == 1)
spm_clear_hotplug();
set_pwrctrl_pcm_flags(pwrctrl, 0);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcmdesc);
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
set_mcdi_ready();
}
spm_mcdi_wfi_sel_enter(mpidr);
if (afflvl == MPIDR_AFFLVL1)
spm_mcdi_set_cputop_pwrctrl_for_cluster_off(mpidr);
spm_lock_release();
}
void spm_mcdi_finish_for_on_state(unsigned long mpidr, unsigned int afflvl)
{
unsigned long linear_id;
linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) |
(mpidr & MPIDR_CPU_MASK);
spm_lock_get();
spm_mcdi_clear_cputop_pwrctrl_for_cluster_on(mpidr);
spm_mcdi_wfi_sel_leave(mpidr);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, (0x1 << linear_id));
spm_lock_release();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h
+14
View File
@@ -0,0 +1,14 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_MCDI_H
#define SPM_MCDI_H
void spm_mcdi_wakeup_all_cores(void);
void spm_mcdi_prepare_for_mtcmos(void);
void spm_mcdi_prepare_for_off_state(unsigned long mpidr, unsigned int afflvl);
void spm_mcdi_finish_for_on_state(unsigned long mpidr, unsigned int afflvl);
#endif /* SPM_MCDI_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
+315
View File
@@ -0,0 +1,315 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <mt8173_def.h>
#include <spm.h>
#include <spm_suspend.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware.
* This driver controls the system power in system suspend flow.
*/
#define WAKE_SRC_FOR_SUSPEND \
(WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \
WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \
WAKE_SRC_SYSPWREQ | WAKE_SRC_ALL_MD32)
#define WAKE_SRC_FOR_MD32 0
#define spm_is_wakesrc_invalid(wakesrc) \
(!!((unsigned int)(wakesrc) & 0xc0003803))
#define ARMCA15PLL_CON0 (APMIXED_BASE + 0x200)
#define ARMCA15PLL_CON1 (APMIXED_BASE + 0x204)
#define ARMCA15PLL_PWR_CON0 (APMIXED_BASE + 0x20c)
#define ARMCA15PLL_PWR_ON (1U << 0)
#define ARMCA15PLL_ISO_EN (1U << 1)
#define ARMCA15PLL_EN (1U << 0)
const unsigned int spm_flags =
SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS |
SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS;
enum wake_reason_t spm_wake_reason = WR_NONE;
/**********************************************************
* PCM sequence for cpu suspend
**********************************************************/
static const unsigned int suspend_binary_ca7[] = {
0x81f58407, 0x81f68407, 0x803a0400, 0x803a8400, 0x1b80001f, 0x20000000,
0x80300400, 0x80318400, 0x80328400, 0xa1d28407, 0x81f20407, 0x81009801,
0xd8000244, 0x17c07c1f, 0x18c0001f, 0x10006234, 0xc0c032e0, 0x1200041f,
0x80310400, 0x1b80001f, 0x2000000a, 0xa0110400, 0x18c0001f, 0x100062c8,
0xe0e00010, 0xe0e00030, 0xe0e00070, 0xe0e000f0, 0x1b80001f, 0x2000001a,
0xe0e00ff0, 0xe8208000, 0x10006354, 0xfffe7fff, 0xe8208000, 0x10006834,
0x00000010, 0x81f00407, 0xa1dd0407, 0x81fd0407, 0xc2803800, 0x1290041f,
0x8880000c, 0x2f7be75f, 0xd8200722, 0x17c07c1f, 0xd82006a9, 0x17c07c1f,
0xe8208000, 0x10006814, 0x00000001, 0xc2803800, 0x1293841f, 0x1b00001f,
0x7fffe7ff, 0xd0000760, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xf0000000,
0x17c07c1f, 0x80880001, 0xd8000842, 0x17c07c1f, 0xd00028e0, 0x1200041f,
0xe8208000, 0x10006834, 0x00000000, 0x1b00001f, 0x3fffe7ff, 0x1b80001f,
0x20000004, 0xd8200a0c, 0x17c07c1f, 0xe8208000, 0x10006834, 0x00000010,
0xd0001280, 0x17c07c1f, 0x18c0001f, 0x10006608, 0x1910001f, 0x10006608,
0x813b0404, 0xe0c00004, 0x1880001f, 0x10006320, 0xc0c03760, 0xe080000f,
0xd8200c03, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xd0001280, 0x17c07c1f,
0xe080001f, 0xe8208000, 0x10006354, 0xffffffff, 0x18c0001f, 0x100062c8,
0xe0e000f0, 0xe0e00030, 0xe0e00000, 0x81009801, 0xd80010c4, 0x17c07c1f,
0x18c0001f, 0x10004094, 0x1910001f, 0x1020e374, 0xe0c00004, 0x18c0001f,
0x10004098, 0x1910001f, 0x1020e378, 0xe0c00004, 0x18c0001f, 0x10011094,
0x1910001f, 0x10213374, 0xe0c00004, 0x18c0001f, 0x10011098, 0x1910001f,
0x10213378, 0xe0c00004, 0x1910001f, 0x10213378, 0x18c0001f, 0x10006234,
0xc0c034a0, 0x17c07c1f, 0xc2803800, 0x1290841f, 0xa1d20407, 0x81f28407,
0xa1d68407, 0xa0128400, 0xa0118400, 0xa0100400, 0xa01a8400, 0xa01a0400,
0x19c0001f, 0x001c239f, 0x1b00001f, 0x3fffefff, 0xf0000000, 0x17c07c1f,
0x808d8001, 0xd8201502, 0x17c07c1f, 0x803d8400, 0x1b80001f, 0x2000001a,
0x80340400, 0x17c07c1f, 0x17c07c1f, 0x80310400, 0x81fa0407, 0x81f18407,
0x81f08407, 0xa1dc0407, 0x1b80001f, 0x200000b6, 0xd0002220, 0x17c07c1f,
0x1880001f, 0x20000208, 0x81011801, 0xd80016e4, 0x17c07c1f, 0xe8208000,
0x1000f600, 0xd2000000, 0x1380081f, 0x18c0001f, 0x10006240, 0xe0e00016,
0xe0e0001e, 0xe0e0000e, 0xe0e0000f, 0x80368400, 0x1380081f, 0x80370400,
0x1380081f, 0x80360400, 0x803e0400, 0x1380081f, 0x80380400, 0x803b0400,
0xa01d8400, 0x1b80001f, 0x20000034, 0x803d8400, 0x1b80001f, 0x20000152,
0x803d0400, 0x1380081f, 0x18c0001f, 0x1000f5c8, 0x1910001f, 0x1000f5c8,
0xa1000404, 0xe0c00004, 0x18c0001f, 0x100125c8, 0x1910001f, 0x100125c8,
0xa1000404, 0xe0c00004, 0x1910001f, 0x100125c8, 0x80340400, 0x17c07c1f,
0x17c07c1f, 0x80310400, 0xe8208000, 0x10000044, 0x00000100, 0x1b80001f,
0x20000068, 0x1b80001f, 0x2000000a, 0x18c0001f, 0x10006240, 0xe0e0000d,
0x81011801, 0xd8001f64, 0x17c07c1f, 0x18c0001f, 0x100040f4, 0x1910001f,
0x100040f4, 0xa11c8404, 0xe0c00004, 0x1b80001f, 0x2000000a, 0x813c8404,
0xe0c00004, 0x18c0001f, 0x100110f4, 0x1910001f, 0x100110f4, 0xa11c8404,
0xe0c00004, 0x1b80001f, 0x2000000a, 0x813c8404, 0xe0c00004, 0x1b80001f,
0x20000100, 0x81fa0407, 0x81f18407, 0x81f08407, 0xe8208000, 0x10006354,
0xfffe7b47, 0x18c0001f, 0x65930003, 0xc0c031c0, 0x17c07c1f, 0xc2803800,
0x1293041f, 0xa1d80407, 0xa1dc0407, 0x18c0001f, 0x10006608, 0x1910001f,
0x10006608, 0xa11b0404, 0xe0c00004, 0xc2803800, 0x1291041f, 0x8880000c,
0x2f7be75f, 0xd8202362, 0x17c07c1f, 0x1b00001f, 0x3fffe7ff, 0xd00023a0,
0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xf0000000, 0x17c07c1f, 0x1890001f,
0x10006608, 0x808b0801, 0xd8202642, 0x17c07c1f, 0x1880001f, 0x10006320,
0xc0c03540, 0xe080000f, 0xd80027a3, 0x17c07c1f, 0xe080001f, 0xa1da0407,
0x81fc0407, 0xa0110400, 0xa0140400, 0xa01d8400, 0xd0003100, 0x17c07c1f,
0x1b80001f, 0x20000fdf, 0x1890001f, 0x10006608, 0x80c98801, 0x810a8801,
0x10918c1f, 0xa0939002, 0x8080080d, 0xd82028e2, 0x12007c1f, 0x1b00001f,
0x3fffe7ff, 0x1b80001f, 0x20000004, 0xd800318c, 0x17c07c1f, 0x1b00001f,
0xbfffe7ff, 0xd0003180, 0x17c07c1f, 0x81f80407, 0x81fc0407, 0x18c0001f,
0x65930006, 0xc0c031c0, 0x17c07c1f, 0x18c0001f, 0x65930007, 0xc0c031c0,
0x17c07c1f, 0x1880001f, 0x10006320, 0xc0c03540, 0xe080000f, 0xd80027a3,
0x17c07c1f, 0xe080001f, 0x18c0001f, 0x65930005, 0xc0c031c0, 0x17c07c1f,
0xa1da0407, 0xe8208000, 0x10000048, 0x00000100, 0x1b80001f, 0x20000068,
0xa0110400, 0xa0140400, 0x18c0001f, 0x1000f5c8, 0x1910001f, 0x1000f5c8,
0x81200404, 0xe0c00004, 0x18c0001f, 0x100125c8, 0x1910001f, 0x100125c8,
0x81200404, 0xe0c00004, 0x1910001f, 0x100125c8, 0xa01d0400, 0xa01b0400,
0xa0180400, 0x803d8400, 0xa01e0400, 0xa0160400, 0xa0170400, 0xa0168400,
0x1b80001f, 0x20000104, 0x81011801, 0xd80030c4, 0x17c07c1f, 0x18c0001f,
0x10006240, 0xc0c034a0, 0x17c07c1f, 0xe8208000, 0x1000f600, 0xd2000001,
0xd8000848, 0x17c07c1f, 0xc2803800, 0x1291841f, 0x1b00001f, 0x7ffff7ff,
0xf0000000, 0x17c07c1f, 0x1900001f, 0x10006830, 0xe1000003, 0x18c0001f,
0x10006834, 0xe0e00000, 0xe0e00001, 0xf0000000, 0x17c07c1f, 0xe0f07f16,
0x1380201f, 0xe0f07f1e, 0x1380201f, 0xe0f07f0e, 0x1b80001f, 0x20000104,
0xe0f07f0c, 0xe0f07f0d, 0xe0f07e0d, 0xe0f07c0d, 0xe0f0780d, 0xf0000000,
0xe0f0700d, 0xe0f07f0d, 0xe0f07f0f, 0xe0f07f1e, 0xf0000000, 0xe0f07f12,
0x11407c1f, 0x81f08407, 0x81f18407, 0x1b80001f, 0x20000001, 0xa1d08407,
0xa1d18407, 0x1392841f, 0x812ab401, 0x80ebb401, 0xa0c00c04, 0xd8203743,
0x17c07c1f, 0x80c01403, 0xd8203563, 0x01400405, 0xf0000000, 0xa1d00407,
0x1b80001f, 0x20000208, 0x80ea3401, 0xf0000000, 0x18c0001f, 0x10006b6c,
0x1910001f, 0x10006b6c, 0xa1002804, 0xf0000000, 0xe0c00004, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0xa1d48407, 0x1990001f,
0x10006b08, 0x1a50001f, 0x10006610, 0x8246a401, 0xe8208000, 0x10006b6c,
0x00000000, 0x1b00001f, 0x2f7be75f, 0x81469801, 0xd8004305, 0x17c07c1f,
0x1b80001f, 0xd00f0000, 0x8880000c, 0x2f7be75f, 0xd8005fa2, 0x17c07c1f,
0xd0004340, 0x17c07c1f, 0x1b80001f, 0x500f0000, 0xe8208000, 0x10006354,
0xfffe7b47, 0xc0c06c00, 0x81401801, 0xd80048e5, 0x17c07c1f, 0x81f60407,
0x18c0001f, 0x10006200, 0xc0c06060, 0x12807c1f, 0xe8208000, 0x1000625c,
0x00000001, 0x1b80001f, 0x20000080, 0xc0c06060, 0x1280041f, 0x18c0001f,
0x10006204, 0xc0c06400, 0x1280041f, 0x18c0001f, 0x10006208, 0xc0c06060,
0x12807c1f, 0xe8208000, 0x10006244, 0x00000001, 0x1b80001f, 0x20000080,
0xc0c06060, 0x1280041f, 0x18d0001f, 0x10200200, 0x18c0001f, 0x10006290,
0xc0c06060, 0x1280041f, 0xe8208000, 0x10006404, 0x00003101, 0xc2803800,
0x1292041f, 0x81469801, 0xd8204a45, 0x17c07c1f, 0x1b00001f, 0x2f7be75f,
0x1b80001f, 0x30000004, 0x8880000c, 0x2f7be75f, 0xd8005a02, 0x17c07c1f,
0xc0c06780, 0x17c07c1f, 0x18c0001f, 0x10006294, 0xe0f07fff, 0xe0e00fff,
0xe0e000ff, 0x81449801, 0xd8004c85, 0x17c07c1f, 0x1a00001f, 0x10006604,
0xe2200003, 0xc0c06840, 0x17c07c1f, 0xe2200005, 0xc0c06840, 0x17c07c1f,
0xa1d38407, 0xa1d98407, 0x1800001f, 0x00000012, 0x1800001f, 0x00000e12,
0x1800001f, 0x03800e12, 0x1800001f, 0x038e0e12, 0xe8208000, 0x10006310,
0x0b1600f8, 0x1940001f, 0x00000000, 0x12407c1f, 0x1b00001f, 0xbfffe7ff,
0x1b80001f, 0x90100000, 0x17c07c1f, 0xd8004fc5, 0x17c07c1f, 0x8247b001,
0x1940001f, 0xffffffff, 0x80c00400, 0xd82050c3, 0xa1d58407, 0xa1dd8407,
0x1b00001f, 0x3fffefff, 0xd0004ec0, 0x17c07c1f, 0x1890001f, 0x100063e8,
0x88c0000c, 0x2f7be75f, 0xd80052e3, 0x17c07c1f, 0x80c40001, 0xd8005263,
0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xd00052a0, 0x17c07c1f, 0x1b00001f,
0x7ffff7ff, 0xd0004ec0, 0x17c07c1f, 0x80c40001, 0xd82053e3, 0x17c07c1f,
0xa1de0407, 0x1b00001f, 0x7fffe7ff, 0xd0004ec0, 0x17c07c1f, 0xe8208000,
0x10006814, 0x00000000, 0x18c0001f, 0x10006b00, 0xe0e00000, 0xe0c00009,
0x18c0001f, 0x10006294, 0xe0e001fe, 0xe0e003fc, 0xe0e007f8, 0xe0e00ff0,
0x1b80001f, 0x20000020, 0xe0f07ff0, 0xe0f07f00, 0x81449801, 0xd80057a5,
0x17c07c1f, 0x1a00001f, 0x10006604, 0xe2200002, 0xc0c06840, 0x17c07c1f,
0xe2200004, 0xc0c06840, 0x17c07c1f, 0x1b80001f, 0x200016a8, 0x1800001f,
0x03800e12, 0x1b80001f, 0x20000300, 0x1800001f, 0x00000e12, 0x1b80001f,
0x20000300, 0x1800001f, 0x00000012, 0x1b80001f, 0x20000104, 0x10007c1f,
0x81f38407, 0x81f98407, 0x81f90407, 0x81f40407, 0x1b80001f, 0x200016a8,
0x81401801, 0xd8005fa5, 0x17c07c1f, 0xe8208000, 0x10006404, 0x00002101,
0x18c0001f, 0x10006290, 0x1212841f, 0xc0c061e0, 0x12807c1f, 0xc0c061e0,
0x1280041f, 0x18c0001f, 0x10006208, 0x1212841f, 0xc0c061e0, 0x12807c1f,
0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xc0c061e0,
0x1280041f, 0xe8208000, 0x10200268, 0x000ffffe, 0x18c0001f, 0x10006204,
0x1212841f, 0xc0c065a0, 0x1280041f, 0x18c0001f, 0x10006200, 0x1212841f,
0xc0c061e0, 0x12807c1f, 0xe8208000, 0x1000625c, 0x00000000, 0x1b80001f,
0x20000080, 0xc0c061e0, 0x1280041f, 0x19c0001f, 0x01411820, 0x1ac0001f,
0x55aa55aa, 0x10007c1f, 0xf0000000, 0xd800610a, 0x17c07c1f, 0xe2e0004f,
0xe2e0006f, 0xe2e0002f, 0xd82061aa, 0x17c07c1f, 0xe2e0002e, 0xe2e0003e,
0xe2e00032, 0xf0000000, 0x17c07c1f, 0xd80062aa, 0x17c07c1f, 0xe2e00036,
0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xd82063ca, 0x17c07c1f, 0x1380201f,
0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d,
0xf0000000, 0x17c07c1f, 0x1a50001f, 0x10006610, 0x8246a401, 0xd8206569,
0x17c07c1f, 0xe2e0000d, 0xe2e0000c, 0xe2e0001c, 0xe2e0001e, 0xe2e00016,
0xe2e00012, 0xf0000000, 0x17c07c1f, 0x1a50001f, 0x10006610, 0x8246a401,
0xd8206749, 0x17c07c1f, 0xe2e00016, 0x1380201f, 0xe2e0001e, 0x1380201f,
0xe2e0001c, 0x1380201f, 0xe2e0000c, 0xe2e0000d, 0xf0000000, 0x17c07c1f,
0xa1d40407, 0x1391841f, 0xa1d90407, 0x1393041f, 0xf0000000, 0x17c07c1f,
0x18d0001f, 0x10006604, 0x10cf8c1f, 0xd8206843, 0x17c07c1f, 0xf0000000,
0x17c07c1f, 0xe8208000, 0x11008014, 0x00000002, 0xe8208000, 0x11008020,
0x00000101, 0xe8208000, 0x11008004, 0x000000d0, 0x1a00001f, 0x11008000,
0xd8006b0a, 0xe220005d, 0xd8206b2a, 0xe2200000, 0xe2200001, 0xe8208000,
0x11008024, 0x00000001, 0x1b80001f, 0x20000424, 0xf0000000, 0x17c07c1f,
0xa1d10407, 0x1b80001f, 0x20000020, 0xf0000000, 0x17c07c1f
};
/*
* PCM binary for suspend scenario
*/
static const struct pcm_desc suspend_pcm_ca7 = {
.version = "pcm_suspend_20150917_V4",
.base = suspend_binary_ca7,
.size = 869,
.sess = 2,
.replace = 0,
.vec0 = EVENT_VEC(11, 1, 0, 0),
.vec1 = EVENT_VEC(12, 1, 0, 61),
.vec2 = EVENT_VEC(30, 1, 0, 150),
.vec3 = EVENT_VEC(31, 1, 0, 287),
};
/*
* SPM settings for suspend scenario
*/
static struct pwr_ctrl spm_ctrl = {
.wake_src = WAKE_SRC_FOR_SUSPEND,
.wake_src_md32 = WAKE_SRC_FOR_MD32,
.r0_ctrl_en = 1,
.r7_ctrl_en = 1,
.infra_dcm_lock = 1,
.wfi_op = WFI_OP_AND,
.pcm_apsrc_req = 0,
.ca7top_idle_mask = 0,
.ca15top_idle_mask = 0,
.mcusys_idle_mask = 0,
.disp_req_mask = 0,
.mfg_req_mask = 0,
.md32_req_mask = 1,
.srclkenai_mask = 1,
.ca7_wfi0_en = 1,
.ca7_wfi1_en = 1,
.ca7_wfi2_en = 1,
.ca7_wfi3_en = 1,
.ca15_wfi0_en = 1,
.ca15_wfi1_en = 1,
.ca15_wfi2_en = 1,
.ca15_wfi3_en = 1,
};
/*
* go_to_sleep_before_wfi() - trigger SPM to enter suspend scenario
*/
static void go_to_sleep_before_wfi(const unsigned int flags_spm)
{
struct pwr_ctrl *pwrctrl;
pwrctrl = &spm_ctrl;
set_pwrctrl_pcm_flags(pwrctrl, flags_spm);
spm_set_sysclk_settle();
INFO("sec = %u, wakesrc = 0x%x (%u)(%u)\n",
pwrctrl->timer_val, pwrctrl->wake_src,
is_cpu_pdn(pwrctrl->pcm_flags),
is_infra_pdn(pwrctrl->pcm_flags));
spm_reset_and_init_pcm();
spm_init_pcm_register();
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
spm_init_event_vector(&suspend_pcm_ca7);
spm_kick_im_to_fetch(&suspend_pcm_ca7);
}
/*
* go_to_sleep_after_wfi() - get wakeup reason after
* leaving suspend scenario and clean up SPM settings
*/
static enum wake_reason_t go_to_sleep_after_wfi(void)
{
struct wake_status wakesta;
static enum wake_reason_t last_wr = WR_NONE;
spm_get_wakeup_status(&wakesta);
spm_clean_after_wakeup();
last_wr = spm_output_wake_reason(&wakesta);
return last_wr;
}
static void bigcore_pll_on(void)
{
mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON);
mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN);
mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN);
}
static void bigcore_pll_off(void)
{
mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN);
mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN);
mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON);
}
void spm_system_suspend(void)
{
bigcore_pll_off();
spm_lock_get();
go_to_sleep_before_wfi(spm_flags);
set_suspend_ready();
spm_lock_release();
}
void spm_system_suspend_finish(void)
{
spm_lock_get();
spm_wake_reason = go_to_sleep_after_wfi();
INFO("spm_wake_reason=%d\n", spm_wake_reason);
clear_all_ready();
spm_lock_release();
bigcore_pll_on();
/* Add 20us delay for turning on PLL*/
udelay(20);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/spm/spm_suspend.h
+16
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@@ -0,0 +1,16 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_SUSPEND_H
#define SPM_SUSPEND_H
/* cpu dormant return code */
#define CPU_DORMANT_RESET 0
#define CPU_DORMANT_ABORT 1
void spm_system_suspend(void);
void spm_system_suspend_finish(void);
#endif /* SPM_SUSPEND_H*/
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c
+34
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@@ -0,0 +1,34 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <lib/mmio.h>
#include <mcucfg.h>
#include <mt8173_def.h>
#include <mt_cpuxgpt.h>
static void write_cpuxgpt(unsigned int reg_index, unsigned int value)
{
mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_idx, reg_index);
mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_ctl, value);
}
static void cpuxgpt_set_init_cnt(unsigned int countH, unsigned int countL)
{
write_cpuxgpt(INDEX_CNT_H_INIT, countH);
/* update count when countL programmed */
write_cpuxgpt(INDEX_CNT_L_INIT, countL);
}
void generic_timer_backup(void)
{
uint64_t cval;
cval = read_cntpct_el0();
cpuxgpt_set_init_cnt((uint32_t)(cval >> 32),
(uint32_t)(cval & 0xffffffff));
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_CPUXGPT_H
#define MT_CPUXGPT_H
/* REG */
#define INDEX_CNT_L_INIT 0x008
#define INDEX_CNT_H_INIT 0x00C
void generic_timer_backup(void);
#endif /* MT_CPUXGPT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/wdt/wdt.c
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/*
* Copyright (c) 2020, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt8173_def.h>
#include <plat_sip_calls.h>
#include <lib/psci/psci.h>
#include <smccc_helpers.h>
#include <wdt.h>
#define WDT_BASE (RGU_BASE + 0)
#define WDT_MODE (WDT_BASE + 0x00)
#define WDT_LENGTH (WDT_BASE + 0x04)
#define WDT_RESTART (WDT_BASE + 0x08)
#define WDT_SWRST (WDT_BASE + 0x14)
#define WDT_MODE_DUAL_MODE 0x40
#define WDT_MODE_IRQ 0x8
#define WDT_MODE_KEY 0x22000000
#define WDT_MODE_EXTEN 0x4
#define WDT_MODE_EN 0x1
#define WDT_LENGTH_KEY 0x8
#define WDT_RESTART_KEY 0x1971
#define WDT_SWRST_KEY 0x1209
#define WDT_MIN_TIMEOUT 1
#define WDT_MAX_TIMEOUT 31
enum smcwd_call {
SMCWD_INFO = 0,
SMCWD_SET_TIMEOUT = 1,
SMCWD_ENABLE = 2,
SMCWD_PET = 3,
};
static int wdt_enabled_before_suspend;
/*
* We expect the WDT registers to be correctly initialized by BL2 firmware
* (which may be board specific), so we do not reinitialize them here.
*/
void wdt_trigger_reset(void)
{
mmio_write_32(WDT_SWRST, WDT_SWRST_KEY);
}
void wdt_pet(void)
{
mmio_write_32(WDT_RESTART, WDT_RESTART_KEY);
}
int wdt_set_timeout(uint32_t timeout)
{
/* One tick here equals 512 32KHz ticks. 512 / 32000 * 125 / 2 = 1 */
uint32_t ticks = timeout * 125 / 2;
if (timeout < WDT_MIN_TIMEOUT || timeout > WDT_MAX_TIMEOUT)
return PSCI_E_INVALID_PARAMS;
mmio_write_32(WDT_LENGTH, ticks << 5 | WDT_LENGTH_KEY);
return PSCI_E_SUCCESS;
}
void wdt_set_enable(int enable)
{
if (enable)
wdt_pet();
mmio_clrsetbits_32(WDT_MODE, WDT_MODE_EN,
WDT_MODE_KEY | (enable ? WDT_MODE_EN : 0));
}
void wdt_suspend(void)
{
wdt_enabled_before_suspend = mmio_read_32(WDT_MODE) & WDT_MODE_EN;
if (wdt_enabled_before_suspend)
wdt_set_enable(0);
}
void wdt_resume(void)
{
if (wdt_enabled_before_suspend)
wdt_set_enable(1);
}
uint64_t wdt_smc_handler(uint32_t x1,
uint32_t x2,
void *handle)
{
int ret;
switch (x1) {
case SMCWD_INFO:
SMC_RET3(handle, PSCI_E_SUCCESS,
WDT_MIN_TIMEOUT, WDT_MAX_TIMEOUT);
case SMCWD_SET_TIMEOUT:
ret = wdt_set_timeout(x2);
SMC_RET1(handle, ret);
case SMCWD_ENABLE:
wdt_set_enable(x2 > 0);
SMC_RET1(handle, PSCI_E_SUCCESS);
case SMCWD_PET:
wdt_pet();
SMC_RET1(handle, PSCI_E_SUCCESS);
default:
ERROR("Unimplemented SMCWD call (%d)\n", x1);
SMC_RET1(handle, PSCI_E_NOT_SUPPORTED);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8173/drivers/wdt/wdt.h
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/*
* Copyright (c) 2020, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef WDT_H
#define WDT_H
#include "stdint.h"
void wdt_pet(void);
void wdt_resume(void);
void wdt_set_enable(int enable);
int wdt_set_timeout(uint32_t timeout);
uint64_t wdt_smc_handler(uint32_t x1, uint32_t x2, void *handle);
void wdt_suspend(void);
void wdt_trigger_reset(void);
#endif /* WDT_H */