GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <mt8173_def.h>
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#include <mtcmos.h>
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#include <spm.h>
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#include <spm_mcdi.h>
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enum {
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SRAM_ISOINT_B = 1U << 6,
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SRAM_CKISO = 1U << 5,
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PWR_CLK_DIS = 1U << 4,
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PWR_ON_2ND = 1U << 3,
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PWR_ON = 1U << 2,
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PWR_ISO = 1U << 1,
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PWR_RST_B = 1U << 0
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};
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enum {
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L1_PDN_ACK = 1U << 8,
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L1_PDN = 1U << 0
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};
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enum {
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LITTLE_CPU3 = 1U << 12,
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LITTLE_CPU2 = 1U << 11,
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LITTLE_CPU1 = 1U << 10,
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};
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enum {
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SRAM_PDN = 0xf << 8,
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DIS_SRAM_ACK = 0x1 << 12,
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AUD_SRAM_ACK = 0xf << 12,
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};
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enum {
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DIS_PWR_STA_MASK = 0x1 << 3,
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AUD_PWR_STA_MASK = 0x1 << 24,
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};
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#define SPM_VDE_PWR_CON 0x0210
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#define SPM_MFG_PWR_CON 0x0214
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#define SPM_VEN_PWR_CON 0x0230
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#define SPM_ISP_PWR_CON 0x0238
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#define SPM_DIS_PWR_CON 0x023c
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#define SPM_VEN2_PWR_CON 0x0298
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#define SPM_AUDIO_PWR_CON 0x029c
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#define SPM_MFG_2D_PWR_CON 0x02c0
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4
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#define SPM_USB_PWR_CON 0x02cc
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#define MTCMOS_CTRL_SUCCESS 0
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#define MTCMOS_CTRL_ERROR -1
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#define MTCMOS_CTRL_EN (0x1 << 18)
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#define VDE_PWR_ON 0
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#define VEN_PWR_ON 1
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#define ISP_PWR_ON 2
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#define DIS_PWR_ON 3
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#define VEN2_PWR_ON 4
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#define AUDIO_PWR_ON 5
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#define MFG_ASYNC_PWR_ON 6
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#define MFG_2D_PWR_ON 7
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#define MFG_PWR_ON 8
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#define USB_PWR_ON 9
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#define VDE_PWR_OFF 10
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#define VEN_PWR_OFF 11
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#define ISP_PWR_OFF 12
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#define DIS_PWR_OFF 13
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#define VEN2_PWR_OFF 14
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#define AUDIO_PWR_OFF 15
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#define MFG_ASYNC_PWR_OFF 16
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#define MFG_2D_PWR_OFF 17
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#define MFG_PWR_OFF 18
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#define USB_PWR_OFF 19
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#define VDE_PWR_CON_PWR_STA 7
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#define VEN_PWR_CON_PWR_STA 21
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#define ISP_PWR_CON_PWR_STA 5
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#define DIS_PWR_CON_PWR_STA 3
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#define VEN2_PWR_CON_PWR_STA 20
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#define AUDIO_PWR_CON_PWR_STA 24
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#define MFG_ASYNC_PWR_CON_PWR_STA 23
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#define MFG_2D_PWR_CON_PWR_STA 22
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#define MFG_PWR_CON_PWR_STA 4
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#define USB_PWR_CON_PWR_STA 25
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/*
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* Timeout if the ack is not signled after 1 second.
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* According to designer, one mtcmos operation should be done
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* around 10us.
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*/
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#define MTCMOS_ACK_POLLING_MAX_COUNT 10000
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#define MTCMOS_ACK_POLLING_INTERVAL 10
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static void mtcmos_ctrl_little_off(unsigned int linear_id)
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{
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uint32_t reg_pwr_con;
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uint32_t reg_l1_pdn;
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uint32_t bit_cpu;
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switch (linear_id) {
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case 1:
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reg_pwr_con = SPM_CA7_CPU1_PWR_CON;
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reg_l1_pdn = SPM_CA7_CPU1_L1_PDN;
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bit_cpu = LITTLE_CPU1;
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break;
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case 2:
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reg_pwr_con = SPM_CA7_CPU2_PWR_CON;
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reg_l1_pdn = SPM_CA7_CPU2_L1_PDN;
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bit_cpu = LITTLE_CPU2;
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break;
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case 3:
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reg_pwr_con = SPM_CA7_CPU3_PWR_CON;
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reg_l1_pdn = SPM_CA7_CPU3_L1_PDN;
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bit_cpu = LITTLE_CPU3;
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break;
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default:
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/* should never come to here */
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return;
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}
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/* enable register control */
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mmio_write_32(SPM_POWERON_CONFIG_SET,
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(SPM_PROJECT_CODE << 16) | (1U << 0));
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mmio_setbits_32(reg_pwr_con, PWR_ISO);
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mmio_setbits_32(reg_pwr_con, SRAM_CKISO);
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mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B);
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mmio_setbits_32(reg_l1_pdn, L1_PDN);
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while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK))
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continue;
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mmio_clrbits_32(reg_pwr_con, PWR_RST_B);
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mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS);
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mmio_clrbits_32(reg_pwr_con, PWR_ON);
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mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND);
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while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) ||
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(mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu))
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continue;
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}
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void mtcmos_little_cpu_off(void)
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{
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/* turn off little cpu 1 - 3 */
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mtcmos_ctrl_little_off(1);
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mtcmos_ctrl_little_off(2);
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mtcmos_ctrl_little_off(3);
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}
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uint32_t wait_mtcmos_ack(uint32_t on, uint32_t pwr_ctrl, uint32_t spm_pwr_sta)
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{
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int i = 0;
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uint32_t cmp, pwr_sta, pwr_sta_2nd;
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while (1) {
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cmp = mmio_read_32(SPM_PCM_PASR_DPD_3) & pwr_ctrl;
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pwr_sta = (mmio_read_32(SPM_PWR_STATUS) >> spm_pwr_sta) & 1;
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pwr_sta_2nd =
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(mmio_read_32(SPM_PWR_STATUS_2ND) >> spm_pwr_sta) & 1;
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if (cmp && (pwr_sta == on) && (pwr_sta_2nd == on)) {
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mmio_write_32(SPM_PCM_RESERVE2, 0);
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return MTCMOS_CTRL_SUCCESS;
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}
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udelay(MTCMOS_ACK_POLLING_INTERVAL);
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i++;
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if (i > MTCMOS_ACK_POLLING_MAX_COUNT) {
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INFO("MTCMOS control failed(%d), SPM_PWR_STA(%d),\n"
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"SPM_PCM_RESERVE=0x%x,SPM_PCM_RESERVE2=0x%x,\n"
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"SPM_PWR_STATUS=0x%x,SPM_PWR_STATUS_2ND=0x%x\n"
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"SPM_PCM_PASR_DPD_3 = 0x%x\n",
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on, spm_pwr_sta, mmio_read_32(SPM_PCM_RESERVE),
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mmio_read_32(SPM_PCM_RESERVE2),
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mmio_read_32(SPM_PWR_STATUS),
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mmio_read_32(SPM_PWR_STATUS_2ND),
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mmio_read_32(SPM_PCM_PASR_DPD_3));
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mmio_write_32(SPM_PCM_RESERVE2, 0);
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return MTCMOS_CTRL_ERROR;
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}
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}
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}
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uint32_t mtcmos_non_cpu_ctrl(uint32_t on, uint32_t mtcmos_num)
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{
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uint32_t ret = MTCMOS_CTRL_SUCCESS;
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uint32_t power_on;
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uint32_t power_off;
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uint32_t power_ctrl;
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uint32_t power_status;
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spm_lock_get();
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spm_mcdi_prepare_for_mtcmos();
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mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
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switch (mtcmos_num) {
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case SPM_VDE_PWR_CON:
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power_on = VDE_PWR_ON;
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power_off = VDE_PWR_OFF;
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power_status = VDE_PWR_CON_PWR_STA;
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break;
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case SPM_MFG_PWR_CON:
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power_on = MFG_PWR_ON;
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power_off = MFG_PWR_OFF;
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power_status = MFG_PWR_CON_PWR_STA;
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break;
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case SPM_VEN_PWR_CON:
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power_on = VEN_PWR_ON;
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power_off = VEN_PWR_OFF;
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power_status = VEN_PWR_CON_PWR_STA;
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break;
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case SPM_ISP_PWR_CON:
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power_on = ISP_PWR_ON;
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power_off = ISP_PWR_OFF;
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power_status = ISP_PWR_CON_PWR_STA;
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break;
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case SPM_DIS_PWR_CON:
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power_on = DIS_PWR_ON;
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power_off = DIS_PWR_OFF;
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power_status = DIS_PWR_CON_PWR_STA;
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break;
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case SPM_VEN2_PWR_CON:
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power_on = VEN2_PWR_ON;
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power_off = VEN2_PWR_OFF;
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power_status = VEN2_PWR_CON_PWR_STA;
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break;
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case SPM_AUDIO_PWR_CON:
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power_on = AUDIO_PWR_ON;
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power_off = AUDIO_PWR_OFF;
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power_status = AUDIO_PWR_CON_PWR_STA;
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break;
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case SPM_MFG_2D_PWR_CON:
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power_on = MFG_2D_PWR_ON;
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power_off = MFG_2D_PWR_OFF;
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power_status = MFG_2D_PWR_CON_PWR_STA;
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break;
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case SPM_MFG_ASYNC_PWR_CON:
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power_on = MFG_ASYNC_PWR_ON;
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power_off = MFG_ASYNC_PWR_OFF;
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power_status = MFG_ASYNC_PWR_CON_PWR_STA;
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break;
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case SPM_USB_PWR_CON:
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power_on = USB_PWR_ON;
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power_off = USB_PWR_OFF;
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power_status = USB_PWR_CON_PWR_STA;
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break;
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default:
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ret = MTCMOS_CTRL_ERROR;
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INFO("No mapping MTCMOS(%d), ret = %d\n", mtcmos_num, ret);
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break;
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}
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if (ret == MTCMOS_CTRL_SUCCESS) {
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power_ctrl = on ? (1 << power_on) : (1 << power_off);
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mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl);
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ret = wait_mtcmos_ack(on, power_ctrl, power_status);
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VERBOSE("0x%x(%d), PWR_STATUS(0x%x), ret(%d)\n",
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power_ctrl, on, mmio_read_32(SPM_PWR_STATUS), ret);
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}
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mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
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spm_lock_release();
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return ret;
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}
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