GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_H
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#define MCUCFG_H
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#include <stdint.h>
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#include <mt8173_def.h>
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struct mt8173_mcucfg_regs {
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uint32_t mp0_ca7l_cache_config;
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struct {
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uint32_t mem_delsel0;
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uint32_t mem_delsel1;
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} mp0_cpu[4];
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uint32_t mp0_cache_mem_delsel0;
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uint32_t mp0_cache_mem_delsel1;
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uint32_t mp0_axi_config;
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uint32_t mp0_misc_config[2];
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struct {
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uint32_t rv_addr_lw;
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uint32_t rv_addr_hw;
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} mp0_rv_addr[4];
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uint32_t mp0_ca7l_cfg_dis;
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uint32_t mp0_ca7l_clken_ctrl;
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uint32_t mp0_ca7l_rst_ctrl;
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uint32_t mp0_ca7l_misc_config;
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uint32_t mp0_ca7l_dbg_pwr_ctrl;
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uint32_t mp0_rw_rsvd0;
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uint32_t mp0_rw_rsvd1;
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uint32_t mp0_ro_rsvd;
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uint32_t reserved0_0[100];
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uint32_t mp1_cpucfg;
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uint32_t mp1_miscdbg;
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uint32_t reserved0_1[13];
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uint32_t mp1_rst_ctl;
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uint32_t mp1_clkenm_div;
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uint32_t reserved0_2[7];
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uint32_t mp1_config_res;
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uint32_t reserved0_3[13];
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struct {
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uint32_t rv_addr_lw;
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uint32_t rv_addr_hw;
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} mp1_rv_addr[2];
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uint32_t reserved0_4[84];
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uint32_t mp0_rst_status; /* 0x400 */
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uint32_t mp0_dbg_ctrl;
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uint32_t mp0_dbg_flag;
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uint32_t mp0_ca7l_ir_mon;
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struct {
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uint32_t pc_lw;
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uint32_t pc_hw;
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uint32_t fp_arch32;
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uint32_t sp_arch32;
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uint32_t fp_arch64_lw;
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uint32_t fp_arch64_hw;
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uint32_t sp_arch64_lw;
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uint32_t sp_arch64_hw;
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} mp0_dbg_core[4];
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uint32_t dfd_ctrl;
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uint32_t dfd_cnt_l;
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uint32_t dfd_cnt_h;
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uint32_t misccfg_mp0_rw_rsvd;
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uint32_t misccfg_sec_vio_status0;
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uint32_t misccfg_sec_vio_status1;
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uint32_t reserved1[22];
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uint32_t misccfg_rw_rsvd; /* 0x500 */
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uint32_t mcusys_dbg_mon_sel_a;
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uint32_t mcusys_dbg_mon;
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uint32_t reserved2[61];
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uint32_t mcusys_config_a; /* 0x600 */
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uint32_t mcusys_config1_a;
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uint32_t mcusys_gic_peribase_a;
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uint32_t reserved3;
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uint32_t sec_range0_start; /* 0x610 */
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uint32_t sec_range0_end;
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uint32_t sec_range_enable;
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uint32_t reserved4;
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uint32_t int_pol_ctl[8]; /* 0x620 */
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uint32_t aclken_div; /* 0x640 */
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uint32_t pclken_div;
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uint32_t l2c_sram_ctrl;
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uint32_t armpll_jit_ctrl;
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uint32_t cci_addrmap; /* 0x650 */
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uint32_t cci_config;
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uint32_t cci_periphbase;
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uint32_t cci_nevntcntovfl;
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uint32_t cci_clk_ctrl; /* 0x660 */
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uint32_t cci_acel_s1_ctrl;
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uint32_t bus_fabric_dcm_ctrl;
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uint32_t reserved5;
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uint32_t xgpt_ctl; /* 0x670 */
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uint32_t xgpt_idx;
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uint32_t ptpod2_ctl0;
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uint32_t ptpod2_ctl1;
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uint32_t mcusys_revid;
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uint32_t mcusys_rw_rsvd0;
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uint32_t mcusys_rw_rsvd1;
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};
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static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;
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/* cpu boot mode */
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#define MP0_CPUCFG_64BIT_SHIFT 12
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#define MP1_CPUCFG_64BIT_SHIFT 28
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#define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT)
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#define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT)
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/* scu related */
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enum {
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MP0_ACINACTM_SHIFT = 4,
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MP1_ACINACTM_SHIFT = 0,
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MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
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MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT
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};
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enum {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum {
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MP1_AINACTS_SHIFT = 4,
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MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
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};
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enum {
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MP1_SW_CG_GEN_SHIFT = 12,
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MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
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};
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enum {
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MP1_L2RSTDISABLE_SHIFT = 14,
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MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
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};
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/* cci clock control related */
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enum {
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MCU_BUS_DCM_EN = 1 << 8
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};
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/* l2c sram control related */
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enum {
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L2C_SRAM_DCM_EN = 1 << 0
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};
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/* bus fabric dcm control related */
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enum {
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PSYS_ADB400_DCM_EN = 1 << 29,
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GPU_ADB400_DCM_EN = 1 << 28,
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EMI1_ADB400_DCM_EN = 1 << 27,
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EMI_ADB400_DCM_EN = 1 << 26,
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INFRA_ADB400_DCM_EN = 1 << 25,
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L2C_ADB400_DCM_EN = 1 << 24,
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MP0_ADB400_DCM_EN = 1 << 23,
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CCI400_CK_ONLY_DCM_EN = 1 << 22,
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L2C_IDLE_DCM_EN = 1 << 21,
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CA15U_ADB_DYNAMIC_CG_EN = 1 << 19,
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CA7L_ADB_DYNAMIC_CG_EN = 1 << 18,
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L2C_ADB_DYNAMIC_CG_EN = 1 << 17,
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EMICLK_EMI1_DYNAMIC_CG_EN = 1 << 12,
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INFRACLK_PSYS_DYNAMIC_CG_EN = 1 << 11,
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EMICLK_GPU_DYNAMIC_CG_EN = 1 << 10,
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EMICLK_EMI_DYNAMIC_CG_EN = 1 << 8,
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CCI400_SLV_RW_DCM_EN = 1 << 7,
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CCI400_SLV_DCM_EN = 1 << 5,
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ACLK_PSYS_DYNAMIC_CG_EN = 1 << 3,
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ACLK_GPU_DYNAMIC_CG_EN = 1 << 2,
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ACLK_EMI_DYNAMIC_CG_EN = 1 << 1,
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ACLK_INFRA_DYNAMIC_CG_EN = 1 << 0,
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/* adb400 related */
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ADB400_GRP_DCM_EN = PSYS_ADB400_DCM_EN | GPU_ADB400_DCM_EN |
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EMI1_ADB400_DCM_EN | EMI_ADB400_DCM_EN |
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INFRA_ADB400_DCM_EN | L2C_ADB400_DCM_EN |
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MP0_ADB400_DCM_EN,
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/* cci400 related */
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CCI400_GRP_DCM_EN = CCI400_CK_ONLY_DCM_EN | CCI400_SLV_RW_DCM_EN |
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CCI400_SLV_DCM_EN,
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/* adb clock related */
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ADBCLK_GRP_DCM_EN = CA15U_ADB_DYNAMIC_CG_EN | CA7L_ADB_DYNAMIC_CG_EN |
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L2C_ADB_DYNAMIC_CG_EN,
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/* emi clock related */
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EMICLK_GRP_DCM_EN = EMICLK_EMI1_DYNAMIC_CG_EN |
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EMICLK_GPU_DYNAMIC_CG_EN |
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EMICLK_EMI_DYNAMIC_CG_EN,
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/* bus clock related */
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ACLK_GRP_DCM_EN = ACLK_PSYS_DYNAMIC_CG_EN | ACLK_GPU_DYNAMIC_CG_EN |
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ACLK_EMI_DYNAMIC_CG_EN | ACLK_INFRA_DYNAMIC_CG_EN,
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};
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#endif /* MCUCFG_H */
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+140
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/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT8173_DEF_H
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#define MT8173_DEF_H
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#if RESET_TO_BL31
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#error "MT8173 is incompatible with RESET_TO_BL31!"
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#endif
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#define MT8173_PRIMARY_CPU 0x0
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/* Register base address */
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#define IO_PHYS (0x10000000)
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define SRAMROM_SEC_BASE (IO_PHYS + 0x1800)
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#define PERI_CON_BASE (IO_PHYS + 0x3000)
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#define GPIO_BASE (IO_PHYS + 0x5000)
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#define SPM_BASE (IO_PHYS + 0x6000)
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#define RGU_BASE (IO_PHYS + 0x7000)
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#define PMIC_WRAP_BASE (IO_PHYS + 0xD000)
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#define DEVAPC0_BASE (IO_PHYS + 0xE000)
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#define MCUCFG_BASE (IO_PHYS + 0x200000)
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#define APMIXED_BASE (IO_PHYS + 0x209000)
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#define TRNG_BASE (IO_PHYS + 0x20F000)
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#define CRYPT_BASE (IO_PHYS + 0x210000)
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#define MT_GIC_BASE (IO_PHYS + 0x220000)
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#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
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/* Aggregate of all devices in the first GB */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x400000
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#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
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#define MTK_DEV_RNG1_SIZE 0x4000000
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/* SRAMROM related registers */
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#define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4)
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#define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8)
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/* DEVAPC0 related registers */
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#define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500)
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#define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define MT8173_UART0_BASE (IO_PHYS + 0x01002000)
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#define MT8173_UART1_BASE (IO_PHYS + 0x01003000)
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#define MT8173_UART2_BASE (IO_PHYS + 0x01004000)
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#define MT8173_UART3_BASE (IO_PHYS + 0x01005000)
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#define MT8173_BAUDRATE (115200)
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#define MT8173_UART_CLOCK (26000000)
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE (MT_GIC_BASE + 0x1000)
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#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
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#define BASE_GICR_BASE 0 /* no GICR in GIC-400 */
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#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
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#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
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#define INT_POL_CTL0 0x10200620
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#define GIC_PRIVATE_SIGNALS (32)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
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/* FIQ platform related define */
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#define MT_IRQ_SEC_SGI_0 8
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#define MT_IRQ_SEC_SGI_1 9
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#define MT_IRQ_SEC_SGI_2 10
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#define MT_IRQ_SEC_SGI_3 11
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#define MT_IRQ_SEC_SGI_4 12
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#define MT_IRQ_SEC_SGI_5 13
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#define MT_IRQ_SEC_SGI_6 14
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#define MT_IRQ_SEC_SGI_7 15
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/*
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* Macros for local power states in MTK platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define MTK_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define MTK_LOCAL_STATE_RET 1
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/* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains
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*/
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#define MTK_LOCAL_STATE_OFF 2
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#if PSCI_EXTENDED_STATE_ID
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define MTK_LOCAL_PSTATE_WIDTH 4
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#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1)
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/* Macros to construct the composite power state */
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/* Make composite power state parameter till power level 0 */
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#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
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#else
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#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#endif /* __PSCI_EXTENDED_STATE_ID__ */
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/* Make composite power state parameter till power level 1 */
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#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \
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mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/* Make composite power state parameter till power level 2 */
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#define mtk_make_pwrstate_lvl2( \
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lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \
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mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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#endif /* MT8173_DEF_H */
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+78
@@ -0,0 +1,78 @@
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/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <mt8173_def.h>
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.section .rodata.gic_reg_name, "aS"
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ---------------------------------------------
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* The below macro prints out relevant GIC and
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* CCI registers whenever an unhandled exception
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* is taken in BL3-1.
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* Clobbers: x0 - x10, x16, x17, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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mov_imm x16, BASE_GICD_BASE
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mov_imm x17, BASE_GICC_BASE
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/* Load the gicc reg list to x6 */
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adr x6, gicc_regs
|
||||
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
|
||||
ldr w8, [x17, #GICC_HPPIR]
|
||||
ldr w9, [x17, #GICC_AHPPIR]
|
||||
ldr w10, [x17, #GICC_CTLR]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
|
||||
/* Print the GICD_ISPENDR regs */
|
||||
add x7, x16, #GICD_ISPENDR
|
||||
adr x4, gicd_pend_reg
|
||||
bl asm_print_str
|
||||
gicd_ispendr_loop:
|
||||
sub x4, x7, x16
|
||||
cmp x4, #0x280
|
||||
b.eq exit_print_gic_regs
|
||||
bl asm_print_hex
|
||||
|
||||
adr x4, spacer
|
||||
bl asm_print_str
|
||||
|
||||
ldr x4, [x7], #8
|
||||
bl asm_print_hex
|
||||
|
||||
adr x4, newline
|
||||
bl asm_print_str
|
||||
b gicd_ispendr_loop
|
||||
exit_print_gic_regs:
|
||||
|
||||
adr x6, cci_iface_regs
|
||||
/* Store in x7 the base address of the first interface */
|
||||
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
||||
PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX))
|
||||
ldr w8, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store in x7 the base address of the second interface */
|
||||
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
||||
PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX))
|
||||
ldr w9, [x7, #SNOOP_CTRL_REG]
|
||||
/* Store to the crash buf and print to console */
|
||||
bl str_in_crash_buf_print
|
||||
.endm
|
||||
+27
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_PRIVATE_H
|
||||
#define PLAT_PRIVATE_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void plat_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long,
|
||||
unsigned long,
|
||||
unsigned long,
|
||||
unsigned long);
|
||||
|
||||
void plat_cci_init(void);
|
||||
void plat_cci_enable(void);
|
||||
void plat_cci_disable(void);
|
||||
|
||||
/* Declarations for plat_topology.c */
|
||||
int mt_setup_topology(void);
|
||||
|
||||
#endif /* PLAT_PRIVATE_H */
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_SIP_CALLS_H
|
||||
#define PLAT_SIP_CALLS_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Plat SiP function constants
|
||||
******************************************************************************/
|
||||
#define MTK_PLAT_SIP_NUM_CALLS 7
|
||||
|
||||
#define MTK_SIP_PWR_ON_MTCMOS 0x82000402
|
||||
#define MTK_SIP_PWR_OFF_MTCMOS 0x82000403
|
||||
#define MTK_SIP_PWR_MTCMOS_SUPPORT 0x82000404
|
||||
#define MTK_SIP_SET_HDCP_KEY_NUM 0x82000405
|
||||
#define MTK_SIP_CLR_HDCP_KEY 0x82000406
|
||||
#define MTK_SIP_SET_HDCP_KEY_EX 0x82000407
|
||||
#define MTK_SIP_SMC_WATCHDOG 0x82003D06
|
||||
|
||||
#endif /* PLAT_SIP_CALLS_H */
|
||||
+141
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <common/interrupt_props.h>
|
||||
#include <drivers/arm/gic_common.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include "mt8173_def.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform binary types for linking
|
||||
******************************************************************************/
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if defined(IMAGE_BL1)
|
||||
#define PLATFORM_STACK_SIZE 0x440
|
||||
#elif defined(IMAGE_BL2)
|
||||
#define PLATFORM_STACK_SIZE 0x400
|
||||
#elif defined(IMAGE_BL31)
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
#elif defined(IMAGE_BL32)
|
||||
#define PLATFORM_STACK_SIZE 0x440
|
||||
#endif
|
||||
|
||||
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
|
||||
|
||||
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
|
||||
#define PLAT_MAX_PWR_LVL U(2)
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
#define PLATFORM_SYSTEM_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER_COUNT U(2)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT U(2)
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER0_CORE_COUNT)
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
|
||||
#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
|
||||
PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
|
||||
#define SOC_CHIP_ID U(0x8173)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform memory map related constants
|
||||
******************************************************************************/
|
||||
/*
|
||||
* MT8173 SRAM memory layout
|
||||
* 0x100000 +-------------------+
|
||||
* | shared mem (4KB) |
|
||||
* 0x101000 +-------------------+
|
||||
* | |
|
||||
* | BL3-1 (124KB) |
|
||||
* | |
|
||||
* 0x120000 +-------------------+
|
||||
* | reserved (64KB) |
|
||||
* 0x130000 +-------------------+
|
||||
*/
|
||||
/* TF txet, ro, rw, xlat table, coherent memory ... etc.
|
||||
* Size: release: 128KB, debug: 128KB
|
||||
*/
|
||||
#define TZRAM_BASE (0x100000)
|
||||
#if DEBUG
|
||||
#define TZRAM_SIZE (0x20000)
|
||||
#else
|
||||
#define TZRAM_SIZE (0x20000)
|
||||
#endif
|
||||
|
||||
/* Reserved: 64KB */
|
||||
#define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE)
|
||||
#define TZRAM2_SIZE (0x10000)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
|
||||
* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#define BL31_BASE (TZRAM_BASE + 0x1000)
|
||||
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
|
||||
#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define MAX_XLAT_TABLES 4
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
******************************************************************************/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
|
||||
#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
|
||||
#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
|
||||
|
||||
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define PLAT_ARM_G0_IRQ_PROPS(grp)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef POWER_TRACER_H
|
||||
#define POWER_TRACER_H
|
||||
|
||||
#define CPU_UP 0
|
||||
#define CPU_DOWN 1
|
||||
#define CPU_SUSPEND 2
|
||||
#define CLUSTER_UP 3
|
||||
#define CLUSTER_DOWN 4
|
||||
#define CLUSTER_SUSPEND 5
|
||||
|
||||
void trace_power_flow(unsigned long mpidr, unsigned char mode);
|
||||
|
||||
#endif /* POWER_TRACER_H */
|
||||
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SCU_H
|
||||
#define SCU_H
|
||||
|
||||
void disable_scu(unsigned long mpidr);
|
||||
void enable_scu(unsigned long mpidr);
|
||||
|
||||
#endif /* SCU_H */
|
||||
Reference in New Issue
Block a user