GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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#include <mcucfg.h>
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#include <mt8173_def.h>
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#include <mt_cpuxgpt.h> /* generic_timer_backup() */
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#include <plat_private.h>
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#include <power_tracer.h>
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#include <rtc.h>
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#include <scu.h>
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#include <spm_hotplug.h>
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#include <spm_mcdi.h>
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#include <spm_suspend.h>
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#include <wdt.h>
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#define MTK_PWR_LVL0 0
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#define MTK_PWR_LVL1 1
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#define MTK_PWR_LVL2 2
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/* Macros to read the MTK power domain state */
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#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
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#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
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#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
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(state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
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#if PSCI_EXTENDED_STATE_ID
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/*
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* The table storing the valid idle power states. Ensure that the
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* array entries are populated in ascending order of state-id to
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* enable us to use binary search during power state validation.
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* The table must be terminated by a NULL entry.
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*/
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const unsigned int mtk_pm_idle_states[] = {
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/* State-id - 0x001 */
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mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN,
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MTK_LOCAL_STATE_RET, MTK_PWR_LVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x002 */
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mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_RUN,
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MTK_LOCAL_STATE_OFF, MTK_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x022 */
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mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_RUN, MTK_LOCAL_STATE_OFF,
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MTK_LOCAL_STATE_OFF, MTK_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
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#if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1
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/* State-id - 0x222 */
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mtk_make_pwrstate_lvl2(MTK_LOCAL_STATE_OFF, MTK_LOCAL_STATE_OFF,
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MTK_LOCAL_STATE_OFF, MTK_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
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#endif
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0,
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};
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#endif
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struct core_context {
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unsigned long timer_data[8];
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unsigned int count;
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unsigned int rst;
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unsigned int abt;
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unsigned int brk;
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};
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struct cluster_context {
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struct core_context core[PLATFORM_MAX_CPUS_PER_CLUSTER];
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};
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/*
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* Top level structure to hold the complete context of a multi cluster system
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*/
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struct system_context {
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struct cluster_context cluster[PLATFORM_CLUSTER_COUNT];
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};
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/*
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* Top level structure which encapsulates the context of the entire system
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*/
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static struct system_context dormant_data[1];
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static inline struct cluster_context *system_cluster(
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struct system_context *system,
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uint32_t clusterid)
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{
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return &system->cluster[clusterid];
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}
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static inline struct core_context *cluster_core(struct cluster_context *cluster,
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uint32_t cpuid)
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{
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return &cluster->core[cpuid];
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}
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static struct cluster_context *get_cluster_data(unsigned long mpidr)
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{
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uint32_t clusterid;
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clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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return system_cluster(dormant_data, clusterid);
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}
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static struct core_context *get_core_data(unsigned long mpidr)
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{
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struct cluster_context *cluster;
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uint32_t cpuid;
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cluster = get_cluster_data(mpidr);
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cpuid = mpidr & MPIDR_CPU_MASK;
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return cluster_core(cluster, cpuid);
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}
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static void mt_save_generic_timer(unsigned long *container)
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{
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uint64_t ctl;
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uint64_t val;
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__asm__ volatile("mrs %x0, cntkctl_el1\n\t"
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"mrs %x1, cntp_cval_el0\n\t"
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"stp %x0, %x1, [%2, #0]"
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: "=&r" (ctl), "=&r" (val)
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: "r" (container)
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: "memory");
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__asm__ volatile("mrs %x0, cntp_tval_el0\n\t"
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"mrs %x1, cntp_ctl_el0\n\t"
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"stp %x0, %x1, [%2, #16]"
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: "=&r" (val), "=&r" (ctl)
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: "r" (container)
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: "memory");
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__asm__ volatile("mrs %x0, cntv_tval_el0\n\t"
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"mrs %x1, cntv_ctl_el0\n\t"
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"stp %x0, %x1, [%2, #32]"
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: "=&r" (val), "=&r" (ctl)
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: "r" (container)
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: "memory");
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}
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static void mt_restore_generic_timer(unsigned long *container)
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{
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uint64_t ctl;
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uint64_t val;
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__asm__ volatile("ldp %x0, %x1, [%2, #0]\n\t"
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"msr cntkctl_el1, %x0\n\t"
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"msr cntp_cval_el0, %x1"
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: "=&r" (ctl), "=&r" (val)
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: "r" (container)
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: "memory");
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__asm__ volatile("ldp %x0, %x1, [%2, #16]\n\t"
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"msr cntp_tval_el0, %x0\n\t"
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"msr cntp_ctl_el0, %x1"
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: "=&r" (val), "=&r" (ctl)
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: "r" (container)
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: "memory");
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__asm__ volatile("ldp %x0, %x1, [%2, #32]\n\t"
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"msr cntv_tval_el0, %x0\n\t"
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"msr cntv_ctl_el0, %x1"
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: "=&r" (val), "=&r" (ctl)
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: "r" (container)
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: "memory");
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}
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static inline uint64_t read_cntpctl(void)
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{
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uint64_t cntpctl;
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__asm__ volatile("mrs %x0, cntp_ctl_el0"
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: "=r" (cntpctl) : : "memory");
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return cntpctl;
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}
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static inline void write_cntpctl(uint64_t cntpctl)
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{
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__asm__ volatile("msr cntp_ctl_el0, %x0" : : "r"(cntpctl));
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}
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static void stop_generic_timer(void)
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{
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/*
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* Disable the timer and mask the irq to prevent
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* suprious interrupts on this cpu interface. It
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* will bite us when we come back if we don't. It
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* will be replayed on the inbound cluster.
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*/
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uint64_t cntpctl = read_cntpctl();
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write_cntpctl(clr_cntp_ctl_enable(cntpctl));
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}
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static void mt_cpu_save(unsigned long mpidr)
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{
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struct core_context *core;
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core = get_core_data(mpidr);
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mt_save_generic_timer(core->timer_data);
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/* disable timer irq, and upper layer should enable it again. */
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stop_generic_timer();
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}
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static void mt_cpu_restore(unsigned long mpidr)
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{
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struct core_context *core;
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core = get_core_data(mpidr);
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mt_restore_generic_timer(core->timer_data);
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}
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static void mt_platform_save_context(unsigned long mpidr)
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{
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/* mcusys_save_context: */
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mt_cpu_save(mpidr);
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}
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static void mt_platform_restore_context(unsigned long mpidr)
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{
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/* mcusys_restore_context: */
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mt_cpu_restore(mpidr);
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}
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static void plat_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t scr;
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scr = read_scr_el3();
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write_scr_el3(scr | SCR_IRQ_BIT);
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isb();
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dsb();
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wfi();
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write_scr_el3(scr);
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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* on. The level and mpidr determine the affinity instance.
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******************************************************************************/
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static uintptr_t secure_entrypoint;
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static int plat_power_domain_on(unsigned long mpidr)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned long cpu_id;
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unsigned long cluster_id;
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uintptr_t rv;
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cpu_id = mpidr & MPIDR_CPU_MASK;
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cluster_id = mpidr & MPIDR_CLUSTER_MASK;
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if (cluster_id)
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rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
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else
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rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
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mmio_write_32(rv, secure_entrypoint);
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INFO("mt_on[%ld:%ld], entry %x\n",
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cluster_id, cpu_id, mmio_read_32(rv));
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spm_hotplug_on(mpidr);
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return rc;
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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* off. The level and mpidr determine the affinity instance. The 'state' arg.
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* allows the platform to decide whether the cluster is being turned off and
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* take apt actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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static void plat_power_domain_off(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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/* Prevent interrupts from spuriously waking up this cpu */
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gicv2_cpuif_disable();
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spm_hotplug_off(mpidr);
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trace_power_flow(mpidr, CPU_DOWN);
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Disable coherency if this cluster is to be turned off */
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plat_cci_disable();
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trace_power_flow(mpidr, CLUSTER_DOWN);
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}
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be
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* suspended. The level and mpidr determine the affinity instance. The 'state'
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* arg. allows the platform to decide whether the cluster is being turned off
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* and take apt actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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static void plat_power_domain_suspend(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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unsigned long cluster_id;
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unsigned long cpu_id;
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uintptr_t rv;
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cpu_id = mpidr & MPIDR_CPU_MASK;
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cluster_id = mpidr & MPIDR_CLUSTER_MASK;
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if (cluster_id)
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rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
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else
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rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
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mmio_write_32(rv, secure_entrypoint);
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if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) {
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spm_mcdi_prepare_for_off_state(mpidr, MTK_PWR_LVL0);
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF)
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spm_mcdi_prepare_for_off_state(mpidr, MTK_PWR_LVL1);
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}
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mt_platform_save_context(mpidr);
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/* Perform the common cluster specific operations */
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Disable coherency if this cluster is to be turned off */
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plat_cci_disable();
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}
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if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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wdt_suspend();
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disable_scu(mpidr);
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generic_timer_backup();
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spm_system_suspend();
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/* Prevent interrupts from spuriously waking up this cpu */
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gicv2_cpuif_disable();
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}
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance has just been powered
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* on after being turned off earlier. The level and mpidr determine the affinity
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* instance. The 'state' arg. allows the platform to decide whether the cluster
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* was turned off prior to wakeup and do what's necessary to setup it up
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* correctly.
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******************************************************************************/
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void mtk_system_pwr_domain_resume(void);
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static void plat_power_domain_on_finish(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF);
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if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) &&
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(state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF))
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mtk_system_pwr_domain_resume();
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if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
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plat_cci_enable();
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trace_power_flow(mpidr, CLUSTER_UP);
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}
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if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) &&
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(state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF))
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return;
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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gicv2_pcpu_distif_init();
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trace_power_flow(mpidr, CPU_UP);
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance has just been powered
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* on after having been suspended earlier. The level and mpidr determine the
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* affinity instance.
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******************************************************************************/
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static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET)
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return;
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if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Enable the gic cpu interface */
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plat_arm_gic_init();
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spm_system_suspend_finish();
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enable_scu(mpidr);
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wdt_resume();
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}
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/* Perform the common cluster specific operations */
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Enable coherency if this cluster was off */
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plat_cci_enable();
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}
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mt_platform_restore_context(mpidr);
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if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) {
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spm_mcdi_finish_for_on_state(mpidr, MTK_PWR_LVL0);
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF)
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spm_mcdi_finish_for_on_state(mpidr, MTK_PWR_LVL1);
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}
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gicv2_pcpu_distif_init();
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}
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static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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assert(PLAT_MAX_PWR_LVL >= 2);
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for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
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}
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/*******************************************************************************
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* MTK handlers to shutdown/reboot the system
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||||
******************************************************************************/
|
||||
static void __dead2 plat_system_off(void)
|
||||
{
|
||||
INFO("MTK System Off\n");
|
||||
|
||||
rtc_bbpu_power_down();
|
||||
|
||||
wfi();
|
||||
ERROR("MTK System Off: operation not handled.\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
static void __dead2 plat_system_reset(void)
|
||||
{
|
||||
/* Write the System Configuration Control Register */
|
||||
INFO("MTK System Reset\n");
|
||||
|
||||
wdt_trigger_reset();
|
||||
|
||||
wfi();
|
||||
ERROR("MTK System Reset: operation not handled.\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
#if !PSCI_EXTENDED_STATE_ID
|
||||
static int plat_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
int pstate = psci_get_pstate_type(power_state);
|
||||
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
|
||||
int i;
|
||||
|
||||
assert(req_state);
|
||||
|
||||
if (pwr_lvl > PLAT_MAX_PWR_LVL)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
/* Sanity check the requested state */
|
||||
if (pstate == PSTATE_TYPE_STANDBY) {
|
||||
/*
|
||||
* It's possible to enter standby only on power level 0
|
||||
* Ignore any other power level.
|
||||
*/
|
||||
if (pwr_lvl != 0)
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
req_state->pwr_domain_state[MTK_PWR_LVL0] =
|
||||
MTK_LOCAL_STATE_RET;
|
||||
} else {
|
||||
for (i = 0; i <= pwr_lvl; i++)
|
||||
req_state->pwr_domain_state[i] =
|
||||
MTK_LOCAL_STATE_OFF;
|
||||
}
|
||||
|
||||
/*
|
||||
* We expect the 'state id' to be zero.
|
||||
*/
|
||||
if (psci_get_pstate_id(power_state))
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
#else
|
||||
int plat_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
unsigned int state_id;
|
||||
int i;
|
||||
|
||||
assert(req_state);
|
||||
|
||||
/*
|
||||
* Currently we are using a linear search for finding the matching
|
||||
* entry in the idle power state array. This can be made a binary
|
||||
* search if the number of entries justify the additional complexity.
|
||||
*/
|
||||
for (i = 0; !!mtk_pm_idle_states[i]; i++) {
|
||||
if (power_state == mtk_pm_idle_states[i])
|
||||
break;
|
||||
}
|
||||
|
||||
/* Return error if entry not found in the idle state array */
|
||||
if (!mtk_pm_idle_states[i])
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
|
||||
i = 0;
|
||||
state_id = psci_get_pstate_id(power_state);
|
||||
|
||||
/* Parse the State ID and populate the state info parameter */
|
||||
while (state_id) {
|
||||
req_state->pwr_domain_state[i++] = state_id &
|
||||
MTK_LOCAL_PSTATE_MASK;
|
||||
state_id >>= MTK_LOCAL_PSTATE_WIDTH;
|
||||
}
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
void mtk_system_pwr_domain_resume(void)
|
||||
{
|
||||
console_switch_state(CONSOLE_FLAG_BOOT);
|
||||
|
||||
/* Assert system power domain is available on the platform */
|
||||
assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2);
|
||||
|
||||
plat_arm_gic_init();
|
||||
|
||||
console_switch_state(CONSOLE_FLAG_RUNTIME);
|
||||
}
|
||||
|
||||
static const plat_psci_ops_t plat_plat_pm_ops = {
|
||||
.cpu_standby = plat_cpu_standby,
|
||||
.pwr_domain_on = plat_power_domain_on,
|
||||
.pwr_domain_on_finish = plat_power_domain_on_finish,
|
||||
.pwr_domain_off = plat_power_domain_off,
|
||||
.pwr_domain_suspend = plat_power_domain_suspend,
|
||||
.pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
|
||||
.system_off = plat_system_off,
|
||||
.system_reset = plat_system_reset,
|
||||
.validate_power_state = plat_validate_power_state,
|
||||
.get_sys_suspend_power_state = plat_get_sys_suspend_power_state,
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
*psci_ops = &plat_plat_pm_ops;
|
||||
secure_entrypoint = sec_entrypoint;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The PSCI generic code uses this API to let the platform participate in state
|
||||
* coordination during a power management operation. It compares the platform
|
||||
* specific local power states requested by each cpu for a given power domain
|
||||
* and returns the coordinated target power state that the domain should
|
||||
* enter. A platform assigns a number to a local power state. This default
|
||||
* implementation assumes that the platform assigns these numbers in order of
|
||||
* increasing depth of the power state i.e. for two power states X & Y, if X < Y
|
||||
* then X represents a shallower power state than Y. As a result, the
|
||||
* coordinated target local power state for a power domain will be the minimum
|
||||
* of the requested local power states.
|
||||
*/
|
||||
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
|
||||
const plat_local_state_t *states,
|
||||
unsigned int ncpu)
|
||||
{
|
||||
plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
|
||||
|
||||
assert(ncpu);
|
||||
|
||||
do {
|
||||
temp = *states++;
|
||||
if (temp < target)
|
||||
target = temp;
|
||||
} while (--ncpu);
|
||||
|
||||
return target;
|
||||
}
|
||||
Reference in New Issue
Block a user