GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <cortex_a53.h>
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#include <cortex_a73.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <mcucfg.h>
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#include <spm.h>
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#include <drivers/delay_timer.h>
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#include <mtspmc.h>
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#include "mtspmc_private.h"
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static void set_retention(int cluster, int tick)
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{
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uint64_t cpuectlr;
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if (cluster)
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cpuectlr = read_a73_cpuectlr_el1();
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else
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cpuectlr = read_a53_cpuectlr_el1();
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cpuectlr &= ~0x7ULL;
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cpuectlr |= tick & 0x7;
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if (cluster)
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write_a73_cpuectlr_el1(cpuectlr);
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else
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write_a53_cpuectlr_el1(cpuectlr);
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}
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void spm_enable_cpu_auto_off(int cluster, int cpu)
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{
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uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
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set_retention(cluster, 1);
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mmio_clrbits_32(reg, SW_NO_WAIT_Q);
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}
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void spm_disable_cpu_auto_off(int cluster, int cpu)
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{
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uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
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mmio_setbits_32(reg, SW_NO_WAIT_Q);
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set_retention(cluster, 0);
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}
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void spm_set_cpu_power_off(int cluster, int cpu)
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{
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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}
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void spm_enable_cluster_auto_off(int cluster)
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{
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assert(cluster);
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mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q);
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mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0));
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mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN);
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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}
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void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr)
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{
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uintptr_t reg;
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const uintptr_t mp2_bootreg[] = {
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MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
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MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
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if (cluster) {
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assert(cpu >= 0 && cpu < 4);
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reg = mp2_bootreg[cpu];
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} else {
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reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
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}
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mmio_write_32(reg, bootaddr);
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}
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uintptr_t mcucfg_get_bootaddr(int cluster, int cpu)
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{
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uintptr_t reg;
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const uintptr_t mp2_bootreg[] = {
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MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
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MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
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if (cluster) {
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assert(cpu >= 0 && cpu < 4);
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reg = mp2_bootreg[cpu];
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} else {
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reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
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}
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return mmio_read_32(reg);
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}
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void mcucfg_init_archstate(int cluster, int cpu, int arm64)
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{
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uintptr_t reg;
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int i;
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reg = per_cluster(cluster, MCUCFG_INITARCH);
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i = cluster ? 16 : 12;
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mmio_setbits_32(reg, (arm64 & 1) << (i + cpu));
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}
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/**
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* Return power state of specified subsystem
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*
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* @mask: mask to SPM_PWR_STATUS to query the power state
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* of one subsystem.
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* RETURNS:
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* 0 (the subsys was powered off)
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* 1 (the subsys was powered on)
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*/
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int spm_get_powerstate(uint32_t mask)
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{
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return mmio_read_32(SPM_PWR_STATUS) & mask;
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}
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int spm_get_cluster_powerstate(int cluster)
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{
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uint32_t mask;
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mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP;
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return spm_get_powerstate(mask);
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}
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int spm_get_cpu_powerstate(int cluster, int cpu)
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{
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uint32_t i;
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/*
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* a quick way to specify the mask of cpu[0-3]/cpu[4-7] in PWR_STATUS
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* register which are the BITS[9:12](MP0_CPU0~3) and
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* BITS[16:19](MP1_CPU0~3)
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*/
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i = (cluster) ? 16 : 9;
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i = 1 << (i + cpu);
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return spm_get_powerstate(i);
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}
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int spmc_init(void)
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{
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/* enable SPM register control */
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mmio_write_32(SPM_POWERON_CONFIG_EN,
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PROJECT_CODE | MD_BCLK_CG_EN | BCLK_CG_EN);
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#if SPMC_MODE == 1
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INFO("SPM: enable SPMC mode\n");
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/* 0: SPMC mode 1: Legacy mode */
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mmio_write_32(SPM_BYPASS_SPMC, 0);
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mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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#endif
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mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B);
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mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_CLK_DIS);
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mmio_clrbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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return 0;
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}
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/**
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* Power on a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered on
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* @cpu: the CPU ID of the CPU which to be powered on
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*/
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void spm_poweron_cpu(int cluster, int cpu)
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{
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INFO("spmc: power on core %d.%d\n", cluster, cpu);
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/* STA_POWER_ON */
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/* Start to turn on MP0_CPU0 */
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/* Set PWR_RST_B = 1 */
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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/* Set PWR_ON = 1 */
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPU0_PWR_STA_MASK = 1 */
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while (!spm_get_cpu_powerstate(cluster, cpu))
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;
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/* Finish to turn on MP0_CPU0 */
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INFO("spmc: power on core %d.%d successfully\n", cluster, cpu);
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}
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/**
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* Power off a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered off
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* @cpu: the CPU ID of the CPU which to be powered off
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*/
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void spm_poweroff_cpu(int cluster, int cpu)
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{
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INFO("spmc: power off core %d.%d\n", cluster, cpu);
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/* Start to turn off MP0_CPU0 */
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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/* Set PWR_ON = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPU0_PWR_STA_MASK = 0 */
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while (spm_get_cpu_powerstate(cluster, cpu))
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;
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/* Set PWR_RST_B = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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/* Finish to turn off MP0_CPU0 */
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INFO("spmc: power off core %d.%d successfully\n", cluster, cpu);
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}
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/**
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* Power off a cluster with specified index
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*
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* @cluster: the cluster index which to be powered off
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*/
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void spm_poweroff_cluster(int cluster)
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{
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uint32_t mask;
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uint32_t pwr_rst_ctl;
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INFO("spmc: power off cluster %d\n", cluster);
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/* Start to turn off MP0_CPUTOP */
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/* Set bus protect - step1 : 0 */
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mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
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MP0_CPUTOP_PROT_STEP1_0_MASK;
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mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask);
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while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask)
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;
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_ON_2ND);
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/* SPMC_DORMANT_ENABLE[0]=0 */
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mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN;
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mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask);
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/* Set PWR_ON = 0" */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPUTOP_PWR_STA_MASK = 0 */
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while (spm_get_cluster_powerstate(cluster))
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;
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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if (cluster) {
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pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
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mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
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(pwr_rst_ctl & ~SW_RST_B) | TOPAON_APB_MASK);
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}
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/* CPU_EXT_BUCK_ISO[0]=1 */
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if (cluster)
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mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
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/* Finish to turn off MP0_CPUTOP */
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INFO("spmc: power off cluster %d successfully\n", cluster);
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}
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/**
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* Power on a cluster with specified index
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*
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* @cluster: the cluster index which to be powered on
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*/
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void spm_poweron_cluster(int cluster)
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{
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uint32_t mask;
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uint32_t pwr_rst_ctl;
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INFO("spmc: power on cluster %d\n", cluster);
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/* Start to turn on MP1_CPUTOP */
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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if (cluster) {
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mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B);
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/* CPU_EXT_BUCK_ISO[1]=0 */
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/* Set mp<n>_vproc_ext_off to 0 to release vproc isolation control */
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mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
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mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
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(pwr_rst_ctl | SW_RST_B) & ~TOPAON_APB_MASK);
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}
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_ON_2ND);
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/* Set PWR_RST_B = 1 */
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mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_RST_B);
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/* Set PWR_CLK_DIS = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_CLK_DIS);
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/* Set PWR_ON = 1 */
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mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP1_CPUTOP_PWR_STA_MASK = 1 */
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while (!spm_get_cluster_powerstate(cluster))
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;
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/* Release bus protect - step1 : 0 */
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mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
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MP0_CPUTOP_PROT_STEP1_0_MASK;
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mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask);
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/* Finish to turn on MP1_CPUTOP */
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INFO("spmc: power on cluster %d successfully\n", cluster);
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}
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+42
@@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTSPMC_H
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#define MTSPMC_H
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/*
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* CONFIG_SPMC_MODE: Select CPU power control mode.
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*
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* 0: Legacy
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* Control power flow from SW through SPM register (MP*_PWR_CON).
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* 1: HW
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* Control power flow from SPMC. Most control flow and timing are handled
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* by SPMC.
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*/
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#define SPMC_MODE 1
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int spmc_init(void);
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void spm_poweron_cpu(int cluster, int cpu);
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void spm_poweroff_cpu(int cluster, int cpu);
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void spm_poweroff_cluster(int cluster);
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void spm_poweron_cluster(int cluster);
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int spm_get_cpu_powerstate(int cluster, int cpu);
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int spm_get_cluster_powerstate(int cluster);
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int spm_get_powerstate(uint32_t mask);
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void spm_enable_cpu_auto_off(int cluster, int cpu);
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void spm_disable_cpu_auto_off(int cluster, int cpu);
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void spm_set_cpu_power_off(int cluster, int cpu);
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void spm_enable_cluster_auto_off(int cluster);
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void mcucfg_init_archstate(int cluster, int cpu, int arm64);
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void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
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uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
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#endif /* MTSPMC_H */
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+233
@@ -0,0 +1,233 @@
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/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
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#ifndef MTSPMC_PRIVATE_H
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#define MTSPMC_PRIVATE_H
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/*
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* per_cpu/cluster helper
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||||
*/
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struct per_cpu_reg {
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int cluster_addr;
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int cpu_stride;
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};
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#define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \
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(cpu << reg[cluster].cpu_stride))
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#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
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/* SPMC related registers */
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#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
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||||
/* bit-fields of SPM_POWERON_CONFIG_EN */
|
||||
#define BCLK_CG_EN (1 << 0)
|
||||
#define MD_BCLK_CG_EN (1 << 1)
|
||||
#define PROJECT_CODE (0xb16 << 16)
|
||||
|
||||
#define SPM_PWR_STATUS (SPM_BASE + 0x180)
|
||||
#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
|
||||
|
||||
#define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
|
||||
#define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
|
||||
|
||||
#define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
|
||||
#define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
|
||||
#define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
|
||||
#define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
|
||||
#define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
|
||||
#define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
|
||||
#define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
|
||||
#define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
|
||||
#define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
|
||||
#define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
|
||||
#define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
|
||||
#define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
|
||||
#define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
|
||||
#define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
|
||||
#define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
|
||||
#define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
|
||||
#define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
|
||||
#define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
|
||||
#define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
|
||||
#define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
|
||||
#define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
|
||||
#define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
|
||||
|
||||
#define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
|
||||
/* bit-fields of SPM_CPU_EXT_BUCK_ISO */
|
||||
#define MP0_EXT_BUCK_ISO (1 << 0)
|
||||
#define MP1_EXT_BUCK_ISO (1 << 1)
|
||||
#define MP_EXT_BUCK_ISO (1 << 2)
|
||||
|
||||
/* bit-fields of SPM_PWR_STATUS */
|
||||
#define PWR_STATUS_MD (1 << 0)
|
||||
#define PWR_STATUS_CONN (1 << 1)
|
||||
#define PWR_STATUS_DDRPHY (1 << 2)
|
||||
#define PWR_STATUS_DISP (1 << 3)
|
||||
#define PWR_STATUS_MFG (1 << 4)
|
||||
#define PWR_STATUS_ISP (1 << 5)
|
||||
#define PWR_STATUS_INFRA (1 << 6)
|
||||
#define PWR_STATUS_VDEC (1 << 7)
|
||||
#define PWR_STATUS_MP0_CPUTOP (1 << 8)
|
||||
#define PWR_STATUS_MP0_CPU0 (1 << 9)
|
||||
#define PWR_STATUS_MP0_CPU1 (1 << 10)
|
||||
#define PWR_STATUS_MP0_CPU2 (1 << 11)
|
||||
#define PWR_STATUS_MP0_CPU3 (1 << 12)
|
||||
#define PWR_STATUS_MCUSYS (1 << 14)
|
||||
#define PWR_STATUS_MP1_CPUTOP (1 << 15)
|
||||
#define PWR_STATUS_MP1_CPU0 (1 << 16)
|
||||
#define PWR_STATUS_MP1_CPU1 (1 << 17)
|
||||
#define PWR_STATUS_MP1_CPU2 (1 << 18)
|
||||
#define PWR_STATUS_MP1_CPU3 (1 << 19)
|
||||
#define PWR_STATUS_VEN (1 << 21)
|
||||
#define PWR_STATUS_MFG_ASYNC (1 << 23)
|
||||
#define PWR_STATUS_AUDIO (1 << 24)
|
||||
#define PWR_STATUS_C2K (1 << 28)
|
||||
#define PWR_STATUS_MD_INFRA (1 << 29)
|
||||
|
||||
|
||||
/* bit-fields of SPM_*_PWR_CON */
|
||||
#define PWRCTRL_PWR_RST_B (1 << 0)
|
||||
#define PWRCTRL_PWR_ISO (1 << 1)
|
||||
#define PWRCTRL_PWR_ON (1 << 2)
|
||||
#define PWRCTRL_PWR_ON_2ND (1 << 3)
|
||||
#define PWRCTRL_PWR_CLK_DIS (1 << 4)
|
||||
#define PWRCTRL_PWR_SRAM_CKISO (1 << 5)
|
||||
#define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6)
|
||||
#define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7)
|
||||
#define PWRCTRL_PWR_SRAM_PDN (1 << 8)
|
||||
#define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12)
|
||||
#define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24)
|
||||
#define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28)
|
||||
|
||||
/* per_cpu registers for SPM_MP?_CPU?_PWR_CON */
|
||||
static const struct per_cpu_reg SPM_CPU_PWR[] = {
|
||||
[0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
|
||||
[1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 },
|
||||
};
|
||||
|
||||
/* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */
|
||||
static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
|
||||
[0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
|
||||
[1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON },
|
||||
};
|
||||
|
||||
/* APB Module infracfg_ao */
|
||||
#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250)
|
||||
#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258)
|
||||
#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8)
|
||||
#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC)
|
||||
|
||||
/* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */
|
||||
#define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \
|
||||
(1 << 13)|(1 << 26))
|
||||
#define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \
|
||||
(1 << 15)|(1 << 27))
|
||||
|
||||
/* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */
|
||||
#define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \
|
||||
(1 << 13)|(1 << 26))
|
||||
#define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \
|
||||
(1 << 15)|(1 << 27))
|
||||
|
||||
|
||||
/*
|
||||
* MCU configuration registers
|
||||
*/
|
||||
|
||||
/* bit-fields of MCUCFG_MP?_AXI_CONFIG */
|
||||
#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0)
|
||||
#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1)
|
||||
#define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2)
|
||||
#define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3)
|
||||
#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4)
|
||||
#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5)
|
||||
|
||||
|
||||
#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2])
|
||||
#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3])
|
||||
#define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2])
|
||||
#define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3])
|
||||
|
||||
#define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
|
||||
/* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */
|
||||
#define CPU0_SPARK_VRET_CTRL (0x3f << 0)
|
||||
#define CPU1_SPARK_VRET_CTRL (0x3f << 8)
|
||||
#define CPU2_SPARK_VRET_CTRL (0x3f << 16)
|
||||
#define CPU3_SPARK_VRET_CTRL (0x3f << 24)
|
||||
|
||||
/* SPARK control in little cores */
|
||||
#define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
|
||||
#define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
|
||||
#define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
|
||||
#define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
|
||||
/* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */
|
||||
#define SW_SPARK_EN (1 << 0)
|
||||
#define SW_NO_WAIT_Q (1 << 1)
|
||||
|
||||
/* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */
|
||||
#define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
|
||||
#define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8)
|
||||
/* bit-fields of MCUCFG_MP2_PWR_RST_CTL */
|
||||
#define SW_RST_B (1 << 0)
|
||||
#define TOPAON_APB_MASK (1 << 1)
|
||||
|
||||
#define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208)
|
||||
|
||||
#define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290)
|
||||
#define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298)
|
||||
#define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0)
|
||||
#define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8)
|
||||
|
||||
/* SPMC control */
|
||||
#define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
|
||||
#define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0)
|
||||
#define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC)
|
||||
|
||||
/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */
|
||||
static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 },
|
||||
};
|
||||
|
||||
/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */
|
||||
static const struct per_cpu_reg MCUCFG_INITARCH[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 },
|
||||
[1] = { .cluster_addr = MCUCFG_MP2_CPUCFG },
|
||||
};
|
||||
|
||||
/* SPARK control in BIG cores */
|
||||
#define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430)
|
||||
#define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434)
|
||||
#define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438)
|
||||
#define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c)
|
||||
#define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440)
|
||||
#define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444)
|
||||
#define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448)
|
||||
#define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c)
|
||||
/* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */
|
||||
#define SW_SPARK_EN (1 << 0)
|
||||
#define SW_NO_WAIT_Q (1 << 1)
|
||||
|
||||
#define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700)
|
||||
/* bit-fields of MCUCFG_MP2_SPARK2LDO */
|
||||
#define SPARK_VRET_CTRL (0x3f << 0)
|
||||
#define CPU0_SPARK_LDO_AMUXSEL (0xf << 6)
|
||||
#define CPU1_SPARK_LDO_AMUXSEL (0xf << 10)
|
||||
#define CPU2_SPARK_LDO_AMUXSEL (0xf << 14)
|
||||
#define CPU3_SPARK_LDO_AMUXSEL (0xf << 18)
|
||||
|
||||
/* per_cpu registers for SPARK */
|
||||
static const struct per_cpu_reg MCUCFG_SPARK[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 },
|
||||
[1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 },
|
||||
};
|
||||
|
||||
/* per_cpu registers for SPARK2LDO */
|
||||
static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL },
|
||||
[1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO },
|
||||
};
|
||||
|
||||
#endif /* MTSPMC_PRIVATE_H */
|
||||
Reference in New Issue
Block a user