GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_H
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#define MCUCFG_H
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#endif /* __ASSEMBLER__ */
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#include <platform_def.h>
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#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
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#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
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#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
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#define MP2_CPUCFG MCUCFG_REG(0x2208)
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#define MP2_CPU0_STANDBYWFE BIT(4)
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#define MP2_CPU1_STANDBYWFE BIT(5)
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#define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
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#define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
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#define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
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#define sw_spark_en BIT(0)
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#define sw_no_wait_for_q_channel BIT(1)
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#define sw_fsm_override BIT(2)
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#define sw_logic_pre1_pdb BIT(3)
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#define sw_logic_pre2_pdb BIT(4)
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#define sw_logic_pdb BIT(5)
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#define sw_iso BIT(6)
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#define sw_sram_sleepb (U(0x3F) << 7)
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#define sw_sram_isointb BIT(13)
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#define sw_clk_dis BIT(14)
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#define sw_ckiso BIT(15)
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#define sw_pd (U(0x3F) << 16)
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#define sw_hot_plug_reset BIT(22)
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#define sw_pwr_on_override_en BIT(23)
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#define sw_pwr_on BIT(24)
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#define sw_coq_dis BIT(25)
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#define logic_pdbo_all_off_ack BIT(26)
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#define logic_pdbo_all_on_ack BIT(27)
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#define logic_pre2_pdbo_all_on_ack BIT(28)
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#define logic_pre1_pdbo_all_on_ack BIT(29)
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#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
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(MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
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#define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
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#define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
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#define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38)
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#define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C)
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#define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30)
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#define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34)
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#define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38)
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#define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C)
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#define cpu_sw_spark_en BIT(0)
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#define cpu_sw_no_wait_for_q_channel BIT(1)
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#define cpu_sw_fsm_override BIT(2)
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#define cpu_sw_logic_pre1_pdb BIT(3)
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#define cpu_sw_logic_pre2_pdb BIT(4)
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#define cpu_sw_logic_pdb BIT(5)
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#define cpu_sw_iso BIT(6)
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#define cpu_sw_sram_sleepb BIT(7)
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#define cpu_sw_sram_isointb BIT(8)
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#define cpu_sw_clk_dis BIT(9)
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#define cpu_sw_ckiso BIT(10)
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#define cpu_sw_pd (U(0x1F) << 11)
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#define cpu_sw_hot_plug_reset BIT(16)
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#define cpu_sw_powr_on_override_en BIT(17)
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#define cpu_sw_pwr_on BIT(18)
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#define cpu_spark2ldo_allswoff BIT(19)
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#define cpu_pdbo_all_on_ack BIT(20)
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#define cpu_pre2_pdbo_allon_ack BIT(21)
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#define cpu_pre1_pdbo_allon_ack BIT(22)
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/* CPC related registers */
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#define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714)
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#define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804)
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#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
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#define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818)
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#define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c)
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#define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824)
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#define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8)
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#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac)
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#define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04)
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#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c)
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#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10)
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#define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14)
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#define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20)
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#define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70)
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#define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74)
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#define SPARK2LDO MCUCFG_REG(0x2700)
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/* APB Module mcucfg */
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#define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000)
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#define MP0_AXI_CONFIG MCUCFG_REG(0x02C)
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#define MP0_MISC_CONFIG0 MCUCFG_REG(0x030)
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#define MP0_MISC_CONFIG1 MCUCFG_REG(0x034)
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#define MP0_MISC_CONFIG2 MCUCFG_REG(0x038)
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#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8))
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#define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C)
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#define MP0_MISC_CONFIG9 MCUCFG_REG(0x054)
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#define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064)
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#define MP0_RW_RSVD0 MCUCFG_REG(0x06C)
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#define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200)
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#define MP1_AXI_CONFIG MCUCFG_REG(0x22C)
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#define MP1_MISC_CONFIG0 MCUCFG_REG(0x230)
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#define MP1_MISC_CONFIG1 MCUCFG_REG(0x234)
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#define MP1_MISC_CONFIG2 MCUCFG_REG(0x238)
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#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8))
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#define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C)
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#define MP1_MISC_CONFIG9 MCUCFG_REG(0x254)
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#define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264)
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#define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740)
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#define SYNC_DCM_CONFIG MCUCFG_REG(0x744)
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#define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0)
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#define MP0_SPMC MCUCFG_REG(0x788)
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#define MP1_SPMC MCUCFG_REG(0x78C)
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#define MP2_AXI_CONFIG MCUCFG_REG(0x220C)
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#define MP2_AXI_CONFIG_ACINACTM BIT(0)
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#define MP2_AXI_CONFIG_AINACTS BIT(4)
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#define MPx_AXI_CONFIG_ACINACTM BIT(4)
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#define MPx_AXI_CONFIG_AINACTS BIT(5)
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#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28)
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#define MP0_CPU0_STANDBYWFE BIT(20)
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#define MP0_CPU1_STANDBYWFE BIT(21)
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#define MP0_CPU2_STANDBYWFE BIT(22)
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#define MP0_CPU3_STANDBYWFE BIT(23)
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#define MP1_CPU0_STANDBYWFE BIT(20)
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#define MP1_CPU1_STANDBYWFE BIT(21)
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#define MP1_CPU2_STANDBYWFE BIT(22)
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#define MP1_CPU3_STANDBYWFE BIT(23)
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#define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00)
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#define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04)
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#define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08)
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#define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00)
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#define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04)
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#define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08)
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#define MP2_PWR_RST_CTL MCUCFG_REG(0x2008)
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#define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0)
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#define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4)
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#define MP2_COQ MCUCFG_REG(0x22BC)
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#define MP2_COQ_SW_DIS BIT(0)
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#define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400)
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#define MP2_CA15M_MON_L MCUCFG_REG(0x2404)
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#define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430)
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#define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438)
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#define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434)
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#define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C)
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#define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068)
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#define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268)
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#define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C)
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#define MP2_SW_RST_B BIT(0)
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#define MP2_TOPAON_APB_MASK BIT(1)
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#define B_SW_HOT_PLUG_RESET BIT(30)
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#define B_SW_PD_OFFSET 18U
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#define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET)
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#define B_SW_SRAM_SLEEPB_OFFSET 12U
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#define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
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#define B_SW_SRAM_ISOINTB BIT(9)
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#define B_SW_ISO BIT(8)
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#define B_SW_LOGIC_PDB BIT(7)
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#define B_SW_LOGIC_PRE2_PDB BIT(6)
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#define B_SW_LOGIC_PRE1_PDB BIT(5)
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#define B_SW_FSM_OVERRIDE BIT(4)
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#define B_SW_PWR_ON BIT(3)
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#define B_SW_PWR_ON_OVERRIDE_EN BIT(2)
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#define B_FSM_STATE_OUT_OFFSET (6U)
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#define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET)
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#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5)
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#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4)
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#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3)
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#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2)
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#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET)
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#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET)
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#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET)
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#ifndef __ASSEMBLER__
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/* cpu boot mode */
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enum {
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MP0_CPUCFG_64BIT_SHIFT = 12U,
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MP1_CPUCFG_64BIT_SHIFT = 28U,
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MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
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MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
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};
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enum {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum {
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MP1_AINACTS_SHIFT = 4U,
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MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
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};
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enum {
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MP1_SW_CG_GEN_SHIFT = 12U,
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MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
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};
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enum {
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MP1_L2RSTDISABLE_SHIFT = 14U,
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MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
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};
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#endif /* __ASSEMBLER__ */
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#endif /* MCUCFG_H */
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+12
@@ -0,0 +1,12 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_HELPERS_H__
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#define __PLAT_HELPERS_H__
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unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
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#endif /* __PLAT_HELPERS_H__ */
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+38
@@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <platform_def.h>
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.section .rodata.gic_reg_name, "aS"
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ---------------------------------------------
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* The below macro prints out relevant GIC
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* registers whenever an unhandled exception
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* is taken in BL31.
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* Clobbers: x0 - x10, x26, x27, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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/* To-do: GIC owner */
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/* To-do: CCI owner */
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.endm
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#endif /* PLAT_MACROS_S */
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+48
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MTK_LPM_H
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#define PLAT_MTK_LPM_H
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#include <lib/psci/psci.h>
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#include <lib/utils_def.h>
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#define MT_IRQ_REMAIN_MAX U(32)
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#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
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struct mt_irqremain {
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unsigned int count;
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unsigned int irqs[MT_IRQ_REMAIN_MAX];
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unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
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unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
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};
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#define PLAT_RC_STATUS_READY BIT(0)
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#define PLAT_RC_STATUS_FEATURE_EN BIT(1)
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#define PLAT_RC_STATUS_UART_NONSLEEP BIT(31)
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struct mt_lpm_tz {
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int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
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int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
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int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
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int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
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int (*pwr_cluster_on)(unsigned int cpu,
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const psci_power_state_t *state);
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int (*pwr_cluster_dwn)(unsigned int cpu,
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const psci_power_state_t *state);
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int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
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int (*pwr_mcusys_on_finished)(unsigned int cpu,
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const psci_power_state_t *state);
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int (*pwr_mcusys_dwn)(unsigned int cpu,
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const psci_power_state_t *state);
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};
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const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
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#endif /* PLAT_MTK_LPM_H */
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@@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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||||
*/
|
||||
|
||||
#ifndef PLAT_PM_H
|
||||
#define PLAT_PM_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#define MT_PLAT_PWR_STATE_CPU U(1)
|
||||
#define MT_PLAT_PWR_STATE_CLUSTER U(2)
|
||||
#define MT_PLAT_PWR_STATE_MCUSYS U(3)
|
||||
#define MT_PLAT_PWR_STATE_SUSPEND2IDLE U(8)
|
||||
#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND U(9)
|
||||
|
||||
#define MTK_LOCAL_STATE_RUN U(0)
|
||||
#define MTK_LOCAL_STATE_RET U(1)
|
||||
#define MTK_LOCAL_STATE_OFF U(2)
|
||||
|
||||
#define MTK_AFFLVL_CPU U(0)
|
||||
#define MTK_AFFLVL_CLUSTER U(1)
|
||||
#define MTK_AFFLVL_MCUSYS U(2)
|
||||
#define MTK_AFFLVL_SYSTEM U(3)
|
||||
|
||||
#define IS_CLUSTER_OFF_STATE(s) \
|
||||
is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
|
||||
#define IS_MCUSYS_OFF_STATE(s) \
|
||||
is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
|
||||
#define IS_SYSTEM_SUSPEND_STATE(s) \
|
||||
is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
|
||||
|
||||
#define IS_PLAT_SUSPEND_ID(stateid)\
|
||||
((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) \
|
||||
|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
|
||||
|
||||
#endif /* PLAT_PM_H */
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_PRIVATE_H
|
||||
#define PLAT_PRIVATE_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void plat_configure_mmu_el3(uintptr_t total_base,
|
||||
uintptr_t total_size,
|
||||
uintptr_t ro_start,
|
||||
uintptr_t ro_limit);
|
||||
|
||||
#endif /* PLAT_PRIVATE_H */
|
||||
+15
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_SIP_CALLS_H
|
||||
#define PLAT_SIP_CALLS_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Plat SiP function constants
|
||||
******************************************************************************/
|
||||
#define MTK_PLAT_SIP_NUM_CALLS (4)
|
||||
|
||||
#endif /* PLAT_SIP_CALLS_H */
|
||||
+151
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
|
||||
#define PLAT_PRIMARY_CPU 0x0
|
||||
|
||||
#define MT_GIC_BASE 0x0c000000
|
||||
#define PLAT_MT_CCI_BASE 0x0c500000
|
||||
#define MCUCFG_BASE 0x0c530000
|
||||
|
||||
#define IO_PHYS 0x10000000
|
||||
|
||||
/* Aggregate of all devices for MMU mapping */
|
||||
#define MTK_DEV_RNG0_BASE IO_PHYS
|
||||
#define MTK_DEV_RNG0_SIZE 0x10000000
|
||||
#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000)
|
||||
#define MTK_DEV_RNG1_SIZE 0x10000000
|
||||
#define MTK_DEV_RNG2_BASE 0x0c000000
|
||||
#define MTK_DEV_RNG2_SIZE 0x600000
|
||||
#define MTK_MCDI_SRAM_BASE 0x11B000
|
||||
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
|
||||
|
||||
#define APUSYS_BASE 0x19000000
|
||||
#define APUSYS_SCTRL_REVISER_BASE 0x19021000
|
||||
#define APUSYS_SCTRL_REVISER_SIZE 0x1000
|
||||
#define APUSYS_APU_S_S_4_BASE 0x190F2000
|
||||
#define APUSYS_APU_S_S_4_SIZE 0x1000
|
||||
#define APUSYS_APC_AO_WRAPPER_BASE 0x190F8000
|
||||
#define APUSYS_APC_AO_WRAPPER_SIZE 0x1000
|
||||
#define APUSYS_NOC_DAPC_AO_BASE 0x190FC000
|
||||
#define APUSYS_NOC_DAPC_AO_SIZE 0x1000
|
||||
|
||||
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
|
||||
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
|
||||
#define GPIO_BASE (IO_PHYS + 0x00005000)
|
||||
#define SPM_BASE (IO_PHYS + 0x00006000)
|
||||
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
|
||||
#define DVFSRC_BASE (IO_PHYS + 0x00012000)
|
||||
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
|
||||
#define DEVAPC_INFRA_AO_BASE (IO_PHYS + 0x00030000)
|
||||
#define DEVAPC_PERI_AO_BASE (IO_PHYS + 0x00034000)
|
||||
#define DEVAPC_PERI_AO2_BASE (IO_PHYS + 0x00038000)
|
||||
#define DEVAPC_PERI_PAR_AO_BASE (IO_PHYS + 0x0003C000)
|
||||
#define EMI_BASE (IO_PHYS + 0x00219000)
|
||||
#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
|
||||
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
|
||||
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
|
||||
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
|
||||
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
|
||||
#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
|
||||
#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
|
||||
#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
|
||||
#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
|
||||
#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
|
||||
#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
|
||||
#define MMSYS_BASE (IO_PHYS + 0x04000000)
|
||||
/*******************************************************************************
|
||||
* UART related constants
|
||||
******************************************************************************/
|
||||
#define UART0_BASE (IO_PHYS + 0x01002000)
|
||||
#define UART1_BASE (IO_PHYS + 0x01003000)
|
||||
|
||||
#define UART_BAUDRATE 115200
|
||||
|
||||
/*******************************************************************************
|
||||
* System counter frequency related constants
|
||||
******************************************************************************/
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS 13000000
|
||||
#define SYS_COUNTER_FREQ_IN_MHZ 13
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC-600 & interrupt handling related constants
|
||||
******************************************************************************/
|
||||
|
||||
/* Base MTK_platform compatible GIC memory map */
|
||||
#define BASE_GICD_BASE MT_GIC_BASE
|
||||
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
|
||||
|
||||
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
|
||||
#define CIRQ_REG_NUM 14
|
||||
#define CIRQ_IRQ_NUM 439
|
||||
#define CIRQ_SPI_START 64
|
||||
#define MD_WDT_IRQ_BIT_ID 110
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform binary types for linking
|
||||
******************************************************************************/
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
|
||||
#define PLAT_MAX_PWR_LVL U(3)
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(9)
|
||||
|
||||
#define PLATFORM_SYSTEM_COUNT U(1)
|
||||
#define PLATFORM_MCUSYS_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
|
||||
|
||||
#define SOC_CHIP_ID U(0x8192)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform memory map related constants
|
||||
******************************************************************************/
|
||||
#define TZRAM_BASE 0x54600000
|
||||
#define TZRAM_SIZE 0x00030000
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
|
||||
* present). BL31_BASE is calculated using the current BL31 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#define BL31_BASE (TZRAM_BASE + 0x1000)
|
||||
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define MAX_XLAT_TABLES 16
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
******************************************************************************/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RTC_H
|
||||
#define RTC_H
|
||||
|
||||
#include <rtc_mt6359p.h>
|
||||
|
||||
#endif /* RTC_H */
|
||||
Reference in New Issue
Block a user