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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/apusys/apupll.c
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/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/spinlock.h>
#include <apupwr_clkctl.h>
#include <apupwr_clkctl_def.h>
#include <mtk_plat_common.h>
#include <platform_def.h>
uint32_t mixed_con0_addr[APUPLL_MAX] = {
APU_PLL4H_PLL1_CON0,
APU_PLL4H_PLL2_CON0,
APU_PLL4H_PLL3_CON0,
APU_PLL4H_PLL4_CON0,
};
uint32_t mixed_con1_addr[APUPLL_MAX] = {
APU_PLL4H_PLL1_CON1,
APU_PLL4H_PLL2_CON1,
APU_PLL4H_PLL3_CON1,
APU_PLL4H_PLL4_CON1,
};
uint32_t mixed_con3_addr[APUPLL_MAX] = {
APU_PLL4H_PLL1_CON3,
APU_PLL4H_PLL2_CON3,
APU_PLL4H_PLL3_CON3,
APU_PLL4H_PLL4_CON3,
};
uint32_t fhctl_dds_addr[APUPLL_MAX] = {
APU_PLL4H_FHCTL0_DDS,
APU_PLL4H_FHCTL1_DDS,
APU_PLL4H_FHCTL2_DDS,
APU_PLL4H_FHCTL3_DDS,
};
uint32_t fhctl_dvfs_addr[APUPLL_MAX] = {
APU_PLL4H_FHCTL0_DVFS,
APU_PLL4H_FHCTL1_DVFS,
APU_PLL4H_FHCTL2_DVFS,
APU_PLL4H_FHCTL3_DVFS,
};
uint32_t fhctl_mon_addr[APUPLL_MAX] = {
APU_PLL4H_FHCTL0_MON,
APU_PLL4H_FHCTL1_MON,
APU_PLL4H_FHCTL2_MON,
APU_PLL4H_FHCTL3_MON,
};
uint32_t fhctl_cfg_addr[APUPLL_MAX] = {
APU_PLL4H_FHCTL0_CFG,
APU_PLL4H_FHCTL1_CFG,
APU_PLL4H_FHCTL2_CFG,
APU_PLL4H_FHCTL3_CFG,
};
static spinlock_t apupll_lock;
static spinlock_t npupll_lock;
static spinlock_t apupll_1_lock;
static spinlock_t apupll_2_lock;
static uint32_t pll_cnt[APUPLL_MAX];
/**
* vd2pllidx() - voltage domain to pll idx.
* @domain: the voltage domain for getting pll index.
*
* Caller will get correspond pll index by different voltage domain.
* pll_idx[0] --> APUPLL (MDLA0/1)
* pll_idx[1] --> NPUPLL (VPU0/1)
* pll_idx[2] --> APUPLL1(CONN)
* pll_idx[3] --> APUPLL2(IOMMU)
* The longer description may have multiple paragraphs.
*
* Context: Any context.
* Return:
* * 0 ~ 3 - return the corresponding pll index
* * -EEXIST - cannot find pll idex of the specific voltage domain
*
*/
static int32_t vd2pllidx(enum dvfs_voltage_domain domain)
{
int32_t ret;
switch (domain) {
case V_VPU0:
case V_VPU1:
ret = NPUPLL;
break;
case V_MDLA0:
case V_MDLA1:
ret = APUPLL;
break;
case V_TOP_IOMMU:
ret = APUPLL2;
break;
case V_APU_CONN:
ret = APUPLL1;
break;
default:
ERROR("%s wrong voltage domain: %d\n", __func__, domain);
ret = -EEXIST; /* non-exist */
break;
}
return ret;
}
/**
* pllidx2name() - return names of specific pll index.
* @pll_idx: input for specific pll index.
*
* Given pll index, this function will return name of it.
*
* Context: Any context.
* Return: Names of pll_idx, if found, otherwise will return "NULL"
*/
static const char *pllidx2name(int32_t pll_idx)
{
static const char *const names[] = {
[APUPLL] = "PLL4H_PLL1",
[NPUPLL] = "PLL4H_PLL2",
[APUPLL1] = "PLL4H_PLL3",
[APUPLL2] = "PLL4H_PLL4",
[APUPLL_MAX] = "NULL",
};
if (pll_idx >= APUPLL_MAX) {
pll_idx = APUPLL_MAX;
}
return names[pll_idx];
}
/**
* _fhctl_mon_done() - poll whether fhctl HW mode is done.
* @pll_idx: input for specific pll index.
* @tar_dds: target dds for fhctl_mon to be.
*
* Given pll index, this function will continue to poll whether fhctl_mon
* has reached the expected value within 80us.
*
* Context: Any context.
* Return:
* * 0 - OK for fhctl_mon == tar_dds
* * -ETIMEDOUT - fhctl_mon not reach tar_dds
*/
static int32_t _fhctl_mon_done(uint32_t pll_idx, unsigned long tar_dds)
{
unsigned long mon_dds;
uint64_t timeout = timeout_init_us(PLL_READY_TIME_20US);
int32_t ret = 0;
tar_dds &= DDS_MASK;
do {
mon_dds = apupwr_readl(fhctl_mon_addr[pll_idx]) & DDS_MASK;
if (mon_dds == tar_dds) {
break;
}
if (timeout_elapsed(timeout)) {
ERROR("%s monitor DDS 0x%08lx != expect 0x%08lx\n",
pllidx2name(pll_idx), mon_dds, tar_dds);
ret = -ETIMEDOUT;
break;
}
} while (mon_dds != tar_dds);
return ret;
}
/**
* _pll_get_postdiv_reg() - return current post dividor of pll_idx
* @pll_idx: input for specific pll index.
*
* Given pll index, this function will return its current post dividor.
*
* Context: Any context.
* Return: post dividor of current pll_idx.
*
*/
static uint32_t _pll_get_postdiv_reg(uint32_t pll_idx)
{
int32_t pll_postdiv_reg = 0;
uint32_t val;
val = apupwr_readl(mixed_con1_addr[pll_idx]);
pll_postdiv_reg = (val >> POSDIV_SHIFT) & POSDIV_MASK;
return pll_postdiv_reg;
}
/**
* _set_postdiv_reg() - set pll_idx's post dividor.
* @pll_idx: Which PLL to enable/disable
* @post_div: the register value of post dividor to be wrtten.
*
* Below are lists of post dividor register value and its meaning:
* [31] APUPLL_SDM_PCW_CHG
* [26:24] APUPLL_POSDIV
* [21:0] APUPLL_SDM_PCW (8bit integer + 14bit fraction)
* expected freq range ----- divider-------post divider in reg:
* >1500M (1500/ 1) -> 1 -> 0(2 to the zero power)
* > 750M (1500/ 2) -> 2 -> 1(2 to the 1st power)
* > 375M (1500/ 4) -> 4 -> 2(2 to the 2nd power)
* > 187.5M (1500/ 8) -> 8 -> 3(2 to the 3rd power)
* > 93.75M (1500/16) -> 16 -> 4(2 to the 4th power)
*
* Context: Any context.
*/
static void _set_postdiv_reg(uint32_t pll_idx, uint32_t post_div)
{
apupwr_clrbits(POSDIV_MASK << POSDIV_SHIFT, mixed_con1_addr[pll_idx]);
apupwr_setbits((post_div & POSDIV_MASK) << POSDIV_SHIFT,
mixed_con1_addr[pll_idx]);
}
/**
* _cal_pll_data() - input freq, calculate correspond post dividor and dds.
* @pd: address of output post dividor.
* @dds: address of output dds.
* @freq: input frequency.
*
* Given freq, this function will calculate correspond post dividor and dds.
*
* Context: Any context.
* Return:
* * 0 - done for calculating post dividor and dds.
*/
static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq)
{
uint32_t vco, postdiv_val = 1, postdiv_reg = 0;
uint32_t pcw_val;
vco = freq;
postdiv_val = 1;
postdiv_reg = 0;
while (vco <= FREQ_VCO_MIN) {
postdiv_val = postdiv_val << 1;
postdiv_reg = postdiv_reg + 1;
vco = vco << 1;
}
pcw_val = vco * (1 << PCW_FRACTIONAL_SHIFT);
pcw_val = pcw_val / FREQ_FIN;
if (postdiv_reg == 0) { /* Fvco * 2 with post_divider = 2 */
pcw_val = pcw_val * 2;
postdiv_val = postdiv_val << 1;
postdiv_reg = postdiv_reg + 1;
} /* Post divider is 1 is not available */
*pd = postdiv_reg;
*dds = pcw_val | RG_PLL_SDM_PCW_CHG;
return 0;
}
/**
* _pll_en() - enable/disable RG_PLL_EN of CON1 for pll[pll_idx]
* @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable.
*
* This funciton will only change RG_PLL_EN of CON1 for pll[pll_idx].
*
* Context: Any context.
*/
static void _pll_en(uint32_t pll_idx, bool on)
{
if (on) {
apupwr_setbits(RG_PLL_EN, mixed_con0_addr[pll_idx]);
} else {
apupwr_clrbits(RG_PLL_EN, mixed_con0_addr[pll_idx]);
}
}
/**
* _pll_pwr() - enable/disable PLL_SDM_PWR_ON of CON3 for pll[pll_idx]
* @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable.
*
* This funciton will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
*
* Context: Any context.
*/
static void _pll_pwr(uint32_t pll_idx, bool on)
{
if (on) {
apupwr_setbits(DA_PLL_SDM_PWR_ON, mixed_con3_addr[pll_idx]);
} else {
apupwr_clrbits(DA_PLL_SDM_PWR_ON, mixed_con3_addr[pll_idx]);
}
}
/**
* _pll_iso() - enable/disable PLL_SDM_ISO_EN of CON3 for pll[pll_idx]
* @pll_idx: Which PLL to enable/disable
* @enable: 1 -> turn on isolation, 0 -> turn off isolation.
*
* This funciton will turn on/off pll isolation by
* changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
*
* Context: Any context.
*/
static void _pll_iso(uint32_t pll_idx, bool enable)
{
if (enable) {
apupwr_setbits(DA_PLL_SDM_ISO_EN, mixed_con3_addr[pll_idx]);
} else {
apupwr_clrbits(DA_PLL_SDM_ISO_EN, mixed_con3_addr[pll_idx]);
}
}
/**
* _pll_switch() - entry point to turn whole PLL on/off
* @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable.
* @fhctl_en: enable or disable fhctl function
*
* This is the entry poing for controlling pll and fhctl funciton on/off.
* Caller can chose only enable pll instead of fhctl function.
*
* Context: Any context.
* Return:
* * 0 - done for enable pll or fhctl as well.
*/
static int32_t _pll_switch(uint32_t pll_idx, bool on, bool fhctl_en)
{
int32_t ret = 0;
if (pll_idx >= APUPLL_MAX) {
ERROR("%s wrong pll_idx: %d\n", __func__, pll_idx);
ret = -EINVAL;
goto err;
}
if (on) {
_pll_pwr(pll_idx, true);
udelay(PLL_CMD_READY_TIME_1US);
_pll_iso(pll_idx, false);
udelay(PLL_CMD_READY_TIME_1US);
_pll_en(pll_idx, true);
udelay(PLL_READY_TIME_20US);
} else {
_pll_en(pll_idx, false);
_pll_iso(pll_idx, true);
_pll_pwr(pll_idx, false);
}
err:
return ret;
}
/**
* apu_pll_enable() - API for smc function to enable/disable pll
* @pll_idx: Which pll to enable/disable.
* @enable: 1 -> enable, 0 -> disable.
* @fhctl_en: enable or disable fhctl function
*
* pll_idx[0] --> APUPLL (MDLA0/1)
* pll_idx[1] --> NPUPLL (VPU0/1)
* pll_idx[2] --> APUPLL1(CONN)
* pll_idx[3] --> APUPLL2(IOMMU)
* The differences between _pll_switch are:
* 1. Atomic update pll reference cnt to protect double enable pll &
* close pll during user is not zero.
*
* Context: Any context.
* Return:
* * 0 - done for enable pll or fhctl as well.
*/
int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en)
{
int32_t ret = 0;
if (pll_idx >= APUPLL_MAX) {
ERROR("%s wrong pll_idx: %d\n", __func__, pll_idx);
ret = -EINVAL;
goto err;
}
if (enable) {
switch (pll_idx) {
case APUPLL:
spin_lock(&apupll_lock);
if (pll_cnt[APUPLL] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
pll_cnt[APUPLL]++;
spin_unlock(&apupll_lock);
break;
case NPUPLL:
spin_lock(&npupll_lock);
if (pll_cnt[NPUPLL] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
pll_cnt[NPUPLL]++;
spin_unlock(&npupll_lock);
break;
case APUPLL1:
spin_lock(&apupll_1_lock);
if (pll_cnt[APUPLL1] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
pll_cnt[APUPLL1]++;
spin_unlock(&apupll_1_lock);
break;
case APUPLL2:
spin_lock(&apupll_2_lock);
if (pll_cnt[APUPLL2] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
pll_cnt[APUPLL2]++;
spin_unlock(&apupll_2_lock);
break;
default:
ERROR("%s invalid pll_idx: %d\n", __func__, pll_idx);
ret = -EINVAL;
break;
}
} else {
switch (pll_idx) {
case APUPLL:
spin_lock(&apupll_lock);
if (pll_cnt[APUPLL]) {
pll_cnt[APUPLL]--;
}
if (pll_cnt[APUPLL] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
spin_unlock(&apupll_lock);
break;
case NPUPLL:
spin_lock(&npupll_lock);
if (pll_cnt[NPUPLL]) {
pll_cnt[NPUPLL]--;
}
if (pll_cnt[NPUPLL] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
spin_unlock(&npupll_lock);
break;
case APUPLL1:
spin_lock(&apupll_1_lock);
if (pll_cnt[APUPLL1]) {
pll_cnt[APUPLL1]--;
}
if (pll_cnt[APUPLL1] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
spin_unlock(&apupll_1_lock);
break;
case APUPLL2:
spin_lock(&apupll_2_lock);
if (pll_cnt[APUPLL2]) {
pll_cnt[APUPLL2]--;
}
if (pll_cnt[APUPLL2] == 0) {
_pll_switch(pll_idx, enable, fhctl_en);
}
spin_unlock(&apupll_2_lock);
break;
default:
ERROR("%s invalid pll_idx: %d\n", __func__, pll_idx);
ret = -EINVAL;
break;
}
}
err:
return ret;
}
/**
* anpu_pll_set_rate() - API for smc function to set rate of voltage domain.
* @domain: Which pll of correspond voltage domain to change rate.
* @mode: which mode to use when set_rate
* @freq: which frequency to set.
*
* For V_VPU0/1, it will only allow 1 of them to modify NPUPLL
* such that there will be no race condition happen.
*
* For V_MDLA0/1, it will only allow 1 of them to modify APUPLL1
* such that there will be no race condition happen.
*
* There are 3 kinds of modes to set pll's rate.
* 1. pure sw mode: (CON0_PCW)
* fhctl function is off and change rate by programming CON1_PCW.
* 2. fhctl sw mode: (FHCTL_SW)
* fhctl function is on and change rate by programming fhctl_dds.
* (post dividor is still need to program CON1_PCW)
* 3. fhctl hw mode: (FHCTL_HW)
* fhctl function is on and change rate by programming fhctl_dvfs.
* (post dividor is still need to program CON1_PCW)
*
* Context: Any context.
* Return:
* * 0 - done for set rate of voltage domain.
*/
int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
enum pll_set_rate_mode mode, int32_t freq)
{
uint32_t pd, old_pd, dds;
int32_t pll_idx, ret = 0;
pll_idx = vd2pllidx(domain);
if (pll_idx < 0) {
ret = pll_idx;
goto err;
}
_cal_pll_data(&pd, &dds, freq / 1000);
INFO("%s %s new post_div=%d, target dds=0x%08x(%dMhz) mode = %d\n",
__func__, pllidx2name(pll_idx), pd, dds, freq / 1000, mode);
/* spin_lock for NPULL, since vpu0/1 share npupll */
if (domain == V_VPU0 || domain == V_VPU1) {
spin_lock(&npupll_lock);
}
/* spin_lock for APUPLL, since mdla0/1 shate apupll */
if (domain == V_MDLA0 || domain == V_MDLA1) {
spin_lock(&apupll_lock);
}
switch (mode) {
case CON0_PCW:
pd = RG_PLL_SDM_PCW_CHG |
(pd & POSDIV_MASK) << POSDIV_SHIFT | dds;
apupwr_writel(pd, mixed_con1_addr[pll_idx]);
udelay(PLL_READY_TIME_20US);
break;
case FHCTL_SW:
/* pll con0 disable */
_pll_en(pll_idx, false);
apupwr_writel(dds, fhctl_dds_addr[pll_idx]);
_set_postdiv_reg(pll_idx, pd);
apupwr_setbits(PLL_TGL_ORG, fhctl_dds_addr[pll_idx]);
udelay(PLL_CMD_READY_TIME_1US);
/* pll con0 enable */
_pll_en(pll_idx, true);
udelay(PLL_READY_TIME_20US);
break;
case FHCTL_HW:
old_pd = _pll_get_postdiv_reg(pll_idx);
if (pd > old_pd) {
_set_postdiv_reg(pll_idx, pd);
apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]);
} else {
apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]);
_set_postdiv_reg(pll_idx, pd);
}
ret = _fhctl_mon_done(pll_idx, dds);
break;
default:
ERROR("%s input wrong mode: %d\n", __func__, mode);
ret = -EINVAL;
break;
}
/* spin_lock for NPULL, since vpu0/1 share npupll */
if (domain == V_VPU0 || domain == V_VPU1) {
spin_unlock(&npupll_lock);
}
/* spin_lock for APUPLL, since mdla0/1 share apupll */
if (domain == V_MDLA0 || domain == V_MDLA1) {
spin_unlock(&apupll_lock);
}
err:
return ret;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/apusys/apupwr_clkctl.c
+341
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@@ -0,0 +1,341 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <apupwr_clkctl.h>
#include <apupwr_clkctl_def.h>
#include <mtk_plat_common.h>
#include <platform_def.h>
/* 8195 use PCW mode to change freq directly */
enum pll_set_rate_mode PLL_MODE = CON0_PCW;
char *buck_domain_str[APUSYS_BUCK_DOMAIN_NUM] = {
"V_VPU0",
"V_VPU1",
"V_MDLA0",
"V_MDLA1",
"V_APU_CONN",
"V_TOP_IOMMU",
"V_VCORE",
};
uint32_t aacc_set[APUSYS_BUCK_DOMAIN_NUM] = {
APU_ACC_CONFG_SET1, APU_ACC_CONFG_SET2,
APU_ACC_CONFG_SET4, APU_ACC_CONFG_SET5,
APU_ACC_CONFG_SET0, APU_ACC_CONFG_SET7
};
uint32_t aacc_clr[APUSYS_BUCK_DOMAIN_NUM] = {
APU_ACC_CONFG_CLR1, APU_ACC_CONFG_CLR2,
APU_ACC_CONFG_CLR4, APU_ACC_CONFG_CLR5,
APU_ACC_CONFG_CLR0, APU_ACC_CONFG_CLR7
};
struct reg_seq {
uint32_t address;
uint32_t val;
};
static const struct reg_seq init_acc_cfg[] = {
{ APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU) },
{ APU_ACC_CONFG_CLR0, BIT(BIT_CGEN_SOC) },
{ APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU_DIV2) },
{ APU_ACC_CONFG_SET7, BIT(BIT_SEL_APU) },
{ APU_ACC_CONFG_CLR7, BIT(BIT_CGEN_SOC) },
{ APU_ACC_CONFG_SET7, BIT(BIT_SEL_APU_DIV2) },
{ APU_ACC_CONFG_SET1, BIT(BIT_SEL_APU) },
{ APU_ACC_CONFG_CLR1, BIT(BIT_CGEN_SOC) },
{ APU_ACC_CONFG_SET1, BIT(BIT_SEL_APU_DIV2) },
{ APU_ACC_CONFG_SET2, BIT(BIT_INVEN_OUT) },
{ APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU) },
{ APU_ACC_CONFG_CLR2, BIT(BIT_CGEN_SOC) },
{ APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU_DIV2) },
{ APU_ACC_CONFG_SET4, BIT(BIT_SEL_APU) },
{ APU_ACC_CONFG_CLR4, BIT(BIT_CGEN_SOC) },
{ APU_ACC_CONFG_SET4, BIT(BIT_SEL_APU_DIV2) },
{ APU_ACC_CONFG_SET5, BIT(BIT_INVEN_OUT) },
{ APU_ACC_CONFG_SET5, BIT(BIT_SEL_APU) },
{ APU_ACC_CONFG_CLR5, BIT(BIT_CGEN_SOC) },
{ APU_ACC_CONFG_SET5, BIT(BIT_SEL_APU_DIV2) },
};
int32_t apupwr_smc_acc_init_all(void)
{
int32_t i;
for (i = 0; i < ARRAY_SIZE(init_acc_cfg); i++) {
apupwr_writel(init_acc_cfg[i].val,
init_acc_cfg[i].address);
}
/* Deault ACC will raise APU_DIV_2 */
apupwr_smc_pll_set_rate(BUCK_VCONN_DOMAIN_DEFAULT_FREQ,
true, V_APU_CONN);
apupwr_smc_pll_set_rate(BUCK_VCONN_DOMAIN_DEFAULT_FREQ,
true, V_TOP_IOMMU);
apupwr_smc_pll_set_rate(BUCK_VVPU_DOMAIN_DEFAULT_FREQ,
true, V_VPU0);
apupwr_smc_pll_set_rate(BUCK_VMDLA_DOMAIN_DEFAULT_FREQ,
true, V_MDLA0);
return 0;
}
void apupwr_smc_acc_top(bool enable)
{
if (enable) {
apupwr_writel(BIT(BIT_CGEN_APU), aacc_set[V_APU_CONN]);
apupwr_writel(BIT(BIT_CGEN_APU), aacc_set[V_TOP_IOMMU]);
} else {
apupwr_writel(BIT(BIT_CGEN_APU), aacc_clr[V_APU_CONN]);
apupwr_writel(BIT(BIT_CGEN_APU), aacc_clr[V_TOP_IOMMU]);
}
}
/*
* acc_clk_set_parent:ACC MUX select
* 0. freq parameters here, only ACC clksrc is valid
* 1. Switch between APUPLL <=> Parking (F26M, PARK)
* 2. Turn on/off CG_F26M, CG_PARK, CG_SOC, but no CG_APU
* 3. Clear APU Div2 while Parking
* 4. Only use clksrc of APUPLL while ACC CG_APU is on
*/
int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain)
{
uint32_t acc_set = 0;
uint32_t acc_clr = 0;
int32_t ret = 0;
if (freq > DVFS_FREQ_ACC_APUPLL) {
ERROR("%s wrong clksrc: %d\n", __func__, freq);
ret = -EIO;
goto err;
}
switch (domain) {
case V_VPU1:
case V_VPU0:
case V_MDLA1:
case V_MDLA0:
case V_APU_CONN:
case V_TOP_IOMMU:
acc_set = aacc_set[domain];
acc_clr = aacc_clr[domain];
break;
default:
ret = -EIO;
break;
}
/* Select park source */
switch (freq) {
case DVFS_FREQ_ACC_PARKING:
/* Select park source */
apupwr_writel(BIT(BIT_SEL_PARK), acc_set);
apupwr_writel(BIT(BIT_SEL_F26M), acc_clr);
/* Enable park cg */
apupwr_writel(BIT(BIT_CGEN_PARK), acc_set);
apupwr_writel(BIT(BIT_CGEN_F26M) | BIT(BIT_CGEN_SOC), acc_clr);
/* Select park path */
apupwr_writel(BIT(BIT_SEL_APU), acc_clr);
/* clear apu div 2 */
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr);
break;
case DVFS_FREQ_ACC_APUPLL:
/* Select park path */
apupwr_writel(BIT(BIT_SEL_APU), acc_set);
/* Clear park cg */
apupwr_writel(BIT(BIT_CGEN_PARK) | BIT(BIT_CGEN_F26M) |
BIT(BIT_CGEN_SOC), acc_clr);
break;
case DVFS_FREQ_ACC_SOC:
/* Select park source */
apupwr_writel(BIT(BIT_SEL_PARK), acc_clr);
apupwr_writel(BIT(BIT_SEL_F26M), acc_clr);
/* Enable park cg */
apupwr_writel(BIT(BIT_CGEN_SOC), acc_set);
apupwr_writel(BIT(BIT_CGEN_F26M) | BIT(BIT_CGEN_PARK), acc_clr);
/* Select park path */
apupwr_writel(BIT(BIT_SEL_APU), acc_clr);
/* clear apu div 2 */
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr);
break;
case DVFS_FREQ_ACC_26M:
case DVFS_FREQ_NOT_SUPPORT:
default:
/* Select park source */
apupwr_writel(BIT(BIT_SEL_F26M), acc_set);
apupwr_writel(BIT(BIT_SEL_PARK), acc_clr);
/* Enable park cg */
apupwr_writel(BIT(BIT_CGEN_F26M), acc_set);
apupwr_writel(BIT(BIT_CGEN_PARK) | BIT(BIT_CGEN_SOC), acc_clr);
/* Select park path */
apupwr_writel(BIT(BIT_SEL_APU), acc_clr);
/* clear apu div 2 */
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr);
ERROR("[APUPWR] %s wrong ACC clksrc : %d, force assign 26M\n",
__func__, freq);
break;
}
err:
return ret;
}
int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain)
{
int32_t ret = 0;
uint32_t acc_set0 = 0, acc_set1 = 0;
if (freq > DVFS_FREQ_MAX) {
ERROR("%s wrong freq: %d\n", __func__, freq);
ret = -EIO;
goto err;
}
/*
* Switch to Parking src
* 1. Need to switch out all ACCs sharing the same apupll
*/
switch (domain) {
case V_MDLA0:
case V_MDLA1:
acc_set0 = APU_ACC_CONFG_SET4;
acc_set1 = APU_ACC_CONFG_SET5;
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
V_MDLA0);
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
V_MDLA1);
break;
case V_VPU0:
case V_VPU1:
acc_set0 = APU_ACC_CONFG_SET1;
acc_set1 = APU_ACC_CONFG_SET2;
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
V_VPU0);
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
V_VPU1);
break;
case V_APU_CONN:
acc_set0 = APU_ACC_CONFG_SET0;
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
V_APU_CONN);
break;
case V_TOP_IOMMU:
acc_set0 = APU_ACC_CONFG_SET7;
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_PARKING,
V_TOP_IOMMU);
break;
default:
ERROR("[APUPWR] %s %d invalid domain (%d)\n",
__func__, __LINE__, domain);
ret = -EIO;
goto err;
}
anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq);
if (div2) {
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set0);
if (acc_set1) {
apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set1);
}
}
/*
* Switch back to APUPLL
* Only switch back to APUPLL while CG_APU on
* And clksrc is not APUPLL
*/
switch (domain) {
case V_VPU0:
case V_VPU1:
if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) &&
!(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) {
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
V_VPU0);
}
if ((apupwr_readl(acc_set1) & BIT(BIT_CGEN_APU)) &&
!(apupwr_readl(acc_set1) & BIT(BIT_SEL_APU))) {
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
V_VPU1);
}
break;
case V_MDLA0:
case V_MDLA1:
if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) &&
!(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) {
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
V_MDLA0);
}
if ((apupwr_readl(acc_set1) & BIT(BIT_CGEN_APU)) &&
!(apupwr_readl(acc_set1) & BIT(BIT_SEL_APU))) {
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
V_MDLA1);
}
break;
case V_APU_CONN:
case V_TOP_IOMMU:
if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) &&
!(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) {
ret = apupwr_smc_acc_set_parent(DVFS_FREQ_ACC_APUPLL,
domain);
}
break;
default:
ERROR("[APUPWR] %s %d invalid domain (%d)\n",
__func__, __LINE__, domain);
ret = -EIO;
break;
}
INFO("[%s][%d] set domain %d to freq %d\n",
__func__, __LINE__, domain, (div2) ? (freq * 2) : freq);
err:
return ret;
}
int32_t apupwr_smc_bulk_pll(bool enable)
{
int32_t ret = 0;
int32_t pll_idx;
if (enable) {
for (pll_idx = APUPLL; pll_idx < APUPLL_MAX; pll_idx++) {
ret = apu_pll_enable(pll_idx, enable, false);
if (ret != 0) {
goto err;
}
}
} else {
for (pll_idx = APUPLL2; pll_idx >= APUPLL; pll_idx--) {
ret = apu_pll_enable(pll_idx, enable, false);
if (ret != 0) {
goto err;
}
}
}
err:
return ret;
}
void apupwr_smc_bus_prot_cg_on(void)
{
apupwr_clrbits(AO_MD32_MNOC_MASK, APU_CSR_DUMMY_0);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/apusys/apupwr_clkctl.h
+23
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@@ -0,0 +1,23 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef APUPWR_CLKCTL_H
#define APUPWR_CLKCTL_H
#include <arch_helpers.h>
#include <apupwr_clkctl_def.h>
int32_t apupwr_smc_acc_init_all(void);
void apupwr_smc_acc_top(bool enable);
int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);
int32_t apupwr_smc_bulk_pll(bool enable);
void apupwr_smc_bus_prot_cg_on(void);
int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain,
enum pll_set_rate_mode mode, int32_t freq);
#endif /* APUPWR_CLKCTL_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/apusys/apupwr_clkctl_def.h
+195
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@@ -0,0 +1,195 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef APUPWR_CLKCTL_DEF_H
#define APUPWR_CLKCTL_DEF_H
#include <lib/mmio.h>
enum dvfs_voltage_domain {
V_VPU0 = 0,
V_VPU1 = 1,
V_MDLA0 = 2,
V_MDLA1 = 3,
V_APU_CONN = 4,
V_TOP_IOMMU = 5,
V_VCORE = 6,
APUSYS_BUCK_DOMAIN_NUM = 7,
};
enum dvfs_freq {
DVFS_FREQ_NOT_SUPPORT = 0,
DVFS_FREQ_ACC_26M = 1,
DVFS_FREQ_ACC_PARKING = 2,
DVFS_FREQ_ACC_SOC = 3,
DVFS_FREQ_ACC_APUPLL = 4,
DVFS_FREQ_00_026000_F = 26000,
DVFS_FREQ_00_208000_F = 208000,
DVFS_FREQ_00_238000_F = 238000,
DVFS_FREQ_00_273000_F = 273000,
DVFS_FREQ_00_312000_F = 312000,
DVFS_FREQ_00_358000_F = 358000,
DVFS_FREQ_00_385000_F = 385000,
DVFS_FREQ_00_499200_F = 499200,
DVFS_FREQ_00_500000_F = 500000,
DVFS_FREQ_00_525000_F = 525000,
DVFS_FREQ_00_546000_F = 546000,
DVFS_FREQ_00_594000_F = 594000,
DVFS_FREQ_00_624000_F = 624000,
DVFS_FREQ_00_688000_F = 688000,
DVFS_FREQ_00_687500_F = 687500,
DVFS_FREQ_00_728000_F = 728000,
DVFS_FREQ_00_800000_F = 800000,
DVFS_FREQ_00_832000_F = 832000,
DVFS_FREQ_00_960000_F = 960000,
DVFS_FREQ_00_1100000_F = 1100000,
};
#define DVFS_FREQ_MAX (DVFS_FREQ_00_1100000_F)
enum pll_set_rate_mode {
CON0_PCW = 0,
FHCTL_SW = 1,
FHCTL_HW = 2,
PLL_SET_RATE_MODE_MAX = 3,
};
enum apupll {
APUPLL = 0,
NPUPLL = 1,
APUPLL1 = 2,
APUPLL2 = 3,
APUPLL_MAX = 4,
};
#define BUCK_VVPU_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_273000_F)
#define BUCK_VMDLA_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_312000_F)
#define BUCK_VCONN_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_208000_F)
#define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
#define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL)
#define apupwr_readl(REG) mmio_read_32((uintptr_t)REG)
#define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL)
#define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL)
#define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \
mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL)
/* PLL and related register */
#define APU_PLL_BASE (APUSYS_APU_PLL_BASE)
#define APU_PLL4H_PLL1_CON0 (APU_PLL_BASE + 0x008)
#define APU_PLL4H_PLL1_CON1 (APU_PLL_BASE + 0x00C)
#define APU_PLL4H_PLL1_CON3 (APU_PLL_BASE + 0x014)
#define APU_PLL4H_PLL2_CON0 (APU_PLL_BASE + 0x018)
#define APU_PLL4H_PLL2_CON1 (APU_PLL_BASE + 0x01C)
#define APU_PLL4H_PLL2_CON3 (APU_PLL_BASE + 0x024)
#define APU_PLL4H_PLL3_CON0 (APU_PLL_BASE + 0x028)
#define APU_PLL4H_PLL3_CON1 (APU_PLL_BASE + 0x02C)
#define APU_PLL4H_PLL3_CON3 (APU_PLL_BASE + 0x034)
#define APU_PLL4H_PLL4_CON0 (APU_PLL_BASE + 0x038)
#define APU_PLL4H_PLL4_CON1 (APU_PLL_BASE + 0x03C)
#define APU_PLL4H_PLL4_CON3 (APU_PLL_BASE + 0x044)
#define APU_PLL4H_FHCTL_HP_EN (APU_PLL_BASE + 0x0E00)
#define APU_PLL4H_FHCTL_UNITSLOPE_EN (APU_PLL_BASE + 0x0E04)
#define APU_PLL4H_FHCTL_CLK_CON (APU_PLL_BASE + 0x0E08)
#define APU_PLL4H_FHCTL_RST_CON (APU_PLL_BASE + 0x0E0C)
#define APU_PLL4H_FHCTL_SLOPE0 (APU_PLL_BASE + 0x0E10)
#define APU_PLL4H_FHCTL_SLOPE1 (APU_PLL_BASE + 0x0E14)
#define APU_PLL4H_FHCTL_DSSC_CFG (APU_PLL_BASE + 0x0E18)
#define APU_PLL4H_FHCTL_DSSC0_CON (APU_PLL_BASE + 0x0E1C)
#define APU_PLL4H_FHCTL_DSSC1_CON (APU_PLL_BASE + 0x0E20)
#define APU_PLL4H_FHCTL_DSSC2_CON (APU_PLL_BASE + 0x0E24)
#define APU_PLL4H_FHCTL_DSSC3_CON (APU_PLL_BASE + 0x0E28)
#define APU_PLL4H_FHCTL_DSSC4_CON (APU_PLL_BASE + 0x0E2C)
#define APU_PLL4H_FHCTL_DSSC5_CON (APU_PLL_BASE + 0x0E30)
#define APU_PLL4H_FHCTL_DSSC6_CON (APU_PLL_BASE + 0x0E34)
#define APU_PLL4H_FHCTL_DSSC7_CON (APU_PLL_BASE + 0x0E38)
#define APU_PLL4H_FHCTL0_CFG (APU_PLL_BASE + 0x0E3C)
#define APU_PLL4H_FHCTL0_UPDNLMT (APU_PLL_BASE + 0x0E40)
#define APU_PLL4H_FHCTL0_DDS (APU_PLL_BASE + 0x0E44)
#define APU_PLL4H_FHCTL0_DVFS (APU_PLL_BASE + 0x0E48)
#define APU_PLL4H_FHCTL0_MON (APU_PLL_BASE + 0x0E4C)
#define APU_PLL4H_FHCTL1_CFG (APU_PLL_BASE + 0x0E50)
#define APU_PLL4H_FHCTL1_UPDNLMT (APU_PLL_BASE + 0x0E54)
#define APU_PLL4H_FHCTL1_DDS (APU_PLL_BASE + 0x0E58)
#define APU_PLL4H_FHCTL1_DVFS (APU_PLL_BASE + 0x0E5C)
#define APU_PLL4H_FHCTL1_MON (APU_PLL_BASE + 0x0E60)
#define APU_PLL4H_FHCTL2_CFG (APU_PLL_BASE + 0x0E64)
#define APU_PLL4H_FHCTL2_UPDNLMT (APU_PLL_BASE + 0x0E68)
#define APU_PLL4H_FHCTL2_DDS (APU_PLL_BASE + 0x0E6C)
#define APU_PLL4H_FHCTL2_DVFS (APU_PLL_BASE + 0x0E70)
#define APU_PLL4H_FHCTL2_MON (APU_PLL_BASE + 0x0E74)
#define APU_PLL4H_FHCTL3_CFG (APU_PLL_BASE + 0x0E78)
#define APU_PLL4H_FHCTL3_UPDNLMT (APU_PLL_BASE + 0x0E7C)
#define APU_PLL4H_FHCTL3_DDS (APU_PLL_BASE + 0x0E80)
#define APU_PLL4H_FHCTL3_DVFS (APU_PLL_BASE + 0x0E84)
#define APU_PLL4H_FHCTL3_MON (APU_PLL_BASE + 0x0E88)
/* PLL4H_PLLx_CON0 */
#define RG_PLL_EN BIT(0)
/* PLL4H_PLLx_CON1 */
#define RG_PLL_SDM_PCW_CHG BIT(31)
#define POSDIV_SHIFT (24U)
#define POSDIV_MASK (0x7)
/* PLL4H_PLLx_CON3 */
#define DA_PLL_SDM_PWR_ON BIT(0)
#define DA_PLL_SDM_ISO_EN BIT(1)
/* FHCTLx_DDS */
#define DDS_MASK GENMASK_32(21, 0)
#define PCW_FRACTIONAL_SHIFT 14U
#define PLL_TGL_ORG BIT(31)
#define PLL_READY_TIME_20US (20U)
#define PLL_CMD_READY_TIME_1US (1U)
#define FREQ_VCO_MIN (1500U) /* 1500MHz*/
#define FREQ_FIN (26U) /* 26M*/
/* ACC and related register */
#define APU_ACC_BASE (APUSYS_APU_ACC_BASE)
#define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000)
#define APU_ACC_CONFG_SET1 (APU_ACC_BASE + 0x004)
#define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008)
#define APU_ACC_CONFG_SET4 (APU_ACC_BASE + 0x010)
#define APU_ACC_CONFG_SET5 (APU_ACC_BASE + 0x014)
#define APU_ACC_CONFG_SET7 (APU_ACC_BASE + 0x01C)
#define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040)
#define APU_ACC_CONFG_CLR1 (APU_ACC_BASE + 0x044)
#define APU_ACC_CONFG_CLR2 (APU_ACC_BASE + 0x048)
#define APU_ACC_CONFG_CLR4 (APU_ACC_BASE + 0x050)
#define APU_ACC_CONFG_CLR5 (APU_ACC_BASE + 0x054)
#define APU_ACC_CONFG_CLR7 (APU_ACC_BASE + 0x05C)
#define APU_ACC_FM_CONFG_SET (APU_ACC_BASE + 0x0C0)
#define APU_ACC_FM_CONFG_CLR (APU_ACC_BASE + 0x0C4)
#define APU_ACC_FM_SEL (APU_ACC_BASE + 0x0C8)
#define APU_ACC_FM_CNT (APU_ACC_BASE + 0x0CC)
/* APU AO control */
#define APU_AO_CTRL_BASE (APUSYS_APU_S_S_4_BASE)
#define APU_CSR_DUMMY_0 (APU_AO_CTRL_BASE + 0x24)
#define AO_MD32_MNOC_MASK (BIT(1) | BIT(0))
#define BIT_CGEN_F26M (0)
#define BIT_CGEN_PARK (1)
#define BIT_CGEN_SOC (2)
#define BIT_CGEN_APU (3)
#define BIT_CGEN_OUT (4)
#define BIT_SEL_PARK (8)
#define BIT_SEL_F26M (9)
#define BIT_SEL_APU_DIV2 (10)
#define BIT_SEL_APU (11)
#define BIT_SEL_PARK_SRC_OUT (12)
#define BIT_INVEN_OUT (15)
#endif /* APUPWR_CLKCTL_DEF_H*/
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c
+83
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@@ -0,0 +1,83 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <apupwr_clkctl.h>
#include <mtk_apusys.h>
#include <plat/common/platform.h>
int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
uint32_t *ret1)
{
int32_t ret = 0L;
uint32_t request_ops;
request_ops = (uint32_t)x1;
switch (request_ops) {
case MTK_SIP_APU_START_MCU:
/* setup addr[33:32] in reviser */
mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
mmio_write_32(REVISER_USDRFW_CTXT, 0U);
/* setup secure sideband */
mmio_write_32(AO_SEC_FW,
(SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
(0U << SEC_FW_DOMAIN_SHIFT));
/* setup boot address */
mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
/* setup pre-define region */
mmio_write_32(AO_MD32_PRE_DEFINE,
(PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
/* release runstall */
mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
INFO("[APUSYS] rev(0x%08x,0x%08x)\n",
mmio_read_32(REVISER_SECUREFW_CTXT),
mmio_read_32(REVISER_USDRFW_CTXT));
INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n",
mmio_read_32(AO_SEC_FW),
mmio_read_32(AO_SEC_USR_FW),
mmio_read_32(AO_MD32_BOOT_CTRL),
mmio_read_32(AO_MD32_PRE_DEFINE),
mmio_read_32(AO_MD32_SYS_CTRL));
break;
case MTK_SIP_APU_STOP_MCU:
/* hold runstall */
mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
mmio_read_32(AO_MD32_BOOT_CTRL),
mmio_read_32(AO_MD32_SYS_CTRL));
break;
case MTK_SIP_APUPWR_BUS_PROT_CG_ON:
apupwr_smc_bus_prot_cg_on();
break;
case MTK_SIP_APUPWR_BULK_PLL:
ret = apupwr_smc_bulk_pll((bool)x2);
break;
case MTK_SIP_APUPWR_ACC_INIT_ALL:
ret = apupwr_smc_acc_init_all();
break;
case MTK_SIP_APUPWR_ACC_TOP:
apupwr_smc_acc_top((bool)x2);
break;
default:
ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
break;
}
return ret;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h
+51
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@@ -0,0 +1,51 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTK_APUSYS_H
#define MTK_APUSYS_H
#include <stdint.h>
/* setup the SMC command ops */
#define MTK_SIP_APU_START_MCU (0x00U)
#define MTK_SIP_APU_STOP_MCU (0x01U)
#define MTK_SIP_APUPWR_BUS_PROT_CG_ON (0x02U)
#define MTK_SIP_APUPWR_BULK_PLL (0x03U)
#define MTK_SIP_APUPWR_ACC_INIT_ALL (0x04U)
#define MTK_SIP_APUPWR_ACC_TOP (0x05U)
/* AO Register */
#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04)
#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08)
#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
#define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14)
#define PRE_DEFINE_CACHE_TCM (0x3U)
#define PRE_DEFINE_CACHE (0x2U)
#define PRE_DEFINE_SHIFT_0G (0U)
#define PRE_DEFINE_SHIFT_1G (2U)
#define PRE_DEFINE_SHIFT_2G (4U)
#define PRE_DEFINE_SHIFT_3G (6U)
#define SEC_FW_NON_SECURE (1U)
#define SEC_FW_SHIFT_NS (4U)
#define SEC_FW_DOMAIN_SHIFT (0U)
#define SEC_USR_FW_NON_SECURE (1U)
#define SEC_USR_FW_SHIFT_NS (4U)
#define SEC_USR_FW_DOMAIN_SHIFT (0U)
#define SYS_CTRL_RUN (0U)
#define SYS_CTRL_STALL (1U)
/* Reviser Register */
#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100)
#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104)
int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
uint32_t *ret1);
#endif /* MTK_APUSYS_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mtk_dcm.h>
#include <mtk_dcm_utils.h>
static void dcm_armcore(bool mode)
{
dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
}
static void dcm_mcusys(bool on)
{
dcm_mp_cpusys_top_adb_dcm(on);
dcm_mp_cpusys_top_apb_dcm(on);
dcm_mp_cpusys_top_cpubiu_dcm(on);
dcm_mp_cpusys_top_misc_dcm(on);
dcm_mp_cpusys_top_mp0_qdcm(on);
dcm_cpccfg_reg_emi_wfifo(on);
dcm_mp_cpusys_top_last_cor_idle_dcm(on);
}
static void dcm_stall(bool on)
{
dcm_mp_cpusys_top_core_stall_dcm(on);
dcm_mp_cpusys_top_fcm_stall_dcm(on);
}
static bool check_dcm_state(void)
{
bool ret = true;
ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
return ret;
}
bool dcm_set_default(void)
{
dcm_armcore(true);
dcm_mcusys(true);
dcm_stall(true);
return check_dcm_state();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTK_DCM_H
#define MTK_DCM_H
#include <stdbool.h>
bool dcm_set_default(void);
#endif /* #ifndef MTK_DCM_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <mtk_dcm_utils.h>
#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
BIT(16) | \
BIT(17) | \
BIT(18) | \
BIT(21))
#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
BIT(16) | \
BIT(17) | \
BIT(18))
#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
BIT(16) | \
BIT(17) | \
BIT(18) | \
BIT(21))
#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
BIT(16) | \
BIT(17) | \
BIT(18))
#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
(0x0 << 16) | \
(0x0 << 17) | \
(0x0 << 18) | \
(0x0 << 21))
#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
(0x0 << 16) | \
(0x0 << 17) | \
(0x0 << 18))
bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
(unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
return ret;
}
void dcm_mp_cpusys_top_adb_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
}
}
#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
(unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
return ret;
}
void dcm_mp_cpusys_top_apb_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
MP_CPUSYS_TOP_APB_DCM_REG0_ON);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
MP_CPUSYS_TOP_APB_DCM_REG1_ON);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
MP_CPUSYS_TOP_APB_DCM_REG2_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
}
}
#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | \
BIT(24) | \
BIT(25))
#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | \
BIT(24) | \
BIT(25))
#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \
(0x0 << 24) | \
(0x0 << 25))
bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_core_stall_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCSIC_DCM0) &
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0,
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0,
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(24) | \
BIT(25))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(24) | \
BIT(25))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 24) | \
(0x0 << 25))
bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) &
MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(24) | \
BIT(25))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(24) | \
BIT(25))
#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 24) | \
(0x0 << 25))
bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) &
MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
BIT(4))
#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
BIT(4))
#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
(0x0 << 4))
bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
return ret;
}
void dcm_mp_cpusys_top_misc_dcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
}
}
#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
BIT(1) | \
BIT(2) | \
BIT(3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
BIT(1) | \
BIT(2) | \
BIT(3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
(0x0 << 1) | \
(0x0 << 2) | \
(0x0 << 3))
bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
(unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
return ret;
}
void dcm_mp_cpusys_top_mp0_qdcm(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
} else {
/* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
}
}
#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
BIT(1) | \
BIT(2) | \
BIT(3))
#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
BIT(1) | \
BIT(2) | \
BIT(3))
#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
(0x0 << 1) | \
(0x0 << 2) | \
(0x0 << 3))
bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
{
bool ret = true;
ret &= ((mmio_read_32(CPCCFG_REG_EMI_WFIFO) &
CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
(unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
return ret;
}
void dcm_cpccfg_reg_emi_wfifo(bool on)
{
if (on) {
/* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO,
CPCCFG_REG_EMI_WFIFO_REG0_MASK,
CPCCFG_REG_EMI_WFIFO_REG0_ON);
} else {
/* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO,
CPCCFG_REG_EMI_WFIFO_REG0_MASK,
CPCCFG_REG_EMI_WFIFO_REG0_OFF);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h
+59
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTK_DCM_UTILS_H
#define MTK_DCM_UTILS_H
#include <stdbool.h>
#include <mtk_dcm.h>
#include <platform_def.h>
/* Base */
#define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
#define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
/* Register Definition */
#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
#define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
#define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
#define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
#define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
#define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
#define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
#define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
/* MP_CPUSYS_TOP */
bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
void dcm_mp_cpusys_top_adb_dcm(bool on);
bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
void dcm_mp_cpusys_top_apb_dcm(bool on);
bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
void dcm_mp_cpusys_top_core_stall_dcm(bool on);
bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
void dcm_mp_cpusys_top_misc_dcm(bool on);
bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
void dcm_mp_cpusys_top_mp0_qdcm(bool on);
/* CPCCFG_REG */
bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
void dcm_cpccfg_reg_emi_wfifo(bool on);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/dfd/plat_dfd.c
+156
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
static bool dfd_enabled;
static uint64_t dfd_base_addr;
static uint64_t dfd_chain_length;
static uint64_t dfd_cache_dump;
static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
uint64_t cache_dump)
{
mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL);
mmio_write_32(MTK_WDT_INTERVAL, MTK_WDT_INTERVAL_VAL);
mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL);
mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL);
/* Bit[2] = 0 (default=1), disable dfd apb bus protect_en */
mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 0x1 << 2);
/* Bit[0] : enable?mcusys_vproc?external_off?dfd?trigger -> 1 */
mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1);
/* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */
/* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */
sync_writel(DFD_INTERNAL_CTL, 0x5);
/* bit[13]: xreset_b_update_disable */
mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13);
/*
* bit[10:3]: DFD trigger selection mask
* bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger)
* bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger)
* bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger)
* bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger)
* bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger)
*/
mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3);
/*
* bit[9] : rg_rw_dfd_trigger_sel[6] = 1(cpu_eb_sw_dfd_trigger)
* bit[10] : rg_rw_dfd_trigger_sel[7] = 1(cpu_eb_wdt_dfd_trigger)
*/
mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9);
/* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */
mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
/*
* bit[0]: rg_rw_dfd_auto_power_on = 1
* bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us)
* bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us)
*/
mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
/* longest scan chain length */
mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
/* bit[1:0]: rg_rw_dfd_shift_clock_ratio */
mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
/* rg_dfd_test_so_over_64 */
mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
/* DFD3.0 */
mmio_write_32(DFD_TEST_SI_0, 0x0);
mmio_write_32(DFD_TEST_SI_1, 0x0);
mmio_write_32(DFD_TEST_SI_2, 0x0);
mmio_write_32(DFD_TEST_SI_3, 0x0);
/* for iLDO feature */
sync_writel(DFD_POWER_CTL, 0xF9);
/* read offset */
sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL);
/* for DFD-3.0 setup */
sync_writel(DFD_V30_CTL, 0xD);
/* set base address */
mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
mmio_write_32(DFD_O_REG_0, 0);
/* setup global variables for suspend and resume */
dfd_enabled = true;
dfd_base_addr = base_addr;
dfd_chain_length = chain_length;
dfd_cache_dump = cache_dump;
if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL);
sync_writel(DFD_V35_ENABLE, 0x1);
sync_writel(DFD_V35_TAP_NUMBER, 0xB);
sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
/* Cache dump only mode */
sync_writel(DFD_V35_CTL, 0x1);
mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF);
mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL);
mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL);
mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL);
mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL);
if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) {
sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
}
}
dsbsy();
}
void dfd_resume(void)
{
if (dfd_enabled == true) {
dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
}
}
uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
uint64_t arg2, uint64_t arg3)
{
uint64_t ret = 0L;
switch (arg0) {
case PLAT_MTK_DFD_SETUP_MAGIC:
INFO("[%s] DFD setup call from kernel\n", __func__);
dfd_setup(arg1, arg2, arg3);
break;
case PLAT_MTK_DFD_READ_MAGIC:
/* only allow to access DFD register base + 0x200 */
if (arg1 <= 0x200) {
ret = mmio_read_32(MISC1_CFG_BASE + arg1);
}
break;
case PLAT_MTK_DFD_WRITE_MAGIC:
/* only allow to access DFD register base + 0x200 */
if (arg1 <= 0x200) {
sync_writel(MISC1_CFG_BASE + arg1, arg2);
}
break;
default:
ret = MTK_SIP_E_INVALID_PARAM;
break;
}
return ret;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/dfd/plat_dfd.h
+85
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_DFD_H
#define PLAT_DFD_H
#include <arch_helpers.h>
#include <lib/mmio.h>
#include <platform_def.h>
#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \
dsbsy(); \
} while (0)
#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
#define MTK_DRM_LATCH_CTL1 (DRM_BASE + 0x40)
#define MTK_DRM_LATCH_CTL2 (DRM_BASE + 0x44)
#define MTK_WDT_BASE (RGU_BASE)
#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10)
#define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48)
#define MCU_BIU_BASE (MCUCFG_BASE)
#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)
#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34)
#define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c)
#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60)
#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
#define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8)
#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
#define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8)
#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
#define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC)
#define DFD_O_PROTECT_EN_REG (0x10001220)
#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C)
#define DFD_O_SET_BASEADDR_REG (0x10043000)
#define DFD_O_REG_0 (0x10001390)
#define DFD_CACHE_DUMP_ENABLE 1U
#define DFD_PARITY_ERR_TRIGGER 2U
#define DFD_V35_TAP_EN_VAL (0x43FF)
#define DFD_V35_SEQ0_0_VAL (0x63668820)
#define DFD_READ_ADDR_VAL (0x40000008)
#define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF)
#define MTK_WDT_LATCH_CTL2_VAL (0x9507FFFF)
#define MTK_WDT_INTERVAL_VAL (0x6600000A)
#define MTK_DRM_LATCH_CTL2_VAL (0x950600C8)
#define MTK_DRM_LATCH_CTL2_CACHE_VAL (0x95065DC0)
#define MTK_DRM_LATCH_CTL1_VAL (0x95000013)
void dfd_resume(void);
uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
uint64_t arg2, uint64_t arg3);
#endif /* PLAT_DFD_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
+151
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/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <emi_mpu.h>
#if ENABLE_EMI_MPU_SW_LOCK
static unsigned char region_lock_state[EMI_MPU_REGION_NUM];
#endif
#define EMI_MPU_START_MASK (0x00FFFFFF)
#define EMI_MPU_END_MASK (0x00FFFFFF)
#define EMI_MPU_APC_SW_LOCK_MASK (0x00FFFFFF)
#define EMI_MPU_APC_HW_LOCK_MASK (0x80FFFFFF)
static int _emi_mpu_set_protection(unsigned int start, unsigned int end,
unsigned int apc)
{
unsigned int dgroup;
unsigned int region;
region = (start >> 24) & 0xFF;
start &= EMI_MPU_START_MASK;
dgroup = (end >> 24) & 0xFF;
end &= EMI_MPU_END_MASK;
if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) {
WARN("invalid region, domain\n");
return -1;
}
#if ENABLE_EMI_MPU_SW_LOCK
if (region_lock_state[region] == 1) {
WARN("invalid region\n");
return -1;
}
if ((dgroup == 0) && ((apc >> 31) & 0x1)) {
region_lock_state[region] = 1;
}
apc &= EMI_MPU_APC_SW_LOCK_MASK;
#else
apc &= EMI_MPU_APC_HW_LOCK_MASK;
#endif
if ((start >= DRAM_OFFSET) && (end >= start)) {
start -= DRAM_OFFSET;
end -= DRAM_OFFSET;
} else {
WARN("invalid range\n");
return -1;
}
mmio_write_32(EMI_MPU_SA(region), start);
mmio_write_32(EMI_MPU_EA(region), end);
mmio_write_32(EMI_MPU_APC(region, dgroup), apc);
#if defined(SUB_EMI_MPU_BASE)
mmio_write_32(SUB_EMI_MPU_SA(region), start);
mmio_write_32(SUB_EMI_MPU_EA(region), end);
mmio_write_32(SUB_EMI_MPU_APC(region, dgroup), apc);
#endif
return 1;
}
int emi_mpu_set_protection(struct emi_region_info_t *region_info)
{
unsigned int start, end;
int i;
if (region_info->region >= EMI_MPU_REGION_NUM) {
WARN("invalid region\n");
return -1;
}
start = (unsigned int)(region_info->start >> EMI_MPU_ALIGN_BITS) |
(region_info->region << 24);
for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) {
end = (unsigned int)(region_info->end >> EMI_MPU_ALIGN_BITS) |
(i << 24);
_emi_mpu_set_protection(start, end, region_info->apc[i]);
}
return 0;
}
void dump_emi_mpu_regions(void)
{
unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea;
int region, i;
/* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */
for (region = 0; region < 8; ++region) {
for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i)
apc[i] = mmio_read_32(EMI_MPU_APC(region, i));
sa = mmio_read_32(EMI_MPU_SA(region));
ea = mmio_read_32(EMI_MPU_EA(region));
INFO("region %d:\n", region);
INFO("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n",
sa, ea, apc[0], apc[1]);
}
}
void emi_mpu_init(void)
{
struct emi_region_info_t region_info;
/* SCP DRAM */
region_info.start = 0x50000000ULL;
region_info.end = 0x51400000ULL;
region_info.region = 2;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
emi_mpu_set_protection(&region_info);
/* DSP protect address */
region_info.start = 0x60000000ULL; /* dram base addr */
region_info.end = 0x610FFFFFULL;
region_info.region = 3;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION,
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
emi_mpu_set_protection(&region_info);
/* Forbidden All */
region_info.start = 0x40000000ULL; /* dram base addr */
region_info.end = 0x1FFFF0000ULL;
region_info.region = 4;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
emi_mpu_set_protection(&region_info);
dump_emi_mpu_regions();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.h
+98
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/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef EMI_MPU_H
#define EMI_MPU_H
#include <platform_def.h>
#define ENABLE_EMI_MPU_SW_LOCK 1
#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
#define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4))
#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4))
#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100))
#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4))
#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4))
#define EMI_MPU_START (0x000)
#define EMI_MPU_END (0x93C)
#define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000)
#define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004)
#define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100)
#define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200)
#define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4))
#define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4))
#define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300)
#define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100))
#define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800)
#define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4))
#define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900)
#define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4))
#define EMI_MPU_DOMAIN_NUM (16)
#define EMI_MPU_REGION_NUM (32)
#define EMI_MPU_ALIGN_BITS (16)
#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
#define NO_PROTECTION 0
#define SEC_RW 1
#define SEC_RW_NSEC_R 2
#define SEC_RW_NSEC_W 3
#define SEC_R_NSEC_R 4
#define FORBIDDEN 5
#define SEC_R_NSEC_RW 6
#define LOCK 1
#define UNLOCK 0
#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
#if (EMI_MPU_DGROUP_NUM == 1)
#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
do { \
apc_ary[1] = 0; \
apc_ary[0] = \
(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \
(((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \
(((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
(((unsigned int) d1) << 3) | ((unsigned int) d0) | \
((unsigned int) lock << 31); \
} while (0)
#elif (EMI_MPU_DGROUP_NUM == 2)
#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \
d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
do { \
apc_ary[1] = \
(((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | \
(((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) | \
(((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \
(((unsigned int) d9) << 3) | ((unsigned int) d8); \
apc_ary[0] = \
(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \
(((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \
(((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
(((unsigned int) d1) << 3) | ((unsigned int) d0) | \
((unsigned int) lock << 31); \
} while (0)
#endif
struct emi_region_info_t {
unsigned long long start;
unsigned long long end;
unsigned int region;
unsigned int apc[EMI_MPU_DGROUP_NUM];
};
void emi_mpu_init(void);
#endif
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
+44
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/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <mtgpio.h>
#include <platform_def.h>
uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
{
uintptr_t reg_addr = 0U;
struct mt_pin_info gpio_info;
assert(pin < MAX_GPIO_PIN);
gpio_info = mt_pin_infos[pin];
switch (gpio_info.base & 0x0f) {
case 0:
reg_addr = IOCFG_BM_BASE;
break;
case 1:
reg_addr = IOCFG_BL_BASE;
break;
case 2:
reg_addr = IOCFG_BR_BASE;
break;
case 3:
reg_addr = IOCFG_LM_BASE;
break;
case 4:
reg_addr = IOCFG_RB_BASE;
break;
case 5:
reg_addr = IOCFG_TL_BASE;
break;
default:
break;
}
return reg_addr;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
+183
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/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_GPIO_H
#define MT_GPIO_H
#include <mtgpio_common.h>
/* Enumeration for GPIO pin */
typedef enum GPIO_PIN {
GPIO_UNSUPPORTED = -1,
GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
MT_GPIO_BASE_MAX
} GPIO_PIN;
static const struct mt_pin_info mt_pin_infos[] = {
PIN(0, 1, 0, 0x23, 0x60),
PIN(1, 1, 1, 0x23, 0x60),
PIN(2, 1, 2, 0x23, 0x60),
PIN(3, 1, 3, 0x23, 0x60),
PIN(4, 1, 4, 0x23, 0x60),
PIN(5, 1, 5, 0x23, 0x60),
PIN(6, 0, 6, 0x23, 0x70),
PIN(7, 0, 7, 0x23, 0x70),
PIN(8, 0, 13, 0x23, 0x70),
PIN(9, 0, 8, 0x23, 0x70),
PIN(10, 0, 14, 0x23, 0x70),
PIN(11, 0, 9, 0x23, 0x70),
PIN(12, 0, 15, 0x23, 0x70),
PIN(13, 0, 10, 0x23, 0x70),
PIN(14, 0, 16, 0x23, 0x70),
PIN(15, 0, 11, 0x23, 0x70),
PIN(16, 0, 17, 0x23, 0x70),
PIN(17, 0, 12, 0x23, 0x70),
PIN(18, 0, 5, 0x10, 0x60),
PIN(19, 0, 12, 0x10, 0x60),
PIN(20, 0, 11, 0x10, 0x60),
PIN(21, 0, 10, 0x10, 0x60),
PIN(22, 0, 0, 0x10, 0x60),
PIN(23, 0, 1, 0x10, 0x60),
PIN(24, 0, 2, 0x10, 0x60),
PIN(25, 0, 4, 0x10, 0x60),
PIN(26, 0, 3, 0x10, 0x60),
PIN(27, 0, 6, 0x10, 0x60),
PIN(28, 0, 7, 0x10, 0x60),
PIN(29, 0, 8, 0x10, 0x60),
PIN(30, 0, 9, 0x10, 0x60),
PIN(31, 0, 13, 0x21, 0xa0),
PIN(32, 0, 12, 0x21, 0xa0),
PIN(33, 0, 11, 0x21, 0xa0),
PIN(34, 0, 14, 0x21, 0xa0),
PIN(35, 0, 15, 0x21, 0xa0),
PIN(36, 0, 3, 0x21, 0xb0),
PIN(37, 0, 6, 0x21, 0xb0),
PIN(38, 0, 4, 0x21, 0xb0),
PIN(39, 0, 5, 0x21, 0xb0),
PIN(40, 0, 8, 0x21, 0xb0),
PIN(41, 0, 7, 0x21, 0xb0),
PIN(42, 0, 10, 0x21, 0xb0),
PIN(43, 0, 9, 0x21, 0xb0),
PIN(44, 0, 20, 0x21, 0xb0),
PIN(45, 0, 21, 0x21, 0xb0),
PIN(46, 0, 18, 0x21, 0xa0),
PIN(47, 0, 16, 0x21, 0xa0),
PIN(48, 0, 19, 0x21, 0xa0),
PIN(49, 0, 17, 0x21, 0xa0),
PIN(50, 0, 25, 0x21, 0xa0),
PIN(51, 0, 20, 0x21, 0xa0),
PIN(52, 0, 26, 0x21, 0xa0),
PIN(53, 0, 21, 0x21, 0xa0),
PIN(54, 0, 22, 0x21, 0xa0),
PIN(55, 0, 23, 0x21, 0xa0),
PIN(56, 0, 24, 0x21, 0xa0),
PIN(57, 0, 29, 0x21, 0xa0),
PIN(58, 0, 27, 0x21, 0xa0),
PIN(59, 0, 30, 0x21, 0xa0),
PIN(60, 0, 28, 0x21, 0xa0),
PIN(61, 0, 8, 0x21, 0xa0),
PIN(62, 0, 7, 0x21, 0xa0),
PIN(63, 0, 10, 0x21, 0xa0),
PIN(64, 0, 9, 0x21, 0xa0),
PIN(65, 0, 1, 0x21, 0xb0),
PIN(66, 0, 31, 0x21, 0xa0),
PIN(67, 0, 0, 0x21, 0xb0),
PIN(68, 0, 2, 0x21, 0xb0),
PIN(69, 0, 0, 0x21, 0xa0),
PIN(70, 0, 6, 0x21, 0xa0),
PIN(71, 0, 4, 0x21, 0xa0),
PIN(72, 0, 5, 0x21, 0xa0),
PIN(73, 0, 1, 0x21, 0xa0),
PIN(74, 0, 2, 0x21, 0xa0),
PIN(75, 0, 3, 0x21, 0xa0),
PIN(76, 0, 11, 0x21, 0xb0),
PIN(77, 1, 1, 0x22, 0x60),
PIN(78, 1, 2, 0x22, 0x60),
PIN(79, 1, 9, 0x22, 0x60),
PIN(80, 1, 10, 0x22, 0x60),
PIN(81, 1, 11, 0x22, 0x60),
PIN(82, 1, 12, 0x22, 0x60),
PIN(83, 1, 13, 0x22, 0x60),
PIN(84, 1, 14, 0x22, 0x60),
PIN(85, 1, 15, 0x22, 0x60),
PIN(86, 1, 16, 0x22, 0x60),
PIN(87, 1, 3, 0x22, 0x60),
PIN(88, 1, 4, 0x22, 0x60),
PIN(89, 1, 5, 0x22, 0x60),
PIN(90, 1, 6, 0x22, 0x60),
PIN(91, 1, 7, 0x22, 0x60),
PIN(92, 1, 8, 0x22, 0x60),
PIN(93, 1, 18, 0x22, 0x60),
PIN(94, 1, 19, 0x22, 0x60),
PIN(95, 1, 17, 0x22, 0x60),
PIN(96, 1, 0, 0x22, 0x60),
PIN(97, 0, 20, 0x22, 0x70),
PIN(98, 0, 28, 0x22, 0x70),
PIN(99, 0, 27, 0x22, 0x70),
PIN(100, 0, 30, 0x22, 0x70),
PIN(101, 0, 29, 0x22, 0x70),
PIN(102, 0, 0, 0x22, 0x70),
PIN(103, 0, 31, 0x22, 0x70),
PIN(104, 1, 25, 0x22, 0x60),
PIN(105, 1, 26, 0x22, 0x60),
PIN(106, 1, 23, 0x22, 0x60),
PIN(107, 1, 24, 0x22, 0x60),
PIN(108, 0, 22, 0x22, 0x70),
PIN(109, 0, 21, 0x22, 0x70),
PIN(110, 1, 1, 0x14, 0x20),
PIN(111, 1, 0, 0x14, 0x20),
PIN(112, 1, 2, 0x14, 0x20),
PIN(113, 1, 3, 0x14, 0x20),
PIN(114, 1, 4, 0x14, 0x20),
PIN(115, 1, 5, 0x14, 0x20),
PIN(116, 1, 9, 0x25, 0x50),
PIN(117, 1, 8, 0x25, 0x50),
PIN(118, 1, 7, 0x25, 0x50),
PIN(119, 1, 6, 0x25, 0x50),
PIN(120, 1, 11, 0x25, 0x50),
PIN(121, 1, 1, 0x25, 0x50),
PIN(122, 1, 0, 0x25, 0x50),
PIN(123, 1, 5, 0x25, 0x50),
PIN(124, 1, 4, 0x25, 0x50),
PIN(125, 1, 3, 0x25, 0x50),
PIN(126, 1, 2, 0x25, 0x50),
PIN(127, 1, 10, 0x25, 0x50),
PIN(128, 0, 3, 0x22, 0x70),
PIN(129, 0, 1, 0x22, 0x70),
PIN(130, 0, 4, 0x22, 0x70),
PIN(131, 0, 2, 0x22, 0x70),
PIN(132, 0, 13, 0x25, 0x60),
PIN(133, 0, 12, 0x25, 0x60),
PIN(134, 0, 15, 0x25, 0x60),
PIN(135, 0, 14, 0x25, 0x60),
PIN(136, 0, 13, 0x21, 0xb0),
PIN(137, 0, 12, 0x21, 0xb0),
PIN(138, 0, 15, 0x21, 0xb0),
PIN(139, 0, 14, 0x21, 0xb0),
PIN(140, 0, 17, 0x21, 0xb0),
PIN(141, 0, 16, 0x21, 0xb0),
PIN(142, 0, 19, 0x21, 0xb0),
PIN(143, 0, 18, 0x21, 0xb0),
};
#endif /* MT_GPIO_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
+150
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <stdint.h>
#include <arch_helpers.h>
#include <lib/psci/psci.h>
#include <lib/spinlock.h>
#include <mt_cpu_pm_cpc.h>
#include <mt_lp_irqremain.h>
#include <mt_lp_rm.h>
#include <mt_mcdi.h>
#include <plat_mtk_lpm.h>
#include <plat_pm.h>
DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1);
static int plat_mt_lp_cpu_rc;
static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state)
{
return 0;
}
static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state)
{
mtk_cpc_core_on_hint_clr(cpu);
if (IS_SYSTEM_SUSPEND_STATE(state)) {
mtk_cpc_time_sync();
}
return 0;
}
static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state)
{
return 0;
}
static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
{
/* clear DBGPRCR.CORENPDRQ to allow CPU power down */
write_dbgprcr_el1(0ULL);
return 0;
}
static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state)
{
return 0;
}
static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
{
return 0;
}
static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
{
if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
return -1;
}
mtk_cpc_mcusys_off_reflect();
return 0;
}
static int pwr_mcusys_pwron_finished(unsigned int cpu,
const psci_power_state_t *state)
{
int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
return -1;
}
mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
mt_lp_irqremain_release();
return 0;
}
static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
{
int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
if (!IS_MCUSYS_OFF_STATE(state)) {
goto mt_pwr_mcusysoff_break;
}
if (mcdi_try_init() != 0) {
goto mt_pwr_mcusysoff_break;
}
if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
goto mt_pwr_mcusysoff_break;
}
plat_mt_lp_cpu_rc =
mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
if (plat_mt_lp_cpu_rc < 0) {
goto mt_pwr_mcusysoff_reflect;
}
mt_lp_irqremain_aquire();
return 0;
mt_pwr_mcusysoff_reflect:
mtk_cpc_mcusys_off_reflect();
mt_pwr_mcusysoff_break:
plat_mt_lp_cpu_rc = -1;
return -1;
}
static const struct mt_lpm_tz plat_pm = {
.pwr_prompt = pwr_state_prompt,
.pwr_reflect = pwr_state_reflect,
.pwr_cpu_on = pwr_cpu_pwron,
.pwr_cpu_dwn = pwr_cpu_pwrdwn,
.pwr_cluster_on = pwr_cluster_pwron,
.pwr_cluster_dwn = pwr_cluster_pwrdwn,
.pwr_mcusys_dwn = pwr_mcusys_pwrdwn,
.pwr_mcusys_on = pwr_mcusys_pwron,
.pwr_mcusys_on_finished = pwr_mcusys_pwron_finished
};
const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
{
mtk_cpc_init();
if (mcdi_try_init() == 0) {
INFO("MCDI init done.\n");
}
mt_lp_irqremain_init();
return &plat_pm;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
+269
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@@ -0,0 +1,269 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <drivers/delay_timer.h>
#include <mt_cpu_pm_cpc.h>
#include <mt_timer.h>
struct mtk_cpc_dev {
int auto_off;
unsigned int auto_thres_tick;
};
static struct mtk_cpc_dev cpc;
static int mtk_cpc_last_core_prot(uint32_t prot_req,
uint32_t resp_reg, uint32_t resp_ofs)
{
uint32_t sta, retry;
retry = 0U;
while (retry++ < RETRY_CNT_MAX) {
mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req);
udelay(1U);
sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK;
if (sta == PROT_SUCCESS) {
return CPC_SUCCESS;
} else if (sta == PROT_GIVEUP) {
return CPC_ERR_FAIL;
}
}
return CPC_ERR_TIMEOUT;
}
int mtk_cpu_pm_mcusys_prot_aquire(void)
{
return mtk_cpc_last_core_prot(
MCUSYS_PROT_SET,
CPC_MCUSYS_LAST_CORE_RESP,
MCUSYS_RESP_OFS);
}
void mtk_cpu_pm_mcusys_prot_release(void)
{
mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR);
}
int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster)
{
return mtk_cpc_last_core_prot(
CPUSYS_PROT_SET,
CPC_MCUSYS_MP_LAST_CORE_RESP,
CPUSYS_RESP_OFS);
}
void mtk_cpu_pm_cluster_prot_release(unsigned int cluster)
{
mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR);
}
static void mtk_cpc_cluster_cnt_backup(void)
{
uint32_t backup_cnt;
uint32_t curr_cnt;
uint32_t cnt_mask = GENMASK(14, 0);
uint32_t clr_mask = GENMASK(1, 0);
/* Single Cluster */
backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP);
curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER);
/* Get off count if dormant count is 0 */
if ((curr_cnt & cnt_mask) == 0U) {
curr_cnt = (curr_cnt >> 16) & cnt_mask;
} else {
curr_cnt = curr_cnt & cnt_mask;
}
mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt);
mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask);
}
static inline void mtk_cpc_mcusys_off_en(void)
{
mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U);
}
static inline void mtk_cpc_mcusys_off_dis(void)
{
mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U);
}
void mtk_cpc_mcusys_off_reflect(void)
{
mtk_cpc_mcusys_off_dis();
mtk_cpu_pm_mcusys_prot_release();
}
int mtk_cpc_mcusys_off_prepare(void)
{
if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) {
return CPC_ERR_FAIL;
}
mtk_cpc_cluster_cnt_backup();
mtk_cpc_mcusys_off_en();
return CPC_SUCCESS;
}
void mtk_cpc_core_on_hint_set(unsigned int cpu)
{
mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu));
}
void mtk_cpc_core_on_hint_clr(unsigned int cpu)
{
mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu));
}
static void mtk_cpc_dump_timestamp(void)
{
uint32_t id;
for (id = 0U; id < CPC_TRACE_ID_NUM; id++) {
mmio_write_32(CPC_MCUSYS_TRACE_SEL, id);
memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id),
(const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA,
CPC_TRACE_SIZE);
}
}
void mtk_cpc_time_sync(void)
{
uint64_t kt;
uint32_t systime_l, systime_h;
kt = sched_clock();
systime_l = mmio_read_32(CNTSYS_L_REG);
systime_h = mmio_read_32(CNTSYS_H_REG);
/* sync kernel timer to cpc */
mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt);
mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32));
/* sync system timer to cpc */
mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l);
mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h);
}
static void mtk_cpc_config(uint32_t cfg, uint32_t data)
{
uint32_t val;
uint32_t reg = 0U;
switch (cfg) {
case CPC_SMC_CONFIG_PROF:
reg = CPC_MCUSYS_CPC_DBG_SETTING;
val = mmio_read_32(reg);
val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN);
break;
case CPC_SMC_CONFIG_AUTO_OFF:
reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG;
val = mmio_read_32(reg);
if (data != 0U) {
val |= CPC_AUTO_OFF_EN;
cpc.auto_off = 1;
} else {
val &= ~CPC_AUTO_OFF_EN;
cpc.auto_off = 0;
}
break;
case CPC_SMC_CONFIG_AUTO_OFF_THRES:
reg = CPC_MCUSYS_CPC_OFF_THRES;
cpc.auto_thres_tick = us_to_ticks(data);
val = cpc.auto_thres_tick;
break;
case CPC_SMC_CONFIG_CNT_CLR:
reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR;
val = GENMASK(1, 0); /* clr_mask */
break;
case CPC_SMC_CONFIG_TIME_SYNC:
mtk_cpc_time_sync();
break;
default:
break;
}
if (reg != 0U) {
mmio_write_32(reg, val);
}
}
static uint32_t mtk_cpc_read_config(uint32_t cfg)
{
uint32_t res = 0U;
switch (cfg) {
case CPC_SMC_CONFIG_PROF:
res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ?
1U : 0U;
break;
case CPC_SMC_CONFIG_AUTO_OFF:
res = cpc.auto_off;
break;
case CPC_SMC_CONFIG_AUTO_OFF_THRES:
res = ticks_to_us(cpc.auto_thres_tick);
break;
case CPC_SMC_CONFIG_CNT_CLR:
break;
default:
break;
}
return res;
}
uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2)
{
uint64_t res = 0ULL;
switch (act) {
case CPC_SMC_EVENT_DUMP_TRACE_DATA:
mtk_cpc_dump_timestamp();
break;
case CPC_SMC_EVENT_GIC_DPG_SET:
/* isolated_status = x2; */
break;
case CPC_SMC_EVENT_CPC_CONFIG:
mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2);
break;
case CPC_SMC_EVENT_READ_CONFIG:
res = mtk_cpc_read_config((uint32_t)arg1);
break;
default:
break;
}
return res;
}
void mtk_cpc_init(void)
{
mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING,
mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING)
| CPC_DBG_EN
| CPC_CALC_EN);
cpc.auto_off = 1;
cpc.auto_thres_tick = us_to_ticks(8000);
mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG)
| CPC_OFF_PRE_EN
| (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U));
mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
+106
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/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_CPU_PM_CPC_H
#define MT_CPU_PM_CPC_H
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <mcucfg.h>
#include <platform_def.h>
#define NEED_CPUSYS_PROT_WORKAROUND 1
/* system sram registers */
#define CPUIDLE_SRAM_REG(r) (uint32_t)(MTK_MCDI_SRAM_BASE + (r))
/* db dump */
#define CPC_TRACE_SIZE U(0x20)
#define CPC_TRACE_ID_NUM U(10)
#define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE)
/* buckup off count */
#define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1F0)
#define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1F4)
/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */
#define CPC_PWR_ON_SEQ_DIS BIT(1)
#define CPC_PWR_ON_PRIORITY BIT(2)
#define CPC_AUTO_OFF_EN BIT(5)
#define CPC_DORMANT_WAIT_EN BIT(14)
#define CPC_CTRL_EN BIT(16)
#define CPC_OFF_PRE_EN BIT(29)
/* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */
#define CPUSYS_PROT_SET BIT(0)
#define MCUSYS_PROT_SET BIT(8)
#define CPUSYS_PROT_CLR BIT(8)
#define MCUSYS_PROT_CLR BIT(9)
#define CPC_PROT_RESP_MASK U(0x3)
#define CPUSYS_RESP_OFS U(16)
#define MCUSYS_RESP_OFS U(30)
#define cpusys_resp(r) (((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
#define mcusys_resp(r) (((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
#define RETRY_CNT_MAX U(1000)
#define PROT_RETRY U(0)
#define PROT_SUCCESS U(1)
#define PROT_GIVEUP U(2)
/* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */
#define CPC_PROF_EN BIT(0)
#define CPC_DBG_EN BIT(1)
#define CPC_FREEZE BIT(2)
#define CPC_CALC_EN BIT(3)
enum {
CPC_SUCCESS = 0,
CPC_ERR_FAIL,
CPC_ERR_TIMEOUT,
NF_CPC_ERR
};
enum {
CPC_SMC_EVENT_DUMP_TRACE_DATA,
CPC_SMC_EVENT_GIC_DPG_SET,
CPC_SMC_EVENT_CPC_CONFIG,
CPC_SMC_EVENT_READ_CONFIG,
NF_CPC_SMC_EVENT
};
enum {
CPC_SMC_CONFIG_PROF,
CPC_SMC_CONFIG_AUTO_OFF,
CPC_SMC_CONFIG_AUTO_OFF_THRES,
CPC_SMC_CONFIG_CNT_CLR,
CPC_SMC_CONFIG_TIME_SYNC,
NF_CPC_SMC_CONFIG
};
#define us_to_ticks(us) ((us) * 13)
#define ticks_to_us(tick) ((tick) / 13)
int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster);
void mtk_cpu_pm_cluster_prot_release(unsigned int cluster);
void mtk_cpc_mcusys_off_reflect(void);
int mtk_cpc_mcusys_off_prepare(void);
void mtk_cpc_core_on_hint_set(unsigned int cpu);
void mtk_cpc_core_on_hint_clr(unsigned int cpu);
void mtk_cpc_time_sync(void);
uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2);
void mtk_cpc_init(void);
#endif /* MT_CPU_PM_CPC_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
+69
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@@ -0,0 +1,69 @@
/*
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mt_cirq.h>
#include <mt_lp_irqremain.h>
#include <mt_lp_rm.h>
#include <plat_mtk_lpm.h>
#define KEYPAD_IRQ_ID U(138)
#define KEYPAD_WAKESRC 0x4
static struct mt_irqremain remain_irqs;
int mt_lp_irqremain_submit(void)
{
if (remain_irqs.count == 0) {
return -1;
}
set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
return 0;
}
int mt_lp_irqremain_aquire(void)
{
if (remain_irqs.count == 0) {
return -1;
}
mt_cirq_sw_reset();
mt_cirq_clone_gic();
mt_cirq_enable();
return 0;
}
int mt_lp_irqremain_release(void)
{
if (remain_irqs.count == 0) {
return -1;
}
mt_cirq_flush();
mt_cirq_disable();
return 0;
}
void mt_lp_irqremain_init(void)
{
uint32_t idx;
remain_irqs.count = 0;
/*edge keypad*/
idx = remain_irqs.count;
remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
remain_irqs.wakeupsrc_cat[idx] = 0;
remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
remain_irqs.count++;
mt_lp_irqremain_submit();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h
+14
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@@ -0,0 +1,14 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_LP_IRQREMAIN_H
#define MT_LP_IRQREMAIN_H
extern int mt_lp_irqremain_submit(void);
extern int mt_lp_irqremain_aquire(void);
extern int mt_lp_irqremain_release(void);
extern void mt_lp_irqremain_init(void);
#endif /* MT_LP_IRQREMAIN_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
+151
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cdefs.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <mt_mcdi.h>
/* Read/Write */
#define APMCU_MCUPM_MBOX_AP_READY U(0)
#define APMCU_MCUPM_MBOX_RESERVED_1 U(1)
#define APMCU_MCUPM_MBOX_RESERVED_2 U(2)
#define APMCU_MCUPM_MBOX_RESERVED_3 U(3)
#define APMCU_MCUPM_MBOX_PWR_CTRL_EN U(4)
#define APMCU_MCUPM_MBOX_L3_CACHE_MODE U(5)
#define APMCU_MCUPM_MBOX_BUCK_MODE U(6)
#define APMCU_MCUPM_MBOX_ARMPLL_MODE U(7)
/* Read only */
#define APMCU_MCUPM_MBOX_TASK_STA U(8)
#define APMCU_MCUPM_MBOX_RESERVED_9 U(9)
#define APMCU_MCUPM_MBOX_RESERVED_10 U(10)
#define APMCU_MCUPM_MBOX_RESERVED_11 U(11)
/* CPC mode - Read/Write */
#define APMCU_MCUPM_MBOX_WAKEUP_CPU U(12)
/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN */
#define MCUPM_MCUSYS_CTRL BIT(0)
#define MCUPM_BUCK_CTRL BIT(1)
#define MCUPM_ARMPLL_CTRL BIT(2)
#define MCUPM_CM_CTRL BIT(3)
#define MCUPM_PWR_CTRL_MASK GENMASK(3, 0)
/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE */
#define MCUPM_BUCK_NORMAL_MODE U(0) /* default */
#define MCUPM_BUCK_LP_MODE U(1)
#define MCUPM_BUCK_OFF_MODE U(2)
#define NF_MCUPM_BUCK_MODE U(3)
/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE */
#define MCUPM_ARMPLL_ON U(0) /* default */
#define MCUPM_ARMPLL_GATING U(1)
#define MCUPM_ARMPLL_OFF U(2)
#define NF_MCUPM_ARMPLL_MODE U(3)
/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA */
#define MCUPM_TASK_UNINIT U(0)
#define MCUPM_TASK_INIT U(1)
#define MCUPM_TASK_INIT_FINISH U(2)
#define MCUPM_TASK_WAIT U(3)
#define MCUPM_TASK_RUN U(4)
#define MCUPM_TASK_PAUSE U(5)
#define SSPM_MBOX_3_BASE U(0x0c55fce0)
#define MCDI_NOT_INIT 0
#define MCDI_INIT_1 1
#define MCDI_INIT_2 2
#define MCDI_INIT_DONE 3
static int mcdi_init_status __section("tzfw_coherent_mem");
static inline uint32_t mcdi_mbox_read(uint32_t id)
{
return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
}
static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
{
mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
}
static void mtk_mcupm_pwr_ctrl_setting(uint32_t dev)
{
mcdi_mbox_write(APMCU_MCUPM_MBOX_PWR_CTRL_EN, dev);
}
static void mtk_set_mcupm_pll_mode(uint32_t mode)
{
if (mode < NF_MCUPM_ARMPLL_MODE) {
mcdi_mbox_write(APMCU_MCUPM_MBOX_ARMPLL_MODE, mode);
}
}
static void mtk_set_mcupm_buck_mode(uint32_t mode)
{
if (mode < NF_MCUPM_BUCK_MODE) {
mcdi_mbox_write(APMCU_MCUPM_MBOX_BUCK_MODE, mode);
}
}
static int mtk_mcupm_is_ready(void)
{
unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
return (sta == MCUPM_TASK_WAIT) || (sta == MCUPM_TASK_INIT_FINISH);
}
static int mcdi_init_1(void)
{
unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
if (sta != MCUPM_TASK_INIT) {
return -1;
}
mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF);
mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE);
mtk_mcupm_pwr_ctrl_setting(
MCUPM_MCUSYS_CTRL |
MCUPM_BUCK_CTRL |
MCUPM_ARMPLL_CTRL);
mcdi_mbox_write(APMCU_MCUPM_MBOX_AP_READY, 1);
return 0;
}
static int mcdi_init_2(void)
{
return mtk_mcupm_is_ready() ? 0 : -1;
}
int mcdi_try_init(void)
{
if (mcdi_init_status == MCDI_INIT_DONE) {
return 0;
}
if (mcdi_init_status == MCDI_NOT_INIT) {
mcdi_init_status = MCDI_INIT_1;
}
if (mcdi_init_status == MCDI_INIT_1 && mcdi_init_1() == 0) {
mcdi_init_status = MCDI_INIT_2;
}
if (mcdi_init_status == MCDI_INIT_2 && mcdi_init_2() == 0) {
mcdi_init_status = MCDI_INIT_DONE;
}
INFO("mcdi ready for mcusys-off-idle and system suspend\n");
return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
+12
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@@ -0,0 +1,12 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_MCDI_H
#define MT_MCDI_H
int mcdi_try_init(void);
#endif /* MT_MCDI_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
+30
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@@ -0,0 +1,30 @@
/*
* Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PMIC_WRAP_INIT_H
#define PMIC_WRAP_INIT_H
#include <stdint.h>
#include "platform_def.h"
#include <pmic_wrap_init_common.h>
static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
/* PMIC_WRAP registers */
struct mt8195_pmic_wrap_regs {
uint32_t init_done;
uint32_t reserved[543];
uint32_t wacs2_cmd;
uint32_t wacs2_wdata;
uint32_t reserved1[3];
uint32_t wacs2_rdata;
uint32_t reserved2[3];
uint32_t wacs2_vldclr;
uint32_t wacs2_sta;
};
#endif /* PMIC_WRAP_INIT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/ptp3/ptp3_plat.h
+46
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@@ -0,0 +1,46 @@
/*
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PTP3_PLAT_H
#define PTP3_PLAT_H
#include <lib/mmio.h>
#include <lib/utils_def.h>
#include <ptp3_common.h>
/* CPU info */
#define NR_PTP3_CFG_CPU U(8)
#define PTP3_CFG_CPU_START_ID_L U(0)
#define PTP3_CFG_CPU_START_ID_B U(4)
#define PTP3_CFG_CPU_END_ID U(7)
#define NR_PTP3_CFG1_DATA U(2)
#define PTP3_CFG1_MASK 0x3000
#define NR_PTP3_CFG2_DATA U(5)
#define PTP3_CFG3_MASK1 0x1180
#define PTP3_CFG3_MASK2 0x35C0
#define PTP3_CFG3_MASK3 0x3DC0
/* Central control */
static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
{0x0C53A2A0, 0x1000},
{0x0C53A2A4, 0x1000}
};
static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
{0x0C530404, 0x3A1000},
{0x0C530428, 0x13E0408},
{0x0C530434, 0xB22800},
{0x0C53043C, 0x750},
{0x0C530440, 0x0222c4cc}
};
static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80};
static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
#endif /* PTP3_PLAT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/build.mk
+68
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@@ -0,0 +1,68 @@
#
# Copyright (c) 2021, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Enable or disable spm feature
MT_SPM_FEATURE_SUPPORT = yes
# Enable or disable cirq restore
MT_SPM_CIRQ_FEATURE_SUPPORT = yes
# sspm notifier support
MT_SPM_SSPM_NOTIFIER_SUPPORT = yes
CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
# spm common files
PLAT_SPM_SOURCE_FILES_COMMON += \
${CUR_SPM_FOLDER}/mt_spm.c \
${CUR_SPM_FOLDER}/mt_spm_conservation.c \
${CUR_SPM_FOLDER}/mt_spm_internal.c \
${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c
# spm platform dependcy files
PLAT_SPM_SOURCE_FILES += \
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c \
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c \
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c \
${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c \
${CUR_SPM_FOLDER}/mt_spm_cond.c \
${CUR_SPM_FOLDER}/mt_spm_suspend.c \
${CUR_SPM_FOLDER}/mt_spm_idle.c \
${CUR_SPM_FOLDER}/mt_spm_vcorefs.c
ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
else
BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
${PLAT_SPM_SOURCE_FILES_COMMON} \
${PLAT_SPM_SOURCE_FILES}
endif
ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
endif
ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
else
BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
endif
$(info --------------------------------------)
$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
$(info --------------------------------------)
# Common makefile for platform.mk
PLAT_INCLUDES += \
${PLAT_SPM_DEBUG_CFLAGS} \
-I${CUR_SPM_FOLDER}/ \
-I${CUR_SPM_FOLDER}/constraints/ \
-I${CUR_SPM_FOLDER}/notifier/
PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
+241
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/*
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_constraint.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#include <plat_mtk_lpm.h>
#ifndef ATF_PLAT_CIRQ_UNSUPPORT
#include <mt_cirq.h>
#include <mt_gic_v3.h>
#endif
#define CONSTRAINT_BUS26M_ALLOW \
(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
#define CONSTRAINT_BUS26M_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_ENABLE_TIA_WORKAROUND | \
SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
#define CONSTRAINT_BUS26M_PCM_FLAG1 0U
#define CONSTRAINT_BUS26M_RESOURCE_REQ 0U
static unsigned int bus26m_ext_opand;
static struct mt_irqremain *refer2remain_irq;
static struct mt_spm_cond_tables cond_bus26m = {
.name = "bus26m",
.table_cg = {
0xFFFFD408, /* MTCMOS1 */
0x2284C802, /* INFRA0 */
0x27AF8000, /* INFRA1 */
0x86040650, /* INFRA2 */
0x30038020, /* INFRA3 */
0x80000000, /* INFRA4 */
0x00080ABB, /* PERI0 */
0x00004000, /* VPPSYS0_0 */
0x08803000, /* VPPSYS0_1 */
0x00000000, /* VPPSYS0_2 */
0x80005555, /* VPPSYS1_0 */
0x00009008, /* VPPSYS1_1 */
0x60060000, /* VDOSYS0_0 */
0x00000000, /* VDOSYS0_1 */
0x201E01F8, /* VDOSYS1_0 */
0x00800000, /* VDOSYS1_1 */
0x00000000, /* VDOSYS1_2 */
0x00000080, /* I2C */
},
.table_pll = (PLL_BIT_UNIVPLL |
PLL_BIT_MFGPLL |
PLL_BIT_MSDCPLL |
PLL_BIT_TVDPLL |
PLL_BIT_MMPLL),
};
static struct mt_spm_cond_tables cond_bus26m_res = {
.table_cg = { 0U },
.table_pll = 0U,
};
static struct constraint_status status = {
.id = MT_RM_CONSTRAINT_ID_BUS26M,
.valid = (MT_SPM_RC_VALID_SW |
MT_SPM_RC_VALID_COND_LATCH),
.cond_block = 0U,
.enter_cnt = 0U,
.cond_res = &cond_bus26m_res,
};
/*
* Cirq will take the place of gic when gic is off.
* However, cirq cannot work if 26m clk is turned off when system idle/suspend.
* Therefore, we need to set irq pending for specific wakeup source.
*/
#ifdef ATF_PLAT_CIRQ_UNSUPPORT
#define do_irqs_delivery()
#else
static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
unsigned int irq_index,
struct wake_status *wakeup)
{
INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
wakeup->tr.comm.b_sw_flag1);
INFO("irq:%u(0x%08x) set pending\n",
irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
}
static void do_irqs_delivery(void)
{
unsigned int idx;
int res = 0;
struct wake_status *wakeup = NULL;
struct mt_irqremain *irqs = refer2remain_irq;
res = spm_conservation_get_result(&wakeup);
if ((res != 0) && (irqs == NULL)) {
return;
}
for (idx = 0U; idx < irqs->count; ++idx) {
if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
if ((irqs->wakeupsrc_cat[idx] &
MT_IRQ_REMAIN_CAT_LOG) != 0U) {
mt_spm_irq_remain_dump(irqs, idx, wakeup);
}
mt_irq_set_pending(irqs->irqs[idx]);
}
}
}
#endif
static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
unsigned int *resource_req)
{
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
*resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
}
bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
{
(void)cpu;
(void)state_id;
return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
}
int spm_update_rc_bus26m(int state_id, int type, const void *val)
{
const struct mt_spm_cond_tables *tlb;
const struct mt_spm_cond_tables *tlb_check;
int res = MT_RM_STATUS_OK;
if (val == NULL) {
return MT_RM_STATUS_BAD;
}
if (type == PLAT_RC_UPDATE_CONDITION) {
tlb = (const struct mt_spm_cond_tables *)val;
tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
status.cond_block =
mt_spm_cond_check(state_id, tlb, tlb_check,
((status.valid &
MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
&cond_bus26m_res : NULL);
} else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
refer2remain_irq = (struct mt_irqremain *)val;
} else {
res = MT_RM_STATUS_BAD;
}
return res;
}
unsigned int spm_allow_rc_bus26m(int state_id)
{
(void)state_id;
return CONSTRAINT_BUS26M_ALLOW;
}
int spm_run_rc_bus26m(unsigned int cpu, int state_id)
{
(void)cpu;
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
(IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_HW_S1_DETECT |
MT_SPM_EX_OP_SET_SUSPEND_MODE |
bus26m_ext_opand),
CONSTRAINT_BUS26M_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
spm_bus26m_conduct);
}
return 0;
}
int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
(void)cpu;
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
mt_spm_suspend_resume(state_id, ext_op, NULL);
bus26m_ext_opand = 0U;
} else {
mt_spm_idle_generic_resume(state_id, ext_op, NULL);
status.enter_cnt++;
}
do_irqs_delivery();
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_constraint.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#define CONSTRAINT_CPU_BUCK_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 0U
#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ \
(MT_SPM_DRAM_S1 | \
MT_SPM_DRAM_S0 | \
MT_SPM_SYSPLL | \
MT_SPM_INFRA | \
MT_SPM_26M | \
MT_SPM_XO_FPM)
static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
static unsigned int cpubuckldo_enter_cnt;
static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
unsigned int *resource_req)
{
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
}
bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
{
(void)cpu;
(void)state_id;
return IS_MT_RM_RC_READY(cpubuckldo_status);
}
unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
{
(void)state_id;
return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
}
int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
{
(void)cpu;
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
(IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
MT_SPM_EX_OP_SET_SUSPEND_MODE |
MT_SPM_EX_OP_SET_WDT,
CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, 0U,
spm_cpu_bcuk_ldo_conduct);
}
cpubuckldo_enter_cnt++;
return 0;
}
int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
{
(void)cpu;
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
} else {
mt_spm_idle_generic_resume(state_id, 0U, NULL);
}
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_constraint.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_reg.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#include <plat_mtk_lpm.h>
#define CONSTRAINT_DRAM_ALLOW \
(MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
#define CONSTRAINT_DRAM_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
#define CONSTRAINT_DRAM_PCM_FLAG1 0U
#define CONSTRAINT_DRAM_RESOURCE_REQ \
(MT_SPM_SYSPLL | \
MT_SPM_INFRA | \
MT_SPM_26M)
static struct mt_spm_cond_tables cond_dram = {
.name = "dram",
.table_cg = {
0xFFFDD008, /* MTCMOS1 */
0x20040802, /* INFRA0 */
0x27AF8000, /* INFRA1 */
0x86040640, /* INFRA2 */
0x00000000, /* INFRA3 */
0x80000000, /* INFRA4 */
0x00000000, /* PERI0 */
0x00004000, /* VPPSYS0_0 */
0x08803000, /* VPPSYS0_1 */
0x00000000, /* VPPSYS0_2 */
0x80005555, /* VPPSYS1_0 */
0x00009008, /* VPPSYS1_1 */
0x60060000, /* VDOSYS0_0 */
0x00000000, /* VDOSYS0_1 */
0x201E01F8, /* VDOSYS1_0 */
0x00800000, /* VDOSYS1_1 */
0x00000000, /* VDOSYS1_2 */
0x00000080, /* I2C */
},
.table_pll = 0U,
};
static struct mt_spm_cond_tables cond_dram_res = {
.table_cg = { 0U },
.table_pll = 0U,
};
static struct constraint_status status = {
.id = MT_RM_CONSTRAINT_ID_DRAM,
.valid = (MT_SPM_RC_VALID_SW |
MT_SPM_RC_VALID_COND_LATCH |
MT_SPM_RC_VALID_XSOC_BBLPM),
.cond_block = 0U,
.enter_cnt = 0U,
.cond_res = &cond_dram_res,
};
static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
unsigned int *resource_req)
{
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
*resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
}
bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
{
(void)cpu;
(void)state_id;
return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
}
int spm_update_rc_dram(int state_id, int type, const void *val)
{
const struct mt_spm_cond_tables *tlb;
const struct mt_spm_cond_tables *tlb_check;
int res = MT_RM_STATUS_OK;
if (val == NULL) {
return MT_RM_STATUS_BAD;
}
if (type == PLAT_RC_UPDATE_CONDITION) {
tlb = (const struct mt_spm_cond_tables *)val;
tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
status.cond_block =
mt_spm_cond_check(state_id, tlb, tlb_check,
((status.valid &
MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
&cond_dram_res : NULL);
} else {
res = MT_RM_STATUS_BAD;
}
return res;
}
unsigned int spm_allow_rc_dram(int state_id)
{
(void)state_id;
return CONSTRAINT_DRAM_ALLOW;
}
int spm_run_rc_dram(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_DRAM_ALLOW;
(void)cpu;
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
(IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
#else
(void)allows;
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_SET_SUSPEND_MODE |
MT_SPM_EX_OP_HW_S1_DETECT),
CONSTRAINT_DRAM_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
}
return 0;
}
int spm_reset_rc_dram(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_DRAM_ALLOW;
(void)cpu;
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
#else
(void)allows;
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id,
(MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_HW_S1_DETECT),
NULL);
} else {
mt_spm_idle_generic_resume(state_id, ext_op, NULL);
status.enter_cnt++;
}
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_RC_INTERNAL_H
#define MT_SPM_RC_INTERNAL_H
#include <stdbool.h>
#define SPM_FLAG_SRAM_SLEEP_CTRL \
(SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_DISABLE_SYSRAM_SLEEP)
/* cpu buck/ldo constraint function */
bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
/* spm resource dram constraint function */
bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
int spm_update_rc_dram(int state_id, int type, const void *val);
unsigned int spm_allow_rc_dram(int state_id);
int spm_run_rc_dram(unsigned int cpu, int state_id);
int spm_reset_rc_dram(unsigned int cpu, int state_id);
/* spm resource syspll constraint function */
bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
int spm_update_rc_syspll(int state_id, int type, const void *val);
unsigned int spm_allow_rc_syspll(int state_id);
int spm_run_rc_syspll(unsigned int cpu, int state_id);
int spm_reset_rc_syspll(unsigned int cpu, int state_id);
/* spm resource bus26m constraint function */
bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
int spm_update_rc_bus26m(int state_id, int type, const void *val);
unsigned int spm_allow_rc_bus26m(int state_id);
int spm_run_rc_bus26m(unsigned int cpu, int state_id);
int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
#endif /* MT_SPM_RC_INTERNAL_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_constraint.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#include <plat_mtk_lpm.h>
#define CONSTRAINT_SYSPLL_ALLOW \
(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
#define CONSTRAINT_SYSPLL_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_ENABLE_6315_CTRL | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
SPM_FLAG_USE_SRCCLKENO2)
#define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
static struct mt_spm_cond_tables cond_syspll = {
.name = "syspll",
.table_cg = {
0xFFFFD008, /* MTCMOS1 */
0x20844802, /* INFRA0 */
0x27AF8000, /* INFRA1 */
0x86040640, /* INFRA2 */
0x30038020, /* INFRA3 */
0x80000000, /* INFRA4 */
0x00080A8B, /* PERI0 */
0x00004000, /* VPPSYS0_0 */
0x08803000, /* VPPSYS0_1 */
0x00000000, /* VPPSYS0_2 */
0x80005555, /* VPPSYS1_0 */
0x00009008, /* VPPSYS1_1 */
0x60060000, /* VDOSYS0_0 */
0x00000000, /* VDOSYS0_1 */
0x201E01F8, /* VDOSYS1_0 */
0x00800000, /* VDOSYS1_1 */
0x00000000, /* VDOSYS1_2 */
0x00000080, /* I2C */
},
.table_pll = 0U,
};
static struct mt_spm_cond_tables cond_syspll_res = {
.table_cg = { 0U },
.table_pll = 0U,
};
static struct constraint_status status = {
.id = MT_RM_CONSTRAINT_ID_SYSPLL,
.valid = (MT_SPM_RC_VALID_SW |
MT_SPM_RC_VALID_COND_LATCH |
MT_SPM_RC_VALID_XSOC_BBLPM),
.cond_block = 0U,
.enter_cnt = 0U,
.cond_res = &cond_syspll_res,
};
static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
unsigned int *resource_req)
{
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
*resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
}
bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
{
(void)cpu;
(void)state_id;
return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
}
int spm_update_rc_syspll(int state_id, int type, const void *val)
{
const struct mt_spm_cond_tables *tlb;
const struct mt_spm_cond_tables *tlb_check;
int res = MT_RM_STATUS_OK;
if (val == NULL) {
return MT_RM_STATUS_BAD;
}
if (type == PLAT_RC_UPDATE_CONDITION) {
tlb = (const struct mt_spm_cond_tables *)val;
tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
status.cond_block =
mt_spm_cond_check(state_id, tlb, tlb_check,
((status.valid &
MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
&cond_syspll_res : NULL);
} else {
res = MT_RM_STATUS_BAD;
}
return res;
}
unsigned int spm_allow_rc_syspll(int state_id)
{
(void)state_id;
return CONSTRAINT_SYSPLL_ALLOW;
}
int spm_run_rc_syspll(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
(void)cpu;
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
(IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
#else
(void)allows;
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_HW_S1_DETECT |
MT_SPM_EX_OP_SET_SUSPEND_MODE),
CONSTRAINT_SYSPLL_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
}
return 0;
}
int spm_reset_rc_syspll(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
(void)cpu;
if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
#else
(void)allows;
#endif
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id,
(MT_SPM_EX_OP_SET_SUSPEND_MODE |
MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_HW_S1_DETECT),
NULL);
} else {
mt_spm_idle_generic_resume(state_id, ext_op, NULL);
status.enter_cnt++;
}
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <string.h>
#include <common/debug.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_suspend.h>
#include <mtk_plat_common.h>
#include <plat_mtk_lpm.h>
#include <plat_pm.h>
#include <platform_def.h>
#include <sleep_def.h>
#ifdef MT_SPM_USING_BAKERY_LOCK
DEFINE_BAKERY_LOCK(spm_lock);
#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
#else
spinlock_t spm_lock;
#define plat_spm_lock_init()
#endif
/* CLK_SCP_CFG_0 */
#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x264)
#define SPM_CK_CONTROL_EN 0x7FF
struct mt_resource_constraint plat_constraint_bus26m = {
.is_valid = spm_is_valid_rc_bus26m,
.update = spm_update_rc_bus26m,
.allow = spm_allow_rc_bus26m,
.run = spm_run_rc_bus26m,
.reset = spm_reset_rc_bus26m,
};
struct mt_resource_constraint plat_constraint_syspll = {
.is_valid = spm_is_valid_rc_syspll,
.update = spm_update_rc_syspll,
.allow = spm_allow_rc_syspll,
.run = spm_run_rc_syspll,
.reset = spm_reset_rc_syspll,
};
struct mt_resource_constraint plat_constraint_dram = {
.is_valid = spm_is_valid_rc_dram,
.update = spm_update_rc_dram,
.allow = spm_allow_rc_dram,
.run = spm_run_rc_dram,
.reset = spm_reset_rc_dram,
};
struct mt_resource_constraint plat_constraint_cpu = {
.is_valid = spm_is_valid_rc_cpu_buck_ldo,
.update = NULL,
.allow = spm_allow_rc_cpu_buck_ldo,
.run = spm_run_rc_cpu_buck_ldo,
.reset = spm_reset_rc_cpu_buck_ldo,
};
struct mt_resource_constraint *plat_constraints[] = {
&plat_constraint_bus26m,
&plat_constraint_syspll,
&plat_constraint_dram,
&plat_constraint_cpu,
NULL,
};
struct mt_resource_manager plat_mt8195_rm = {
.update = mt_spm_cond_update,
.consts = plat_constraints,
};
void spm_boot_init(void)
{
NOTICE("MT8195 %s\n", __func__);
/* switch ck_off/axi_26m control to SPM */
mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
plat_spm_lock_init();
mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
mt_lp_rm_register(&plat_mt8195_rm);
mt_spm_idle_generic_init();
mt_spm_suspend_init();
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_H
#define MT_SPM_H
#include <lib/bakery_lock.h>
#include <lib/spinlock.h>
#include <plat_mtk_lpm.h>
/*
* ARM v8.2, the cache will turn off automatically when cpu
* power down. So, there is no doubt to use the spin_lock here
*/
#if !HW_ASSISTED_COHERENCY
#define MT_SPM_USING_BAKERY_LOCK
#endif
#ifdef MT_SPM_USING_BAKERY_LOCK
DECLARE_BAKERY_LOCK(spm_lock);
#define plat_spm_lock() bakery_lock_get(&spm_lock)
#define plat_spm_unlock() bakery_lock_release(&spm_lock)
#else
extern spinlock_t spm_lock;
#define plat_spm_lock() spin_lock(&spm_lock)
#define plat_spm_unlock() spin_unlock(&spm_lock)
#endif
#define MT_SPM_USING_SRCLKEN_RC
/* spm extern operand definition */
#define MT_SPM_EX_OP_CLR_26M_RECORD (1U << 0)
#define MT_SPM_EX_OP_SET_WDT (1U << 1)
#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ (1U << 2)
#define MT_SPM_EX_OP_SET_SUSPEND_MODE (1U << 3)
#define MT_SPM_EX_OP_SET_IS_ADSP (1U << 4)
#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM (1U << 5)
#define MT_SPM_EX_OP_HW_S1_DETECT (1U << 6)
typedef enum {
WR_NONE = 0,
WR_UART_BUSY = 1,
WR_ABORT = 2,
WR_PCM_TIMER = 3,
WR_WAKE_SRC = 4,
WR_DVFSRC = 5,
WR_TWAM = 6,
WR_PMSR = 7,
WR_SPM_ACK_CHK = 8,
WR_UNKNOWN = 9,
} wake_reason_t;
static inline void spm_lock_get(void)
{
plat_spm_lock();
}
static inline void spm_lock_release(void)
{
plat_spm_unlock();
}
extern void spm_boot_init(void);
#endif /* MT_SPM_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdbool.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <plat_mtk_lpm.h>
#include <plat_pm.h>
#include <platform_def.h>
#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs)
#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
#define MT_LP_TZ_VPPSYS0_REG(ofs) (VPPSYS0_BASE + ofs)
#define MT_LP_TZ_VPPSYS1_REG(ofs) (VPPSYS1_BASE + ofs)
#define MT_LP_TZ_VDOSYS0_REG(ofs) (VDOSYS0_BASE + ofs)
#define MT_LP_TZ_VDOSYS1_REG(ofs) (VDOSYS1_BASE + ofs)
#define MT_LP_TZ_PERI_AO_REG(ofs) (PERICFG_AO_BASE + ofs)
#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094)
#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090)
#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00E8)
#define TOP_SW_I2C_CG MT_LP_TZ_TOPCK_REG(0x00BC)
#define PERI_SW_CG0 MT_LP_TZ_PERI_AO_REG(0x0018)
#define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020)
#define VPPSYS0_SW_CG1 MT_LP_TZ_VPPSYS0_REG(0x002C)
#define VPPSYS0_SW_CG2 MT_LP_TZ_VPPSYS0_REG(0x0038)
#define VPPSYS1_SW_CG0 MT_LP_TZ_VPPSYS1_REG(0x0100)
#define VPPSYS1_SW_CG1 MT_LP_TZ_VPPSYS1_REG(0x0110)
#define VDOSYS0_SW_CG0 MT_LP_TZ_VDOSYS0_REG(0x0100)
#define VDOSYS0_SW_CG1 MT_LP_TZ_VDOSYS0_REG(0x0110)
#define VDOSYS1_SW_CG0 MT_LP_TZ_VDOSYS1_REG(0x0100)
#define VDOSYS1_SW_CG1 MT_LP_TZ_VDOSYS1_REG(0x0120)
#define VDOSYS1_SW_CG2 MT_LP_TZ_VDOSYS1_REG(0x0130)
/***********************************************************
* Check clkmux registers
***********************************************************/
#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x98 + id * 0x10)
#define PDN_CHECK BIT(7)
#define CLK_CHECK BIT(31)
enum {
CLKMUX_DISP = 0,
NF_CLKMUX,
};
static bool is_clkmux_pdn(unsigned int clkmux_id)
{
unsigned int reg, val, idx;
if ((clkmux_id & CLK_CHECK) != 0U) {
clkmux_id = (clkmux_id & ~CLK_CHECK);
reg = clkmux_id / 4U;
val = mmio_read_32(CLK_CFG(reg));
idx = clkmux_id % 4U;
val = (val >> (idx * 8U)) & PDN_CHECK;
return (val != 0U);
}
return false;
}
static struct mt_spm_cond_tables spm_cond_t;
struct idle_cond_info {
unsigned int subsys_mask;
uintptr_t addr;
bool bBitflip;
unsigned int clkmux_id;
};
#define IDLE_CG(mask, addr, bitflip, clkmux) \
{mask, (uintptr_t)addr, bitflip, clkmux}
static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0U),
IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0U),
IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0U),
IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0U),
IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0U),
IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0U),
IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00000800, VPPSYS0_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
IDLE_CG(0x00000080, TOP_SW_I2C_CG, true, (CLK_CHECK|CLKMUX_DISP)),
};
/***********************************************************
* Check pll idle condition
***********************************************************/
#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x340)
#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x0E0)
#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x1F0)
#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x710)
#define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380)
unsigned int mt_spm_cond_check(int state_id,
const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res)
{
unsigned int blocked = 0U, i;
bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
if ((src == NULL) || (dest == NULL)) {
return SPM_COND_CHECK_FAIL;
}
for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
if (res != NULL) {
res->table_cg[i] =
(src->table_cg[i] & dest->table_cg[i]);
if (is_system_suspend && (res->table_cg[i] != 0U)) {
INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
dest->name, i, idle_cg_info[i].addr,
res->table_cg[i]);
}
if (res->table_cg[i] != 0U) {
blocked |= (1U << i);
}
} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
blocked |= (1U << i);
break;
}
}
if (res != NULL) {
res->table_pll = (src->table_pll & dest->table_pll);
if (res->table_pll != 0U) {
blocked |=
(res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
SPM_COND_CHECK_BLOCKED_PLL;
}
} else if ((src->table_pll & dest->table_pll) != 0U) {
blocked |= SPM_COND_CHECK_BLOCKED_PLL;
}
if (is_system_suspend && (blocked != 0U)) {
INFO("suspend: %s blocked=0x%08x\n", dest->name, blocked);
}
return blocked;
}
#define IS_MT_SPM_PWR_OFF(mask) \
(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
int mt_spm_cond_update(struct mt_resource_constraint **con,
int stateid, void *priv)
{
int res;
uint32_t i;
struct mt_resource_constraint *const *rc;
/* read all cg state */
for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
spm_cond_t.table_cg[i] = 0U;
/* check mtcmos, if off set idle_value and clk to 0 disable */
if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
continue;
}
/* check clkmux */
if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
continue;
}
spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
~mmio_read_32(idle_cg_info[i].addr) :
mmio_read_32(idle_cg_info[i].addr);
}
spm_cond_t.table_pll = 0U;
if ((mmio_read_32(PLL_MFGPLL) & 0x200) != 0U) {
spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
}
if ((mmio_read_32(PLL_MMPLL) & 0x200) != 0U) {
spm_cond_t.table_pll |= PLL_BIT_MMPLL;
}
if ((mmio_read_32(PLL_UNIVPLL) & 0x200) != 0U) {
spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
}
if ((mmio_read_32(PLL_MSDCPLL) & 0x200) != 0U) {
spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
}
if ((mmio_read_32(PLL_TVDPLL) & 0x200) != 0U) {
spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
}
spm_cond_t.priv = priv;
for (rc = con; *rc != NULL; rc++) {
if (((*rc)->update) == NULL) {
continue;
}
res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
(void const *)&spm_cond_t);
if (res != MT_RM_STATUS_OK) {
break;
}
}
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_CONDIT_H
#define MT_SPM_CONDIT_H
#include <mt_lp_rm.h>
enum PLAT_SPM_COND {
PLAT_SPM_COND_MTCMOS1 = 0,
PLAT_SPM_COND_CG_INFRA_0,
PLAT_SPM_COND_CG_INFRA_1,
PLAT_SPM_COND_CG_INFRA_2,
PLAT_SPM_COND_CG_INFRA_3,
PLAT_SPM_COND_CG_INFRA_4,
PLAT_SPM_COND_CG_PERI_SW_0,
PLAT_SPM_COND_CG_VPPSYS0_SW_CG_0,
PLAT_SPM_COND_CG_VPPSYS0_SW_CG_1,
PLAT_SPM_COND_CG_VPPSYS0_SW_CG_2,
PLAT_SPM_COND_CG_VPPSYS1_SW_CG_0,
PLAT_SPM_COND_CG_VPPSYS1_SW_CG_1,
PLAT_SPM_COND_CG_VDOSYS0_SW_CG_0,
PLAT_SPM_COND_CG_VDOSYS0_SW_CG_1,
PLAT_SPM_COND_CG_VDOSYS1_SW_CG_0,
PLAT_SPM_COND_CG_VDOSYS1_SW_CG_1,
PLAT_SPM_COND_CG_VDOSYS1_SW_CG_2,
PLAT_SPM_COND_CG_I2C_SW_CG,
PLAT_SPM_COND_MAX,
};
enum PLAT_SPM_COND_PLL {
PLAT_SPM_COND_PLL_UNIVPLL = 0,
PLAT_SPM_COND_PLL_MFGPLL,
PLAT_SPM_COND_PLL_MSDCPLL,
PLAT_SPM_COND_PLL_TVDPLL,
PLAT_SPM_COND_PLL_MMPLL,
PLAT_SPM_COND_PLL_MAX,
};
#define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL)
#define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL)
#define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL)
#define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL)
#define PLL_BIT_TVDPLL BIT(PLAT_SPM_COND_PLL_TVDPLL)
/* Definition about SPM_COND_CHECK_BLOCKED
* bit [00 ~ 17]: cg blocking index
* bit [18 ~ 29]: pll blocking index
* bit [30] : pll blocking information
* bit [31] : idle condition check fail
*/
#define SPM_COND_BLOCKED_CG_IDX U(0)
#define SPM_COND_BLOCKED_PLL_IDX U(18)
#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
#define SPM_COND_CHECK_FAIL BIT(31)
struct mt_spm_cond_tables {
char *name;
unsigned int table_cg[PLAT_SPM_COND_MAX];
unsigned int table_pll;
void *priv;
};
extern unsigned int mt_spm_cond_check(int state_id,
const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
extern int mt_spm_cond_update(struct mt_resource_constraint **con,
int stateid, void *priv);
#endif /* MT_SPM_CONDIT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_internal.h>
#include <mt_spm_reg.h>
#include <plat_mtk_lpm.h>
#include <plat_pm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
struct wake_status spm_wakesta; /* record last wakesta */
static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
unsigned int resource_req)
{
int ret = 0;
struct pwr_ctrl *pwrctrl;
uint32_t cpu = plat_my_core_pos();
pwrctrl = spm_lp->pwrctrl;
__spm_set_cpu_status(cpu);
__spm_set_power_control(pwrctrl);
__spm_set_wakeup_event(pwrctrl);
__spm_set_pcm_flags(pwrctrl);
__spm_src_req_update(pwrctrl, resource_req);
if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
__spm_set_pcm_wdt(1);
}
if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
__spm_xo_soc_bblpm(1);
}
if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
spm_hw_s1_state_monitor_resume();
}
/* Disable auto resume by PCM in system suspend stage */
if (IS_PLAT_SUSPEND_ID(state_id)) {
__spm_disable_pcm_timer();
__spm_set_pcm_wdt(0);
}
__spm_send_cpu_wakeup_event();
INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
mmio_read_32(PCM_TIMER_VAL) / 32768);
INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
mmio_read_32(PWR_STATUS_2ND));
INFO("cpu_pwr = 0x%x 0x%x\n", mmio_read_32(CPU_PWR_STATUS),
mmio_read_32(CPU_PWR_STATUS_2ND));
return ret;
}
static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
struct wake_status **status)
{
unsigned int ext_status = 0U;
/* system watchdog will be resumed at kernel stage */
if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
__spm_set_pcm_wdt(0);
}
if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
__spm_xo_soc_bblpm(0);
}
if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
spm_hw_s1_state_monitor_pause(&ext_status);
}
__spm_ext_int_wakeup_req_clr();
__spm_get_wakeup_status(&spm_wakesta, ext_status);
if (status != NULL) {
*status = &spm_wakesta;
}
__spm_clean_after_wakeup();
if (IS_PLAT_SUSPEND_ID(state_id)) {
__spm_output_wake_reason(state_id, &spm_wakesta);
}
}
int spm_conservation(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp, unsigned int resource_req)
{
if (spm_lp == NULL) {
return -1;
}
spm_lock_get();
go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
spm_lock_release();
return 0;
}
void spm_conservation_finish(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
struct wake_status **status)
{
spm_lock_get();
go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
spm_lock_release();
}
int spm_conservation_get_result(struct wake_status **res)
{
if (res == NULL) {
return -1;
}
*res = &spm_wakesta;
return 0;
}
#define GPIO_BANK (GPIO_BASE + 0x6F0)
#define TRAP_UFS_FIRST BIT(11) /* bit 11, 0: UFS, 1: eMMC */
void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
{
if (pwrctrl == NULL) {
return;
}
/* For ufs, emmc storage type */
if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
/* If eMMC is used, mask UFS req */
pwrctrl->reg_ufs_srcclkena_mask_b = 0;
pwrctrl->reg_ufs_infra_req_mask_b = 0;
pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
pwrctrl->reg_ufs_ddr_en_mask_b = 0;
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h
+20
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_CONSERVATION_H
#define MT_SPM_CONSERVATION_H
#include <mt_spm_internal.h>
extern int spm_conservation(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
unsigned int resource_req);
extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
struct spm_lp_scen *spm_lp,
struct wake_status **status);
extern int spm_conservation_get_result(struct wake_status **res);
extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
#endif /* MT_SPM_CONSERVATION_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h
+63
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_CONSTRAINT_H
#define MT_SPM_CONSTRAINT_H
#include <mt_lp_rm.h>
#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0)
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1)
#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2)
#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3)
#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4)
#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5)
#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6)
#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7)
#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8)
#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9)
#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10)
#define MT_SPM_RC_INVALID 0x0
#define MT_SPM_RC_VALID_SW (1U << 0)
#define MT_SPM_RC_VALID_FW (1U << 1)
#define MT_SPM_RC_VALID_RESIDNECY (1U << 2)
#define MT_SPM_RC_VALID_COND_CHECK (1U << 3)
#define MT_SPM_RC_VALID_COND_LATCH (1U << 4)
#define MT_SPM_RC_VALID_UFS_H8 (1U << 5)
#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6)
#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7)
#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8)
#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
#define IS_MT_RM_RC_READY(status) \
((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
#define MT_SPM_RC_BBLPM_MODE \
(MT_SPM_RC_VALID_UFS_H8 | \
MT_SPM_RC_VALID_FLIGHTMODE | \
MT_SPM_RC_VALID_XSOC_BBLPM)
#define IS_MT_SPM_RC_BBLPM_MODE(st) \
((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
struct constraint_status {
uint16_t id;
uint16_t valid;
uint32_t cond_block;
uint32_t enter_cnt;
struct mt_spm_cond_tables *cond_res;
};
enum MT_SPM_RM_RC_TYPE {
MT_RM_CONSTRAINT_ID_BUS26M,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
MT_RM_CONSTRAINT_ID_ALL,
};
#endif /* MT_SPM_CONSTRAINT_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <plat_pm.h>
#define __WAKE_SRC_FOR_IDLE_COMMON__ \
(R12_PCM_TIMER | \
R12_KP_IRQ_B | \
R12_APWDT_EVENT_B | \
R12_APXGPT1_EVENT_B | \
R12_CONN2AP_SPM_WAKEUP_B | \
R12_EINT_EVENT_B | \
R12_CONN_WDT_IRQ_B | \
R12_CCIF0_EVENT_B | \
R12_SSPM2SPM_WAKEUP_B | \
R12_SCP2SPM_WAKEUP_B | \
R12_ADSP2SPM_WAKEUP_B | \
R12_USBX_CDSC_B | \
R12_USBX_POWERDWN_B | \
R12_SYS_TIMER_EVENT_B | \
R12_EINT_EVENT_SECURE_B | \
R12_AFE_IRQ_MCU_B | \
R12_SYS_CIRQ_IRQ_B | \
R12_MD2AP_PEER_EVENT_B | \
R12_MD1_WDT_B | \
R12_CLDMA_EVENT_B | \
R12_REG_CPU_WAKEUP | \
R12_APUSYS_WAKE_HOST_B)
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
#else
#define WAKE_SRC_FOR_IDLE \
(__WAKE_SRC_FOR_IDLE_COMMON__ | \
R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl idle_spm_pwr = {
.wake_src = WAKE_SRC_FOR_IDLE,
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 1,
/* [3] */
.reg_spm_infra_req = 1,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] FIXME: default disable HW Auto S1 */
.reg_spm_ddr_en_req = 1,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 1,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 1,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 1,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 1,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 1,
/* [16] */
.reg_ufs_infra_req_mask_b = 1,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 1,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 1,
/* [19] */
.reg_ufs_ddr_en_mask_b = 1,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0x17,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 0,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 0,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xC1282203,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
};
struct spm_lp_scen idle_spm_lp = {
.pwrctrl = &idle_spm_pwr,
};
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
spm_idle_conduct fn)
{
unsigned int src_req = 0;
if (fn != NULL) {
fn(&idle_spm_lp, &src_req);
}
return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
}
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status)
{
spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
}
void mt_spm_idle_generic_init(void)
{
spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h
+17
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_IDLE_H
#define MT_SPM_IDLE_H
typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
unsigned int *resource_req);
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
spm_idle_conduct fn);
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status);
void mt_spm_idle_generic_init(void);
#endif /* MT_SPM_IDLE_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c
+550
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <assert.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <platform_def.h>
#include <plat_pm.h>
/**************************************
* Define and Declare
**************************************/
#define ROOT_CORE_ADDR_OFFSET 0x20000000
#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
#define SPM_INIT_DONE_US 20
#define SPM_WAKEUP_REASON_MISSING 0xdeaddead
static unsigned int mt_spm_bblpm_cnt;
const char *wakeup_src_str[32] = {
[0] = "PCM_TIMER",
[1] = "RESERVED_DEBUG_B",
[2] = "KEYPAD",
[3] = "APWDT",
[4] = "APXGPT",
[5] = "MSDC",
[6] = "EINT",
[7] = "IRRX",
[8] = "ETHERNET_QOS",
[9] = "RESERVE0",
[10] = "SSPM",
[11] = "SCP",
[12] = "ADSP",
[13] = "SPM_WDT",
[14] = "USB_U2",
[15] = "USB_TOP",
[16] = "SYS_TIMER",
[17] = "EINT_SECURE",
[18] = "HDMI",
[19] = "RESERVE1",
[20] = "AFE",
[21] = "THERMAL",
[22] = "SYS_CIRQ",
[23] = "NNA2INFRA",
[24] = "CSYSPWREQ",
[25] = "RESERVE2",
[26] = "PCIE",
[27] = "SEJ",
[28] = "SPM_CPU_WAKEUPEVENT",
[29] = "APUSYS",
[30] = "RESERVE3",
[31] = "RESERVE4",
};
/**************************************
* Function and API
**************************************/
wake_reason_t __spm_output_wake_reason(int state_id,
const struct wake_status *wakesta)
{
uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
char *spm_26m_sta = NULL;
wake_reason_t wr = WR_UNKNOWN;
if (wakesta == NULL) {
return WR_UNKNOWN;
}
spm_26m_sta = ((wakesta->debug_flag & SPM_DBG_DEBUG_IDX_26M_SLEEP) == 0U) ? "on" : "off";
if (wakesta->abort != 0U) {
ERROR("spmfw flow is aborted: 0x%x, timer_out = %u, 26M(%s)\n",
wakesta->abort, wakesta->timer_out, spm_26m_sta);
} else if (wakesta->r12 == SPM_WAKEUP_REASON_MISSING) {
WARN("cannot find wake up reason, timer_out = %u, 26M(%s)\n",
wakesta->timer_out, spm_26m_sta);
} else {
for (i = 0U; i < 32U; i++) {
if ((wakesta->r12 & (1U << i)) != 0U) {
INFO("wake up by %s, timer_out = %u, 26M(%s)\n",
wakeup_src_str[i], wakesta->timer_out, spm_26m_sta);
wr = WR_WAKE_SRC;
break;
}
}
}
INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
wakesta->debug_flag1);
INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
wakesta->md32pcm_event_sta, wakesta->idle_sta,
wakesta->cg_check_sta);
INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
mmio_read_32(SYS_TIMER_VALUE_H));
if (wakesta->timer_out != 0U) {
bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
}
return wr;
}
void __spm_set_cpu_status(unsigned int cpu)
{
uint32_t root_core_addr;
if (cpu < 8U) {
mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
root_core_addr += ROOT_CORE_ADDR_OFFSET;
mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
/* Notify MCUPM that preferred cpu wakeup */
mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
} else {
ERROR("%s: error cpu number %d\n", __func__, cpu);
}
}
void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
unsigned int resource_usage)
{
uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
1 : pwrctrl->reg_spm_apsrc_req;
uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
1 : pwrctrl->reg_spm_ddr_en_req;
uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
1 : pwrctrl->reg_spm_vrf18_req;
uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
1 : pwrctrl->reg_spm_infra_req;
uint8_t f26m_req = ((resource_usage &
(MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
1 : pwrctrl->reg_spm_f26m_req;
mmio_write_32(SPM_SRC_REQ,
((apsrc_req & 0x1) << 0) |
((f26m_req & 0x1) << 1) |
((infra_req & 0x1) << 3) |
((vrf18_req & 0x1) << 4) |
((ddr_en_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
}
void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
mmio_write_32(SPM_AP_STANDBY_CON,
((pwrctrl->reg_wfi_op & 0x1) << 0) |
((pwrctrl->reg_wfi_type & 0x1) << 1) |
((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
/* SPM_SRC_REQ */
mmio_write_32(SPM_SRC_REQ,
((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
/* SPM_SRC_MASK */
mmio_write_32(SPM_SRC_MASK,
((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
/* SPM_SRC2_MASK */
mmio_write_32(SPM_SRC2_MASK,
((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
/* SPM_SRC3_MASK */
mmio_write_32(SPM_SRC3_MASK,
((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
/* Mask MCUSYS request since SOC HW would check it */
mmio_write_32(SPM_SRC4_MASK, 0x1fc0000);
/* SPM_WAKEUP_EVENT_MASK */
mmio_write_32(SPM_WAKEUP_EVENT_MASK,
((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
/* SPM_WAKEUP_EVENT_EXT_MASK */
mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
/* Auto-gen End */
}
void __spm_disable_pcm_timer(void)
{
mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
}
void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
uint32_t val, mask;
/* toggle event counter clear */
mmio_setbits_32(PCM_CON1,
SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
/* toggle for reset SYS TIMER start point */
mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
if (pwrctrl->timer_val_cust == 0U) {
val = pwrctrl->timer_val;
} else {
val = pwrctrl->timer_val_cust;
}
mmio_write_32(PCM_TIMER_VAL, val);
mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
/* unmask AP wakeup source */
if (pwrctrl->wake_src_cust == 0U) {
mask = pwrctrl->wake_src;
} else {
mask = pwrctrl->wake_src_cust;
}
mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
/* unmask SPM ISR (keep TWAM setting) */
mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
/* toggle event counter clear */
mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
SPM_REGWR_CFG_KEY);
/* toggle for reset SYS TIMER start point */
mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
}
void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
{
/* set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0U) {
pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
}
if (pwrctrl->pcm_flags_cust_set != 0U) {
pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
}
if (pwrctrl->pcm_flags1_cust_clr != 0U) {
pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
}
if (pwrctrl->pcm_flags1_cust_set != 0U) {
pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
}
mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
}
void __spm_get_wakeup_status(struct wake_status *wakesta,
unsigned int ext_status)
{
wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
mmio_write_32(PCM_WDT_LATCH_SPARE_0,
wakesta->tr.comm.debug_flag);
}
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
/* record below spm info for debug */
wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
/* backup of SPM_WAKEUP_MISC */
wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
/* get sleep time, backup of PCM_TIMER_OUT */
wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
/* get other SYS and co-clock status */
wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
/* get HW CG check status */
wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
/* get debug flag for PCM execution check */
wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
/* get backup SW flag status */
wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
/* get ISR status */
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
/* get SW flag status */
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
/* get CLK SETTLE */
wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
/* check abort */
wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
(wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
}
void __spm_clean_after_wakeup(void)
{
mmio_write_32(SPM_BK_WAKE_EVENT,
mmio_read_32(SPM_WAKEUP_STA) |
mmio_read_32(SPM_BK_WAKE_EVENT));
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
/*
* clean wakeup event raw status (for edge trigger event)
* bit[28] for cpu wake up event
*/
mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
/* clean ISR status (except TWAM) */
mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
}
void __spm_set_pcm_wdt(int en)
{
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
SPM_REGWR_CFG_KEY);
if (en == 1) {
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
SPM_REGWR_CFG_KEY);
if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
}
mmio_write_32(PCM_WDT_VAL,
mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_setbits_32(PCM_CON1,
SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
}
}
void __spm_send_cpu_wakeup_event(void)
{
/* SPM will clear SPM_CPU_WAKEUP_EVENT */
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
}
void __spm_ext_int_wakeup_req_clr(void)
{
mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
/* Clear spm2mcupm wakeup interrupt status */
mmio_write_32(SPM2CPUEB_CON, 0);
}
void __spm_xo_soc_bblpm(int en)
{
if (en == 1) {
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
assert(mt_spm_bblpm_cnt == 0);
mt_spm_bblpm_cnt += 1;
} else {
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
mt_spm_bblpm_cnt -= 1;
}
}
void __spm_hw_s1_state_monitor(int en, unsigned int *status)
{
unsigned int reg;
reg = mmio_read_32(SPM_ACK_CHK_CON_3);
if (en == 1) {
reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
reg |= SPM_ACK_CHK_3_CON_EN;
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
} else {
if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
(status != NULL)) {
*status |= SPM_INTERNAL_STATUS_HW_S1;
}
mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
SPM_ACK_CHK_3_CON_CLR_ALL);
}
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h
+583
View File
@@ -0,0 +1,583 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_INTERNAL_H
#define MT_SPM_INTERNAL_H
#include "mt_spm.h"
/**************************************
* Config and Parameter
**************************************/
#define POWER_ON_VAL0_DEF 0x0000F100
#define POWER_ON_VAL1_DEF 0x80015860
#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
/**************************************
* Define and Declare
**************************************/
/* PCM_PWR_IO_EN */
#define PCM_PWRIO_EN_R0 (1U << 0)
#define PCM_PWRIO_EN_R7 (1U << 7)
#define PCM_RF_SYNC_R0 (1U << 16)
#define PCM_RF_SYNC_R6 (1U << 22)
#define PCM_RF_SYNC_R7 (1U << 23)
/* SPM_SWINT */
#define PCM_SW_INT0 (1U << 0)
#define PCM_SW_INT1 (1U << 1)
#define PCM_SW_INT2 (1U << 2)
#define PCM_SW_INT3 (1U << 3)
#define PCM_SW_INT4 (1U << 4)
#define PCM_SW_INT5 (1U << 5)
#define PCM_SW_INT6 (1U << 6)
#define PCM_SW_INT7 (1U << 7)
#define PCM_SW_INT8 (1U << 8)
#define PCM_SW_INT9 (1U << 9)
#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
PCM_SW_INT0)
/* SPM_AP_STANDBY_CON */
#define WFI_OP_AND 1
#define WFI_OP_OR 0
/* SPM_IRQ_MASK */
#define ISRM_TWAM (1U << 2)
#define ISRM_PCM_RETURN (1U << 3)
#define ISRM_RET_IRQ0 (1U << 8)
#define ISRM_RET_IRQ1 (1U << 9)
#define ISRM_RET_IRQ2 (1U << 10)
#define ISRM_RET_IRQ3 (1U << 11)
#define ISRM_RET_IRQ4 (1U << 12)
#define ISRM_RET_IRQ5 (1U << 13)
#define ISRM_RET_IRQ6 (1U << 14)
#define ISRM_RET_IRQ7 (1U << 15)
#define ISRM_RET_IRQ8 (1U << 16)
#define ISRM_RET_IRQ9 (1U << 17)
#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
(ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
(ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
(ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
(ISRM_RET_IRQ1))
#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
/* SPM_IRQ_STA */
#define ISRS_TWAM (1U << 2)
#define ISRS_PCM_RETURN (1U << 3)
#define ISRC_TWAM ISRS_TWAM
#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
/* SPM_WAKEUP_MISC */
#define WAKE_MISC_GIC_WAKEUP 0x3FF
#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
/* ABORT MASK for DEBUG FOORTPRINT */
#define DEBUG_ABORT_MASK \
(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
#define DEBUG_ABORT_MASK_1 \
(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10
struct pwr_ctrl {
uint32_t pcm_flags;
uint32_t pcm_flags_cust;
uint32_t pcm_flags_cust_set;
uint32_t pcm_flags_cust_clr;
uint32_t pcm_flags1;
uint32_t pcm_flags1_cust;
uint32_t pcm_flags1_cust_set;
uint32_t pcm_flags1_cust_clr;
uint32_t timer_val;
uint32_t timer_val_cust;
uint32_t timer_val_ramp_en;
uint32_t timer_val_ramp_en_sec;
uint32_t wake_src;
uint32_t wake_src_cust;
uint8_t wdt_disable;
/* SPM_AP_STANDBY_CON */
uint8_t reg_wfi_op;
uint8_t reg_wfi_type;
uint8_t reg_mp0_cputop_idle_mask;
uint8_t reg_mp1_cputop_idle_mask;
uint8_t reg_mcusys_idle_mask;
uint8_t reg_md_apsrc_1_sel;
uint8_t reg_md_apsrc_0_sel;
uint8_t reg_conn_apsrc_sel;
/* SPM_SRC_REQ */
uint8_t reg_spm_apsrc_req;
uint8_t reg_spm_f26m_req;
uint8_t reg_spm_infra_req;
uint8_t reg_spm_vrf18_req;
uint8_t reg_spm_ddr_en_req;
uint8_t reg_spm_dvfs_req;
uint8_t reg_spm_sw_mailbox_req;
uint8_t reg_spm_sspm_mailbox_req;
uint8_t reg_spm_adsp_mailbox_req;
uint8_t reg_spm_scp_mailbox_req;
/* SPM_SRC_MASK */
uint8_t reg_sspm_srcclkena_0_mask_b;
uint8_t reg_sspm_infra_req_0_mask_b;
uint8_t reg_sspm_apsrc_req_0_mask_b;
uint8_t reg_sspm_vrf18_req_0_mask_b;
uint8_t reg_sspm_ddr_en_0_mask_b;
uint8_t reg_scp_srcclkena_mask_b;
uint8_t reg_scp_infra_req_mask_b;
uint8_t reg_scp_apsrc_req_mask_b;
uint8_t reg_scp_vrf18_req_mask_b;
uint8_t reg_scp_ddr_en_mask_b;
uint8_t reg_audio_dsp_srcclkena_mask_b;
uint8_t reg_audio_dsp_infra_req_mask_b;
uint8_t reg_audio_dsp_apsrc_req_mask_b;
uint8_t reg_audio_dsp_vrf18_req_mask_b;
uint8_t reg_audio_dsp_ddr_en_mask_b;
uint8_t reg_apu_srcclkena_mask_b;
uint8_t reg_apu_infra_req_mask_b;
uint8_t reg_apu_apsrc_req_mask_b;
uint8_t reg_apu_vrf18_req_mask_b;
uint8_t reg_apu_ddr_en_mask_b;
uint8_t reg_cpueb_srcclkena_mask_b;
uint8_t reg_cpueb_infra_req_mask_b;
uint8_t reg_cpueb_apsrc_req_mask_b;
uint8_t reg_cpueb_vrf18_req_mask_b;
uint8_t reg_cpueb_ddr_en_mask_b;
uint8_t reg_bak_psri_srcclkena_mask_b;
uint8_t reg_bak_psri_infra_req_mask_b;
uint8_t reg_bak_psri_apsrc_req_mask_b;
uint8_t reg_bak_psri_vrf18_req_mask_b;
uint8_t reg_bak_psri_ddr_en_mask_b;
/* SPM_SRC2_MASK */
uint8_t reg_msdc0_srcclkena_mask_b;
uint8_t reg_msdc0_infra_req_mask_b;
uint8_t reg_msdc0_apsrc_req_mask_b;
uint8_t reg_msdc0_vrf18_req_mask_b;
uint8_t reg_msdc0_ddr_en_mask_b;
uint8_t reg_msdc1_srcclkena_mask_b;
uint8_t reg_msdc1_infra_req_mask_b;
uint8_t reg_msdc1_apsrc_req_mask_b;
uint8_t reg_msdc1_vrf18_req_mask_b;
uint8_t reg_msdc1_ddr_en_mask_b;
uint8_t reg_msdc2_srcclkena_mask_b;
uint8_t reg_msdc2_infra_req_mask_b;
uint8_t reg_msdc2_apsrc_req_mask_b;
uint8_t reg_msdc2_vrf18_req_mask_b;
uint8_t reg_msdc2_ddr_en_mask_b;
uint8_t reg_ufs_srcclkena_mask_b;
uint8_t reg_ufs_infra_req_mask_b;
uint8_t reg_ufs_apsrc_req_mask_b;
uint8_t reg_ufs_vrf18_req_mask_b;
uint8_t reg_ufs_ddr_en_mask_b;
uint8_t reg_usb_srcclkena_mask_b;
uint8_t reg_usb_infra_req_mask_b;
uint8_t reg_usb_apsrc_req_mask_b;
uint8_t reg_usb_vrf18_req_mask_b;
uint8_t reg_usb_ddr_en_mask_b;
uint8_t reg_pextp_p0_srcclkena_mask_b;
uint8_t reg_pextp_p0_infra_req_mask_b;
uint8_t reg_pextp_p0_apsrc_req_mask_b;
uint8_t reg_pextp_p0_vrf18_req_mask_b;
uint8_t reg_pextp_p0_ddr_en_mask_b;
/* SPM_SRC3_MASK */
uint8_t reg_pextp_p1_srcclkena_mask_b;
uint8_t reg_pextp_p1_infra_req_mask_b;
uint8_t reg_pextp_p1_apsrc_req_mask_b;
uint8_t reg_pextp_p1_vrf18_req_mask_b;
uint8_t reg_pextp_p1_ddr_en_mask_b;
uint8_t reg_gce0_infra_req_mask_b;
uint8_t reg_gce0_apsrc_req_mask_b;
uint8_t reg_gce0_vrf18_req_mask_b;
uint8_t reg_gce0_ddr_en_mask_b;
uint8_t reg_gce1_infra_req_mask_b;
uint8_t reg_gce1_apsrc_req_mask_b;
uint8_t reg_gce1_vrf18_req_mask_b;
uint8_t reg_gce1_ddr_en_mask_b;
uint8_t reg_spm_srcclkena_reserved_mask_b;
uint8_t reg_spm_infra_req_reserved_mask_b;
uint8_t reg_spm_apsrc_req_reserved_mask_b;
uint8_t reg_spm_vrf18_req_reserved_mask_b;
uint8_t reg_spm_ddr_en_reserved_mask_b;
uint8_t reg_disp0_apsrc_req_mask_b;
uint8_t reg_disp0_ddr_en_mask_b;
uint8_t reg_disp1_apsrc_req_mask_b;
uint8_t reg_disp1_ddr_en_mask_b;
uint8_t reg_disp2_apsrc_req_mask_b;
uint8_t reg_disp2_ddr_en_mask_b;
uint8_t reg_disp3_apsrc_req_mask_b;
uint8_t reg_disp3_ddr_en_mask_b;
uint8_t reg_infrasys_apsrc_req_mask_b;
uint8_t reg_infrasys_ddr_en_mask_b;
uint8_t reg_cg_check_srcclkena_mask_b;
uint8_t reg_cg_check_apsrc_req_mask_b;
uint8_t reg_cg_check_vrf18_req_mask_b;
uint8_t reg_cg_check_ddr_en_mask_b;
/* SPM_SRC4_MASK */
uint32_t reg_mcusys_merge_apsrc_req_mask_b;
uint32_t reg_mcusys_merge_ddr_en_mask_b;
uint8_t reg_dramc_md32_infra_req_mask_b;
uint8_t reg_dramc_md32_vrf18_req_mask_b;
uint8_t reg_dramc_md32_ddr_en_mask_b;
uint8_t reg_dvfsrc_event_trigger_mask_b;
/* SPM_WAKEUP_EVENT_MASK2 */
uint8_t reg_sc_sw2spm_wakeup_mask_b;
uint8_t reg_sc_adsp2spm_wakeup_mask_b;
uint8_t reg_sc_sspm2spm_wakeup_mask_b;
uint8_t reg_sc_scp2spm_wakeup_mask_b;
uint8_t reg_csyspwrup_ack_mask;
uint8_t reg_csyspwrup_req_mask;
/* SPM_WAKEUP_EVENT_MASK */
uint32_t reg_wakeup_event_mask;
/* SPM_WAKEUP_EVENT_EXT_MASK */
uint32_t reg_ext_wakeup_event_mask;
};
/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
enum pwr_ctrl_enum {
PW_PCM_FLAGS,
PW_PCM_FLAGS_CUST,
PW_PCM_FLAGS_CUST_SET,
PW_PCM_FLAGS_CUST_CLR,
PW_PCM_FLAGS1,
PW_PCM_FLAGS1_CUST,
PW_PCM_FLAGS1_CUST_SET,
PW_PCM_FLAGS1_CUST_CLR,
PW_TIMER_VAL,
PW_TIMER_VAL_CUST,
PW_TIMER_VAL_RAMP_EN,
PW_TIMER_VAL_RAMP_EN_SEC,
PW_WAKE_SRC,
PW_WAKE_SRC_CUST,
PW_WAKELOCK_TIMER_VAL,
PW_WDT_DISABLE,
/* SPM_CLK_CON */
PW_REG_SRCCLKEN0_CTL,
PW_REG_SRCCLKEN1_CTL,
PW_REG_SPM_LOCK_INFRA_DCM,
PW_REG_SRCCLKEN_MASK,
PW_REG_MD1_C32RM_EN,
PW_REG_MD2_C32RM_EN,
PW_REG_CLKSQ0_SEL_CTRL,
PW_REG_CLKSQ1_SEL_CTRL,
PW_REG_SRCCLKEN0_EN,
PW_REG_SRCCLKEN1_EN,
PW_REG_SYSCLK0_SRC_MASK_B,
PW_REG_SYSCLK1_SRC_MASK_B,
/* SPM_AP_STANDBY_CON */
PW_REG_WFI_OP,
PW_REG_WFI_TYPE,
PW_REG_MP0_CPUTOP_IDLE_MASK,
PW_REG_MP1_CPUTOP_IDLE_MASK,
PW_REG_MCUSYS_IDLE_MASK,
PW_REG_MD_APSRC_1_SEL,
PW_REG_MD_APSRC_0_SEL,
PW_REG_CONN_APSRC_SEL,
/* SPM_SRC_REQ */
PW_REG_SPM_APSRC_REQ,
PW_REG_SPM_F26M_REQ,
PW_REG_SPM_INFRA_REQ,
PW_REG_SPM_VRF18_REQ,
PW_REG_SPM_DDR_EN_REQ,
PW_REG_SPM_DVFS_REQ,
PW_REG_SPM_SW_MAILBOX_REQ,
PW_REG_SPM_SSPM_MAILBOX_REQ,
PW_REG_SPM_ADSP_MAILBOX_REQ,
PW_REG_SPM_SCP_MAILBOX_REQ,
/* SPM_SRC_MASK */
PW_REG_MD_SRCCLKENA_0_MASK_B,
PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
PW_REG_MD_APSRC_REQ_0_MASK_B,
PW_REG_MD_VRF18_REQ_0_MASK_B,
PW_REG_MD_DDR_EN_0_MASK_B,
PW_REG_MD_SRCCLKENA_1_MASK_B,
PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
PW_REG_MD_APSRC_REQ_1_MASK_B,
PW_REG_MD_VRF18_REQ_1_MASK_B,
PW_REG_MD_DDR_EN_1_MASK_B,
PW_REG_CONN_SRCCLKENA_MASK_B,
PW_REG_CONN_SRCCLKENB_MASK_B,
PW_REG_CONN_INFRA_REQ_MASK_B,
PW_REG_CONN_APSRC_REQ_MASK_B,
PW_REG_CONN_VRF18_REQ_MASK_B,
PW_REG_CONN_DDR_EN_MASK_B,
PW_REG_CONN_VFE28_MASK_B,
PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
PW_REG_INFRASYS_APSRC_REQ_MASK_B,
PW_REG_INFRASYS_DDR_EN_MASK_B,
PW_REG_MD32_SRCCLKENA_MASK_B,
PW_REG_MD32_INFRA_REQ_MASK_B,
PW_REG_MD32_APSRC_REQ_MASK_B,
PW_REG_MD32_VRF18_REQ_MASK_B,
PW_REG_MD32_DDR_EN_MASK_B,
/* SPM_SRC2_MASK */
PW_REG_SCP_SRCCLKENA_MASK_B,
PW_REG_SCP_INFRA_REQ_MASK_B,
PW_REG_SCP_APSRC_REQ_MASK_B,
PW_REG_SCP_VRF18_REQ_MASK_B,
PW_REG_SCP_DDR_EN_MASK_B,
PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
PW_REG_UFS_SRCCLKENA_MASK_B,
PW_REG_UFS_INFRA_REQ_MASK_B,
PW_REG_UFS_APSRC_REQ_MASK_B,
PW_REG_UFS_VRF18_REQ_MASK_B,
PW_REG_UFS_DDR_EN_MASK_B,
PW_REG_DISP0_APSRC_REQ_MASK_B,
PW_REG_DISP0_DDR_EN_MASK_B,
PW_REG_DISP1_APSRC_REQ_MASK_B,
PW_REG_DISP1_DDR_EN_MASK_B,
PW_REG_GCE_INFRA_REQ_MASK_B,
PW_REG_GCE_APSRC_REQ_MASK_B,
PW_REG_GCE_VRF18_REQ_MASK_B,
PW_REG_GCE_DDR_EN_MASK_B,
PW_REG_APU_SRCCLKENA_MASK_B,
PW_REG_APU_INFRA_REQ_MASK_B,
PW_REG_APU_APSRC_REQ_MASK_B,
PW_REG_APU_VRF18_REQ_MASK_B,
PW_REG_APU_DDR_EN_MASK_B,
PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
PW_REG_CG_CHECK_DDR_EN_MASK_B,
/* SPM_SRC3_MASK */
PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
PW_REG_SW2SPM_INT0_MASK_B,
PW_REG_SW2SPM_INT1_MASK_B,
PW_REG_SW2SPM_INT2_MASK_B,
PW_REG_SW2SPM_INT3_MASK_B,
PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
PW_REG_CSYSPWRREQ_MASK,
PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
PW_REG_MCUPM_SRCCLKENA_MASK_B,
PW_REG_MCUPM_INFRA_REQ_MASK_B,
PW_REG_MCUPM_APSRC_REQ_MASK_B,
PW_REG_MCUPM_VRF18_REQ_MASK_B,
PW_REG_MCUPM_DDR_EN_MASK_B,
PW_REG_MSDC0_SRCCLKENA_MASK_B,
PW_REG_MSDC0_INFRA_REQ_MASK_B,
PW_REG_MSDC0_APSRC_REQ_MASK_B,
PW_REG_MSDC0_VRF18_REQ_MASK_B,
PW_REG_MSDC0_DDR_EN_MASK_B,
PW_REG_MSDC1_SRCCLKENA_MASK_B,
PW_REG_MSDC1_INFRA_REQ_MASK_B,
PW_REG_MSDC1_APSRC_REQ_MASK_B,
PW_REG_MSDC1_VRF18_REQ_MASK_B,
PW_REG_MSDC1_DDR_EN_MASK_B,
/* SPM_SRC4_MASK */
PW_CCIF_EVENT_MASK_B,
PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
PW_REG_BAK_PSRI_DDR_EN_MASK_B,
PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
PW_REG_DRAMC0_MD32_WAKEUP_MASK,
PW_REG_DRAMC1_MD32_WAKEUP_MASK,
/* SPM_SRC5_MASK */
PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
/* SPM_WAKEUP_EVENT_MASK */
PW_REG_WAKEUP_EVENT_MASK,
/* SPM_WAKEUP_EVENT_EXT_MASK */
PW_REG_EXT_WAKEUP_EVENT_MASK,
PW_MAX_COUNT,
};
#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
#define SPM_ACK_CHK_3_HW_S1_CNT 1
#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
#define SPM_ACK_CHK_3_CON_EN 0x110
#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
#define SPM_ACK_CHK_3_CON_RESULT 0x8000
struct wake_status_trace_comm {
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
uint32_t timer_out; /* SPM_BK_PCM_TIMER */
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
uint32_t r12; /* SPM_SW_RSV_0 */
uint32_t r13; /* PCM_REG13_DATA */
uint32_t req_sta0; /* SRC_REQ_STA_0 */
uint32_t req_sta1; /* SRC_REQ_STA_1 */
uint32_t req_sta2; /* SRC_REQ_STA_2 */
uint32_t req_sta3; /* SRC_REQ_STA_3 */
uint32_t req_sta4; /* SRC_REQ_STA_4 */
uint32_t raw_sta; /* SPM_WAKEUP_STA */
uint32_t times_h; /* timestamp high bits */
uint32_t times_l; /* timestamp low bits */
uint32_t resumetime; /* timestamp low bits */
};
struct wake_status_trace {
struct wake_status_trace_comm comm;
};
struct wake_status {
struct wake_status_trace tr;
uint32_t r12; /* SPM_BK_WAKE_EVENT */
uint32_t r12_ext; /* SPM_WAKEUP_STA */
uint32_t raw_sta; /* SPM_WAKEUP_STA */
uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */
uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
uint32_t src_req; /* SPM_SRC_REQ */
uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
uint32_t timer_out; /* SPM_BK_PCM_TIMER */
uint32_t r13; /* PCM_REG13_DATA */
uint32_t idle_sta; /* SUBSYS_IDLE_STA */
uint32_t req_sta0; /* SRC_REQ_STA_0 */
uint32_t req_sta1; /* SRC_REQ_STA_1 */
uint32_t req_sta2; /* SRC_REQ_STA_2 */
uint32_t req_sta3; /* SRC_REQ_STA_3 */
uint32_t req_sta4; /* SRC_REQ_STA_4 */
uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
uint32_t isr; /* SPM_IRQ_STA */
uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
uint32_t clk_settle; /* SPM_CLK_SETTLE */
uint32_t abort;
};
struct spm_lp_scen {
struct pcm_desc *pcmdesc;
struct pwr_ctrl *pwrctrl;
};
extern struct spm_lp_scen __spm_vcorefs;
extern void __spm_set_cpu_status(unsigned int cpu);
extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
extern void __spm_init_pcm_register(void);
extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
unsigned int resource_usage);
extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
extern void __spm_disable_pcm_timer(void);
extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
extern void __spm_send_cpu_wakeup_event(void);
extern void __spm_get_wakeup_status(struct wake_status *wakesta,
unsigned int ext_status);
extern void __spm_clean_after_wakeup(void);
extern wake_reason_t
__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
extern void
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
const struct pwr_ctrl *src_pwr_ctrl);
extern void __spm_set_pcm_wdt(int en);
extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
extern void __spm_ext_int_wakeup_req_clr(void);
extern void __spm_xo_soc_bblpm(int en);
static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
uint32_t flags)
{
if (pwrctrl->pcm_flags_cust == 0U) {
pwrctrl->pcm_flags = flags;
} else {
pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
}
}
static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
uint32_t flags)
{
if (pwrctrl->pcm_flags1_cust == 0U) {
pwrctrl->pcm_flags1 = flags;
} else {
pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
}
}
extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
static inline void spm_hw_s1_state_monitor_resume(void)
{
__spm_hw_s1_state_monitor(1, NULL);
}
static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
{
__spm_hw_s1_state_monitor(0, status);
}
#endif /* MT_SPM_INTERNAL_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <plat_pm.h>
#include <platform_def.h>
/* PMIC_WRAP MT6359 */
#define VCORE_BASE_UV 40000
#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
#define SPM_DATA_SHIFT 16
#define BUCK_VGPU11_ELR0 0x15B4
#define TOP_SPI_CON0 0x0456
#define BUCK_TOP_CON1 0x1443
#define TOP_CON 0x0013
#define TOP_DIG_WPK 0x03a9
#define TOP_CON_LOCK 0x03a8
#define TOP_CLK_CON0 0x0134
struct pmic_wrap_cmd {
unsigned long cmd_addr;
unsigned long cmd_wdata;
};
struct pmic_wrap_setting {
enum pmic_wrap_phase_id phase;
struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
struct {
struct {
unsigned long cmd_addr;
unsigned long cmd_wdata;
} _[NR_PMIC_WRAP_CMD];
const int nr_idx;
} set[NR_PMIC_WRAP_PHASE];
};
static struct pmic_wrap_setting pw = {
.phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
.addr = { {0UL, 0UL} },
.set[PMIC_WRAP_PHASE_ALLINONE] = {
._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
._[CMD_4] = {TOP_SPI_CON0, 0x1,},
._[CMD_5] = {TOP_SPI_CON0, 0x0,},
._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
._[CMD_8] = {TOP_CON, 0x3,},
._[CMD_9] = {TOP_CON, 0x0,},
._[CMD_10] = {TOP_DIG_WPK, 0x63,},
._[CMD_11] = {TOP_CON_LOCK, 0x15,},
._[CMD_12] = {TOP_DIG_WPK, 0x0,},
._[CMD_13] = {TOP_CON_LOCK, 0x0,},
._[CMD_14] = {TOP_CLK_CON0, 0x40,},
._[CMD_15] = {TOP_CLK_CON0, 0x0,},
.nr_idx = NR_IDX_ALL,
},
};
void _mt_spm_pmic_table_init(void)
{
struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
{(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
{(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
{(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
{(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
{(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
{(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
{(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
{(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
{(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
{(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
{(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
{(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
{(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
{(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
{(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
{(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
};
memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
}
void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
{
uint32_t idx, addr, data;
if (phase >= NR_PMIC_WRAP_PHASE) {
return;
}
if (pw.phase == phase) {
return;
}
if (pw.addr[0].cmd_addr == 0UL) {
_mt_spm_pmic_table_init();
}
pw.phase = phase;
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
data = pw.set[phase]._[idx].cmd_wdata;
mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
}
}
void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
uint32_t cmd_wdata)
{
uint32_t addr;
if (phase >= NR_PMIC_WRAP_PHASE) {
return;
}
if (idx >= pw.set[phase].nr_idx) {
return;
}
pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
if (pw.phase == phase) {
addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
}
}
uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
{
if (phase >= NR_PMIC_WRAP_PHASE) {
return 0UL;
}
if (idx >= pw.set[phase].nr_idx) {
return 0UL;
}
return pw.set[phase]._[idx].cmd_wdata;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************
* Auto generated by DE, please DO NOT modify this file directly.
*****************************************************************/
#ifndef MT_SPM_PMIC_WRAP_H
#define MT_SPM_PMIC_WRAP_H
enum pmic_wrap_phase_id {
PMIC_WRAP_PHASE_ALLINONE,
NR_PMIC_WRAP_PHASE,
};
/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
enum {
CMD_0, /* 0x0 */
CMD_1, /* 0x1 */
CMD_2, /* 0x2 */
CMD_3, /* 0x3 */
CMD_4, /* 0x4 */
CMD_5, /* 0x5 */
CMD_6, /* 0x6 */
CMD_7, /* 0x7 */
CMD_8, /* 0x8 */
CMD_9, /* 0x9 */
CMD_10, /* 0xA */
CMD_11, /* 0xB */
CMD_12, /* 0xC */
CMD_13, /* 0xD */
CMD_14, /* 0xE */
CMD_15, /* 0xF */
NR_IDX_ALL,
};
/* APIs */
extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx, uint32_t cmd_wdata);
extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx);
#endif /* MT_SPM_PMIC_WRAP_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h
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source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_RESOURCE_REQ_H
#define MT_SPM_RESOURCE_REQ_H
/* SPM resource request internal bit */
#define MT_SPM_BIT_XO_FPM 0
#define MT_SPM_BIT_26M 1
#define MT_SPM_BIT_INFRA 2
#define MT_SPM_BIT_SYSPLL 3
#define MT_SPM_BIT_DRAM_S0 4
#define MT_SPM_BIT_DRAM_S1 5
/* SPM resource request internal bit_mask */
#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
#endif /* MT_SPM_RESOURCE_REQ_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_internal.h>
#include <mt_spm_rc_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_resource_req.h>
#include <mt_spm_suspend.h>
#include <plat_pm.h>
#include <uart.h>
#define SPM_SUSPEND_SLEEP_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_SLEEP_PCM_FLAG1 0
#define SPM_SUSPEND_PCM_FLAG \
(SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_ENABLE_TIA_WORKAROUND | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_PCM_FLAG1 0
/* Suspend spm power control */
#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
(R12_PCM_TIMER | \
R12_KP_IRQ_B | \
R12_APWDT_EVENT_B | \
R12_CONN2AP_SPM_WAKEUP_B | \
R12_EINT_EVENT_B | \
R12_CONN_WDT_IRQ_B | \
R12_CCIF0_EVENT_B | \
R12_SSPM2SPM_WAKEUP_B | \
R12_SCP2SPM_WAKEUP_B | \
R12_USBX_CDSC_B | \
R12_USBX_POWERDWN_B | \
R12_SYS_TIMER_EVENT_B | \
R12_EINT_EVENT_SECURE_B | \
R12_SYS_CIRQ_IRQ_B | \
R12_MD2AP_PEER_EVENT_B | \
R12_MD1_WDT_B | \
R12_CLDMA_EVENT_B | \
R12_REG_CPU_WAKEUP | \
R12_APUSYS_WAKE_HOST_B)
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
#else
#define WAKE_SRC_FOR_SUSPEND \
(__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl suspend_ctrl = {
.wake_src = WAKE_SRC_FOR_SUSPEND,
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 0,
/* [3] */
.reg_spm_infra_req = 0,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] FIXME: default disable HW Auto S1*/
.reg_spm_ddr_en_req = 1,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 1,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 1,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 1,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 1,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 0,
/* [16] */
.reg_ufs_infra_req_mask_b = 0,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 0,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 0,
/* [19] */
.reg_ufs_ddr_en_mask_b = 0,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0x17,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0x17,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 0,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 0,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xC1382213,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
};
struct spm_lp_scen __spm_suspend = {
.pwrctrl = &suspend_ctrl,
};
int mt_spm_suspend_mode_set(int mode)
{
if (mode == MT_SPM_SUSPEND_SLEEP) {
suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
} else {
suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
}
return 0;
}
int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
unsigned int resource_req)
{
/* If FMAudio / ADSP is active, change to sleep suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
}
/* Notify MCUPM that device is going suspend flow */
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
/* Notify UART to sleep */
mt_uart_save();
return spm_conservation(state_id, ext_opand,
&__spm_suspend, resource_req);
}
void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
struct wake_status **status)
{
spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
/* Notify UART to wakeup */
mt_uart_restore();
/* Notify MCUPM that device leave suspend */
mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
/* If FMAudio / ADSP is active, change back to suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
}
}
void mt_spm_suspend_init(void)
{
spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h
+26
View File
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SUSPEND_H
#define MT_SPM_SUSPEND_H
#include <mt_spm_internal.h>
#define MCUPM_MBOX_OFFSET_PDN 0x1031FF88
#define MCUPM_POWER_DOWN 0x4D50444E
enum MT_SPM_SUSPEND_MODE {
MT_SPM_SUSPEND_SYSTEM_PDN,
MT_SPM_SUSPEND_SLEEP,
};
extern int mt_spm_suspend_mode_set(int mode);
extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
unsigned int reosuce_req);
extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
struct wake_status **status);
extern void mt_spm_suspend_init(void);
#endif /* MT_SPM_SUSPEND_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c
+526
View File
@@ -0,0 +1,526 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <string.h>
#include <common/debug.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include <mt_spm.h>
#include <mt_spm_internal.h>
#include <mt_spm_pmic_wrap.h>
#include <mt_spm_reg.h>
#include <mt_spm_vcorefs.h>
#include <mtk_plat_common.h>
#include <mtk_sip_svc.h>
#include <platform_def.h>
#define VCORE_MAX_OPP 4
#define DRAM_MAX_OPP 7
static bool spm_dvfs_init_done;
static bool dvfs_enable_done;
static int vcore_opp_0_uv = 750000;
static int vcore_opp_1_uv = 650000;
static int vcore_opp_2_uv = 600000;
static int vcore_opp_3_uv = 550000;
static struct reg_config dvfsrc_init_configs[] = {
{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
{ DVFSRC_DEBOUNCE_TIME, 0x19651965 },
{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
{ DVFSRC_LEVEL_MASK, 0x000EE000 },
{ DVFSRC_DDR_QOS0, 0x00000019 },
{ DVFSRC_DDR_QOS1, 0x00000026 },
{ DVFSRC_DDR_QOS2, 0x00000033 },
{ DVFSRC_DDR_QOS3, 0x0000003B },
{ DVFSRC_DDR_QOS4, 0x0000004C },
{ DVFSRC_DDR_QOS5, 0x00000066 },
{ DVFSRC_DDR_QOS6, 0x00660066 },
{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
{ DVFSRC_MD_LATENCY_IMPROVE, 0x00000040 },
{ DVFSRC_DDR_REQUEST, 0x00004321 },
{ DVFSRC_DDR_REQUEST3, 0x00000065 },
{ DVFSRC_DDR_ADD_REQUEST, 0x66543210 },
{ DVFSRC_HRT_REQUEST, 0x66654321 },
{ DVFSRC_DDR_REQUEST5, 0x54321000 },
{ DVFSRC_DDR_REQUEST7, 0x66000000 },
{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
{ DVFSRC_HRT_HIGH, 0x070804B0 },
{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
{ DVFSRC_HRT_LOW_2, 0x18A51182 },
{ DVFSRC_HRT_LOW_1, 0x0D680B7F },
{ DVFSRC_HRT_LOW, 0x070704AF },
{ DVFSRC_BASIC_CONTROL_3, 0x00000006 },
{ DVFSRC_INT_EN, 0x00000002 },
{ DVFSRC_QOS_EN, 0x0000407C },
{ DVFSRC_HRT_BW_BASE, 0x00000004 },
{ DVFSRC_PCIE_VCORE_REQ, 0x65908101 },
{ DVFSRC_CURRENT_FORCE, 0x00000001 },
{ DVFSRC_BASIC_CONTROL, 0x6698444B },
{ DVFSRC_BASIC_CONTROL, 0x6698054B },
{ DVFSRC_CURRENT_FORCE, 0x00000000 },
};
static struct pwr_ctrl vcorefs_ctrl = {
.wake_src = R12_REG_CPU_WAKEUP,
/* default VCORE DVFS is disabled */
.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS),
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 0,
/* [3] */
.reg_spm_infra_req = 0,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] FIXME: default disable HW Auto S1*/
.reg_spm_ddr_en_req = 1,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 1,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 1,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 1,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 1,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 1,
/* [16] */
.reg_ufs_infra_req_mask_b = 1,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 1,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 1,
/* [19] */
.reg_ufs_ddr_en_mask_b = 1,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0x11,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 0,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 0,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xEFFFFFFF,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
};
struct spm_lp_scen __spm_vcorefs = {
.pwrctrl = &vcorefs_ctrl,
};
static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
{
if (cmd < NR_IDX_ALL) {
mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
} else {
INFO("cmd out of range!\n");
}
}
void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
{
if (spm_dvfs_init_done == false) {
mmio_write_32(SPM_DVFS_MISC, (mmio_read_32(SPM_DVFS_MISC) &
~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
spm_dvfs_init_done = true;
}
}
void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
const struct pwr_ctrl *src_pwr_ctrl)
{
uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
SPM_FLAG_DISABLE_VCORE_DFS |
SPM_FLAG_ENABLE_VOLTAGE_BIN;
dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
(src_pwr_ctrl->pcm_flags & dvfs_mask);
if (dest_pwr_ctrl->pcm_flags_cust) {
dest_pwr_ctrl->pcm_flags_cust = (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
(src_pwr_ctrl->pcm_flags & dvfs_mask);
}
}
void spm_go_to_vcorefs(uint64_t spm_flags)
{
__spm_set_power_control(__spm_vcorefs.pwrctrl);
__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
__spm_send_cpu_wakeup_event();
}
uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3)
{
uint64_t ret = 0U;
uint64_t cmd = x1;
uint64_t spm_flags;
switch (cmd) {
case VCOREFS_SMC_CMD_0:
spm_dvfsfw_init(x2, x3);
break;
case VCOREFS_SMC_CMD_1:
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
if (x2 & SPM_FLAG_DISABLE_VCORE_DVS)
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
if (x2 & SPM_FLAG_DISABLE_VCORE_DFS)
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
spm_go_to_vcorefs(spm_flags);
break;
case VCOREFS_SMC_CMD_3:
spm_vcorefs_pwarp_cmd(x2, x3);
break;
case VCOREFS_SMC_CMD_2:
case VCOREFS_SMC_CMD_4:
case VCOREFS_SMC_CMD_5:
case VCOREFS_SMC_CMD_7:
default:
break;
}
return ret;
}
static void dvfsrc_init(void)
{
int i;
int count = ARRAY_SIZE(dvfsrc_init_configs);
if (dvfs_enable_done == false) {
for (i = 0; i < count; i++) {
mmio_write_32(dvfsrc_init_configs[i].offset,
dvfsrc_init_configs[i].val);
}
mmio_write_32(DVFSRC_QOS_EN, 0x0011007C);
dvfs_enable_done = true;
}
}
static void spm_vcorefs_vcore_setting(uint64_t flag)
{
spm_vcorefs_pwarp_cmd(3, __vcore_uv_to_pmic(vcore_opp_3_uv));
spm_vcorefs_pwarp_cmd(2, __vcore_uv_to_pmic(vcore_opp_2_uv));
spm_vcorefs_pwarp_cmd(1, __vcore_uv_to_pmic(vcore_opp_1_uv));
spm_vcorefs_pwarp_cmd(0, __vcore_uv_to_pmic(vcore_opp_0_uv));
}
int spm_vcorefs_get_vcore(unsigned int gear)
{
int ret_val;
switch (gear) {
case 3:
ret_val = vcore_opp_0_uv;
break;
case 2:
ret_val = vcore_opp_1_uv;
break;
case 1:
ret_val = vcore_opp_2_uv;
break;
case 0:
default:
ret_val = vcore_opp_3_uv;
break;
}
return ret_val;
}
uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3, u_register_t *x4)
{
uint64_t ret = 0U;
uint64_t cmd = x1;
uint64_t spm_flags;
switch (cmd) {
case VCOREFS_SMC_CMD_INIT:
/* vcore_dvfs init + kick */
spm_dvfsfw_init(0, 0);
spm_vcorefs_vcore_setting(x3 & 0xF);
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
if (x2 & 0x1) {
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
}
if (x2 & 0x2) {
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
}
spm_go_to_vcorefs(spm_flags);
dvfsrc_init();
*x4 = 0U;
break;
case VCOREFS_SMC_CMD_OPP_TYPE:
/* get dram type */
*x4 = 0U;
break;
case VCOREFS_SMC_CMD_FW_TYPE:
*x4 = 0U;
break;
case VCOREFS_SMC_CMD_GET_UV:
*x4 = spm_vcorefs_get_vcore(x2);
break;
case VCOREFS_SMC_CMD_GET_NUM_V:
*x4 = VCORE_MAX_OPP;
break;
case VCOREFS_SMC_CMD_GET_NUM_F:
*x4 = DRAM_MAX_OPP;
break;
default:
break;
}
return ret;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.h
+328
View File
@@ -0,0 +1,328 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __MT_SPM_VCOREFS__H__
#define __MT_SPM_VCOREFS__H__
int spm_vcorefs_get_vcore(unsigned int gear);
uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3,
u_register_t *x4);
enum vcorefs_smc_cmd {
VCOREFS_SMC_CMD_0 = 0,
VCOREFS_SMC_CMD_1,
VCOREFS_SMC_CMD_2,
VCOREFS_SMC_CMD_3,
VCOREFS_SMC_CMD_4,
/* check spmfw status */
VCOREFS_SMC_CMD_5,
/* get spmfw type */
VCOREFS_SMC_CMD_6,
/* get spm reg status */
VCOREFS_SMC_CMD_7,
NUM_VCOREFS_SMC_CMD,
};
enum vcorefs_smc_cmd_new {
VCOREFS_SMC_CMD_INIT = 0,
VCOREFS_SMC_CMD_KICK = 1,
VCOREFS_SMC_CMD_OPP_TYPE = 2,
VCOREFS_SMC_CMD_FW_TYPE = 3,
VCOREFS_SMC_CMD_GET_UV = 4,
VCOREFS_SMC_CMD_GET_FREQ = 5,
VCOREFS_SMC_CMD_GET_NUM_V = 6,
VCOREFS_SMC_CMD_GET_NUM_F = 7,
VCOREFS_SMC_CMD_FB_ACTION = 8,
/*chip specific setting */
VCOREFS_SMC_CMD_SET_FREQ = 16,
VCOREFS_SMC_CMD_SET_EFUSE = 17,
VCOREFS_SMC_CMD_GET_EFUSE = 18,
VCOREFS_SMC_CMD_DVFS_HOPPING = 19,
VCOREFS_SMC_CMD_DVFS_HOPPING_STATE = 20,
};
enum dvfsrc_channel {
DVFSRC_CHANNEL_1 = 1,
DVFSRC_CHANNEL_2,
DVFSRC_CHANNEL_3,
DVFSRC_CHANNEL_4,
NUM_DVFSRC_CHANNEL,
};
#define _VCORE_BASE_UV 400000
#define _VCORE_STEP_UV 6250
/* PMIC */
#define __vcore_pmic_to_uv(pmic) \
(((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV)
#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
struct reg_config {
uint32_t offset;
uint32_t val;
};
#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
#define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4)
#define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8)
#define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC)
#define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10)
#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
#define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18)
#define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C)
#define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20)
#define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24)
#define DVFSRC_EMI_REQUEST2 (DVFSRC_BASE + 0x28)
#define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x2C)
#define DVFSRC_EMI_REQUEST4 (DVFSRC_BASE + 0x30)
#define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x34)
#define DVFSRC_EMI_REQUEST6 (DVFSRC_BASE + 0x38)
#define DVFSRC_EMI_HRT (DVFSRC_BASE + 0x3C)
#define DVFSRC_EMI_HRT2 (DVFSRC_BASE + 0x40)
#define DVFSRC_EMI_HRT3 (DVFSRC_BASE + 0x44)
#define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x48)
#define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x4C)
#define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x50)
#define DVFSRC_EMI_MD2SPM0 (DVFSRC_BASE + 0x54)
#define DVFSRC_EMI_MD2SPM1 (DVFSRC_BASE + 0x58)
#define DVFSRC_EMI_MD2SPM2 (DVFSRC_BASE + 0x5C)
#define DVFSRC_EMI_MD2SPM0_T (DVFSRC_BASE + 0x60)
#define DVFSRC_EMI_MD2SPM1_T (DVFSRC_BASE + 0x64)
#define DVFSRC_EMI_MD2SPM2_T (DVFSRC_BASE + 0x68)
#define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x6C)
#define DVFSRC_VCORE_REQUEST2 (DVFSRC_BASE + 0x70)
#define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x74)
#define DVFSRC_VCORE_REQUEST4 (DVFSRC_BASE + 0x78)
#define DVFSRC_VCORE_HRT (DVFSRC_BASE + 0x7C)
#define DVFSRC_VCORE_HRT2 (DVFSRC_BASE + 0x80)
#define DVFSRC_VCORE_HRT3 (DVFSRC_BASE + 0x84)
#define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x88)
#define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x8C)
#define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x90)
#define DVFSRC_VCORE_MD2SPM0 (DVFSRC_BASE + 0x94)
#define DVFSRC_VCORE_MD2SPM1 (DVFSRC_BASE + 0x98)
#define DVFSRC_VCORE_MD2SPM2 (DVFSRC_BASE + 0x9C)
#define DVFSRC_VCORE_MD2SPM0_T (DVFSRC_BASE + 0xA0)
#define DVFSRC_VCORE_MD2SPM1_T (DVFSRC_BASE + 0xA4)
#define DVFSRC_VCORE_MD2SPM2_T (DVFSRC_BASE + 0xA8)
#define DVFSRC_MD_VSRAM_REMAP (DVFSRC_BASE + 0xBC)
#define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC0)
#define DVFSRC_INT (DVFSRC_BASE + 0xC4)
#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
#define DVFSRC_INT_CLR (DVFSRC_BASE + 0xCC)
#define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD0)
#define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD4)
#define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xD8)
#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
#define DVFSRC_DEBOUNCE_FOUR (DVFSRC_BASE + 0xF0)
#define DVFSRC_DEBOUNCE_RISE_FALL (DVFSRC_BASE + 0xF4)
#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
#define DVFSRC_MM_BW_0 (DVFSRC_BASE + 0x200)
#define DVFSRC_MM_BW_1 (DVFSRC_BASE + 0x204)
#define DVFSRC_MM_BW_2 (DVFSRC_BASE + 0x208)
#define DVFSRC_MM_BW_3 (DVFSRC_BASE + 0x20C)
#define DVFSRC_MM_BW_4 (DVFSRC_BASE + 0x210)
#define DVFSRC_MM_BW_5 (DVFSRC_BASE + 0x214)
#define DVFSRC_MM_BW_6 (DVFSRC_BASE + 0x218)
#define DVFSRC_MM_BW_7 (DVFSRC_BASE + 0x21C)
#define DVFSRC_MM_BW_8 (DVFSRC_BASE + 0x220)
#define DVFSRC_MM_BW_9 (DVFSRC_BASE + 0x224)
#define DVFSRC_MM_BW_10 (DVFSRC_BASE + 0x228)
#define DVFSRC_MM_BW_11 (DVFSRC_BASE + 0x22C)
#define DVFSRC_MM_BW_12 (DVFSRC_BASE + 0x230)
#define DVFSRC_MM_BW_13 (DVFSRC_BASE + 0x234)
#define DVFSRC_MM_BW_14 (DVFSRC_BASE + 0x238)
#define DVFSRC_MM_BW_15 (DVFSRC_BASE + 0x23C)
#define DVFSRC_MD_BW_0 (DVFSRC_BASE + 0x240)
#define DVFSRC_MD_BW_1 (DVFSRC_BASE + 0x244)
#define DVFSRC_MD_BW_2 (DVFSRC_BASE + 0x248)
#define DVFSRC_MD_BW_3 (DVFSRC_BASE + 0x24C)
#define DVFSRC_MD_BW_4 (DVFSRC_BASE + 0x250)
#define DVFSRC_MD_BW_5 (DVFSRC_BASE + 0x254)
#define DVFSRC_MD_BW_6 (DVFSRC_BASE + 0x258)
#define DVFSRC_MD_BW_7 (DVFSRC_BASE + 0x25C)
#define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x260)
#define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x264)
#define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x268)
#define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x26C)
#define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x270)
#define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x274)
#define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x278)
#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
#define DVFSRC_MD_BW_URG (DVFSRC_BASE + 0x284)
#define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x290)
#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
#define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x304)
#define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x308)
#define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x30C)
#define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x310)
#define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x314)
#define DVFSRC_LEVEL_MASK (DVFSRC_BASE + 0x318)
#define DVFSRC_DEFAULT_OPP (DVFSRC_BASE + 0x31C)
#define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x500)
#define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x504)
#define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x508)
#define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x50C)
#define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x510)
#define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x514)
#define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x518)
#define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x51C)
#define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x520)
#define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524)
#define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x528)
#define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x52C)
#define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x530)
#define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x534)
#define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x538)
#define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x53C)
#define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x540)
#define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x544)
#define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x548)
#define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600)
#define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x604)
#define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x608)
#define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x60C)
#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
#define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x630)
#define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x700)
#define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x704)
#define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x708)
#define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x70C)
#define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x710)
#define DVFSRC_DEBUG_STA_5 (DVFSRC_BASE + 0x714)
#define DVFSRC_EMI_REQUEST7 (DVFSRC_BASE + 0x800)
#define DVFSRC_EMI_HRT_1 (DVFSRC_BASE + 0x804)
#define DVFSRC_EMI_HRT2_1 (DVFSRC_BASE + 0x808)
#define DVFSRC_EMI_HRT3_1 (DVFSRC_BASE + 0x80C)
#define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x810)
#define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x814)
#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
#define DVFSRC_DDR_HRT (DVFSRC_BASE + 0xA1C)
#define DVFSRC_DDR_HRT2 (DVFSRC_BASE + 0xA20)
#define DVFSRC_DDR_HRT3 (DVFSRC_BASE + 0xA24)
#define DVFSRC_DDR_HRT_1 (DVFSRC_BASE + 0xA28)
#define DVFSRC_DDR_HRT2_1 (DVFSRC_BASE + 0xA2C)
#define DVFSRC_DDR_HRT3_1 (DVFSRC_BASE + 0xA30)
#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
#define DVFSRC_DDR_MD2SPM0 (DVFSRC_BASE + 0xA48)
#define DVFSRC_DDR_MD2SPM1 (DVFSRC_BASE + 0xA4C)
#define DVFSRC_DDR_MD2SPM2 (DVFSRC_BASE + 0xA50)
#define DVFSRC_DDR_MD2SPM0_T (DVFSRC_BASE + 0xA54)
#define DVFSRC_DDR_MD2SPM1_T (DVFSRC_BASE + 0xA58)
#define DVFSRC_DDR_MD2SPM2_T (DVFSRC_BASE + 0xA5C)
#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
#define DVSFRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0xA64)
#define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0xA68)
#define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0xA6C)
#define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0xA70)
#define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0xA74)
#define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0xA78)
#define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0xA7C)
#define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0xA80)
#define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0xA84)
#define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0xA88)
#define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0xA8C)
#define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0xA90)
#define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0xA94)
#define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0xA98)
#define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0xA9C)
#define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0xAA0)
#define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0xAA4)
#define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0xAA8)
#define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0xAAC)
#define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0xAB0)
#define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0xAB4)
#define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0xAB8)
#define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0xABC)
#define DVFSRC_HRT_REQ_BW_SW_REG (DVFSRC_BASE + 0xAC0)
#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
#define DVFSRC_VCORE_REQUEST5 (DVFSRC_BASE + 0xD20)
#define DVFSRC_VCORE_HRT_1 (DVFSRC_BASE + 0xD24)
#define DVFSRC_VCORE_HRT2_1 (DVFSRC_BASE + 0xD28)
#define DVFSRC_VCORE_HRT3_1 (DVFSRC_BASE + 0xD2C)
#define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xD30)
#define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xD34)
#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
#define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0xD40)
#define DVFSRC_CURRENT_LEVEL (DVFSRC_BASE + 0xD44)
#define DVFSRC_TARGET_LEVEL (DVFSRC_BASE + 0xD48)
#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
#define DVFSRC_TARGET_FORCE (DVFSRC_BASE + 0xD70)
#define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0xD74)
#endif /* __MT_SPM_VCOREFS__H__ */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SSPM_NOTIFIER_H
#define MT_SPM_SSPM_NOTIFIER_H
enum MT_SPM_SSPM_NOTIFY_ID {
MT_SPM_NOTIFY_LP_ENTER,
MT_SPM_NOTIFY_LP_LEAVE,
};
int mt_spm_sspm_notify(int type, unsigned int lp_mode);
static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
{
return mt_spm_sspm_notify(type, lp_mode);
}
#endif /* MT_SPM_SSPM_NOTIFIER_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SSPM_INTC_H
#define MT_SPM_SSPM_INTC_H
#include <mt_spm_reg.h>
#define MT_SPM_SSPM_INTC_SEL_0 0x10
#define MT_SPM_SSPM_INTC_SEL_1 0x20
#define MT_SPM_SSPM_INTC_SEL_2 0x40
#define MT_SPM_SSPM_INTC_SEL_3 0x80
#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
(((0x10 << id) | (sg << id)) & 0xff)
#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
#define DO_SPM_SSPM_LP_SUSPEND() \
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
#define DO_SPM_SSPM_LP_RESUME() \
mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
#endif /* MT_SPM_SSPM_INTC_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <lib/mmio.h>
#include <mt_spm_notifier.h>
#include <mt_spm_sspm_intc.h>
#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
int mt_spm_sspm_notify(int type, unsigned int lp_mode)
{
switch (type) {
case MT_SPM_NOTIFY_LP_ENTER:
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
DO_SPM_SSPM_LP_SUSPEND();
break;
case MT_SPM_NOTIFY_LP_LEAVE:
mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
DO_SPM_SSPM_LP_RESUME();
break;
default:
break;
}
return 0;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/pcm_def.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PCM_DEF_H
#define PCM_DEF_H
/*
* Auto generated by DE, please DO NOT modify this file directly.
*/
/* --- R0 Define --- */
#define R0_SC_26M_CK_OFF (1U << 0)
#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
#define R0_SC_MEM_CK_OFF (1U << 2)
#define R0_SC_AXI_CK_OFF (1U << 3)
#define R0_SC_DR_SRAM_LOAD (1U << 4)
#define R0_SC_MD26M_CK_OFF (1U << 5)
#define R0_SC_DPY_MODE_SW (1U << 6)
#define R0_SC_DMSUS_OFF (1U << 7)
#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
#define R0_SC_DR_SRAM_RESTORE (1U << 9)
#define R0_SC_MPLLOUT_OFF (1U << 10)
#define R0_SC_TX_TRACKING_DIS (1U << 11)
#define R0_SC_DPY_DLL_EN (1U << 12)
#define R0_SC_DPY_DLL_CK_EN (1U << 13)
#define R0_SC_DPY_VREF_EN (1U << 14)
#define R0_SC_PHYPLL_EN (1U << 15)
#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
#define R0_SC_MPLL_OFF (1U << 18)
#define R0_SC_SHU_RESTORE (1U << 19)
#define R0_SC_CKSQ0_OFF (1U << 20)
#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
#define R0_SC_DR_SHU_EN (1U << 22)
#define R0_SC_DPHY_PRECAL_UP (1U << 23)
#define R0_SC_MPLL_S_OFF (1U << 24)
#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
#define R0_SC_PHYPLL_SHU_EN (1U << 26)
#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
#define R0_SC_PHYPLL_MODE_SW (1U << 28)
#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
/* --- R7 Define --- */
#define R7_PWRAP_SLEEP_REQ (1U << 0)
#define R7_EMI_CLK_OFF_REQ (1U << 1)
#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
#define R7_SPM_CK_UPDATE (1U << 3)
#define R7_SPM_CK_SEL0 (1U << 4)
#define R7_SPM_CK_SEL1 (1U << 5)
#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
#define R7_SC_26M_CK_SEL (1U << 8)
#define R7_PCM_TIMER_SET (1U << 9)
#define R7_PCM_TIMER_CLR (1U << 10)
#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
#define R7_CSYSPWRUPACK (1U << 12)
#define R7_PCM_IM_SLP_EN (1U << 13)
#define R7_SRCCLKENO0 (1U << 14)
#define R7_FORCE_DDR_EN_WAKE (1U << 15)
#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
#define R7_SC_AXI_DCM_DIS (1U << 18)
#define R7_SC_FHC_PAUSE_MEM (1U << 19)
#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
#define R7_SRCCLKENO1 (1U << 21)
#define R7_PCM_WDT_KICK_P (1U << 22)
#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
#define R7_PMIC_IRQ_REQ_EN (1U << 26)
#define R7_FORCE_F26M_WAKE (1U << 27)
#define R7_FORCE_APSRC_WAKE (1U << 28)
#define R7_FORCE_INFRA_WAKE (1U << 29)
#define R7_FORCE_VRF18_WAKE (1U << 30)
#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
/* --- R12 Define --- */
#define R12_PCM_TIMER (1U << 0)
#define R12_TWAM_IRQ_B (1U << 1)
#define R12_KP_IRQ_B (1U << 2)
#define R12_APWDT_EVENT_B (1U << 3)
#define R12_APXGPT1_EVENT_B (1U << 4)
#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
#define R12_EINT_EVENT_B (1U << 6)
#define R12_CONN_WDT_IRQ_B (1U << 7)
#define R12_CCIF0_EVENT_B (1U << 8)
#define R12_LOWBATTERY_IRQ_B (1U << 9)
#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
#define R12_SCP2SPM_WAKEUP_B (1U << 11)
#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
#define R12_PCM_WDT_WAKEUP_B (1U << 13)
#define R12_USBX_CDSC_B (1U << 14)
#define R12_USBX_POWERDWN_B (1U << 15)
#define R12_SYS_TIMER_EVENT_B (1U << 16)
#define R12_EINT_EVENT_SECURE_B (1U << 17)
#define R12_CCIF1_EVENT_B (1U << 18)
#define R12_UART0_IRQ_B (1U << 19)
#define R12_AFE_IRQ_MCU_B (1U << 20)
#define R12_THERM_CTRL_EVENT_B (1U << 21)
#define R12_SYS_CIRQ_IRQ_B (1U << 22)
#define R12_MD2AP_PEER_EVENT_B (1U << 23)
#define R12_CSYSPWREQ_B (1U << 24)
#define R12_MD1_WDT_B (1U << 25)
#define R12_CLDMA_EVENT_B (1U << 26)
#define R12_SEJ_EVENT_B (1U << 27)
#define R12_REG_CPU_WAKEUP (1U << 28)
#define R12_APUSYS_WAKE_HOST_B (1U << 29)
#define R12_NOT_USED1 (1U << 30)
#define R12_NOT_USED2 (1U << 31)
/* --- R12ext Define --- */
#define R12EXT_26M_WAKE (1U << 0)
#define R12EXT_26M_SLEEP (1U << 1)
#define R12EXT_INFRA_WAKE (1U << 2)
#define R12EXT_INFRA_SLEEP (1U << 3)
#define R12EXT_APSRC_WAKE (1U << 4)
#define R12EXT_APSRC_SLEEP (1U << 5)
#define R12EXT_VRF18_WAKE (1U << 6)
#define R12EXT_VRF18_SLEEP (1U << 7)
#define R12EXT_DVFS_WAKE (1U << 8)
#define R12EXT_DDREN_WAKE (1U << 9)
#define R12EXT_DDREN_SLEEP (1U << 10)
#define R12EXT_MCU_PM_WFI (1U << 11)
#define R12EXT_SSPM_IDLE (1U << 12)
#define R12EXT_CONN_SRCCLKENB (1U << 13)
#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
#define R12EXT_VS1_TRIGGER (1U << 21)
#define R12EXT_VS2_TRIGGER (1U << 22)
#define R12EXT_COROSS_REQ_APU (1U << 23)
#define R12EXT_CROSS_REQ_L3 (1U << 24)
#define R12EXT_DDR_PST_ACK (1U << 25)
#define R12EXT_BIT26 (1U << 26)
#define R12EXT_BIT27 (1U << 27)
#define R12EXT_BIT28 (1U << 28)
#define R12EXT_BIT29 (1U << 29)
#define R12EXT_BIT30 (1U << 30)
#define R12EXT_BIT31 (1U << 31)
/* --- R13 Define --- */
#define R13_SRCCLKENI0 (1U << 0)
#define R13_SRCCLKENI1 (1U << 1)
#define R13_MD_SRCCLKENA_0 (1U << 2)
#define R13_MD_APSRC_REQ_0 (1U << 3)
#define R13_CONN_DDR_EN (1U << 4)
#define R13_MD_SRCCLKENA_1 (1U << 5)
#define R13_SSPM_SRCCLKENA (1U << 6)
#define R13_SSPM_APSRC_REQ (1U << 7)
#define R13_MD1_STATE (1U << 8)
#define R13_BIT9 (1U << 9)
#define R13_MM_STATE (1U << 10)
#define R13_SSPM_STATE (1U << 11)
#define R13_MD_DDR_EN_0 (1U << 12)
#define R13_CONN_STATE (1U << 13)
#define R13_CONN_SRCCLKENA (1U << 14)
#define R13_CONN_APSRC_REQ (1U << 15)
#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
#define R13_SCP_STATE (1U << 18)
#define R13_CSYSPWRUPREQ (1U << 19)
#define R13_PWRAP_SLEEP_ACK (1U << 20)
#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
#define R13_AUDIO_DSP_STATE (1U << 22)
#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
#define R13_CONN_SRCCLKENB (1U << 24)
#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
#define R13_DVFS_STATE (1U << 27)
#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
#define R13_MD_VRF18_REQ_0 (1U << 30)
#define R13_DDR_EN_STATE (1U << 31)
#endif /* PCM_DEF_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spm/sleep_def.h
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/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SLEEP_DEF_H
#define SLEEP_DEF_H
/*
* Auto generated by DE, please DO NOT modify this file directly.
*/
/* --- SPM Flag Define --- */
#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
#define SPM_FLAG_RESERVED_BIT11 (1U << 11)
#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD (1U << 19)
#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP (1U << 23)
#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
#define SPM_FLAG_VTCXO_STATE (1U << 27)
#define SPM_FLAG_INFRA_STATE (1U << 28)
#define SPM_FLAG_APSRC_STATE (1U << 29)
#define SPM_FLAG_VRF18_STATE (1U << 30)
#define SPM_FLAG_DDREN_STATE (1U << 31)
/* --- SPM Flag1 Define --- */
#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
#define SPM_FLAG1_RESERVED_BIT7 (1U << 7)
#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
#define SPM_FLAG1_RESERVED_BIT31 (1U << 31)
/* --- SPM DEBUG Define --- */
#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
/* --- SPM DEBUG1 Define --- */
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
#define SPM_DBG1_RESERVED_BIT31 (1U << 31)
/* Macro and Inline */
#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
#endif /* SLEEP_DEF_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
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/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <mcucfg.h>
#include <mtspmc.h>
#include <mtspmc_private.h>
void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu)
{
mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
}
void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu)
{
mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
}
void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr)
{
assert(cluster == 0U);
mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
}
uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu)
{
assert(cluster == 0U);
return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
}
void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64)
{
uint32_t reg;
assert(cluster == 0U);
reg = per_cluster(cluster, MCUCFG_INITARCH);
if (arm64) {
mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
} else {
mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
}
}
/**
* Return subsystem's power state.
*
* @mask: mask to MCUCFG_CPC_SPMC_PWR_STATUS to query the power state
* of one subsystem.
* RETURNS:
* 0 (the subsys was powered off)
* 1 (the subsys was powered on)
*/
bool spm_get_powerstate(uint32_t mask)
{
return (mmio_read_32(MCUCFG_CPC_SPMC_PWR_STATUS) & mask) != 0U;
}
bool spm_get_cluster_powerstate(unsigned int cluster)
{
assert(cluster == 0U);
return spm_get_powerstate(BIT(14));
}
bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu)
{
uint32_t mask = BIT(cpu);
assert(cluster == 0U);
return spm_get_powerstate(mask);
}
int spmc_init(void)
{
INFO("SPM: enable CPC mode\n");
mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN);
return 0;
}
/**
* Power on a core with specified cluster and core index
*
* @cluster: the cluster ID of the CPU which to be powered on
* @cpu: the CPU ID of the CPU which to be powered on
*/
void spm_poweron_cpu(unsigned int cluster, unsigned int cpu)
{
uintptr_t cpu_pwr_con = per_cpu(cluster, cpu, SPM_CPU_PWR);
/* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
if (cpu >= 4U) {
mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
}
mmio_setbits_32(cpu_pwr_con, PWR_ON);
while (!spm_get_cpu_powerstate(cluster, cpu)) {
mmio_clrbits_32(cpu_pwr_con, PWR_ON);
mmio_setbits_32(cpu_pwr_con, PWR_ON);
}
}
/**
* Power off a core with specified cluster and core index
*
* @cluster: the cluster ID of the CPU which to be powered off
* @cpu: the CPU ID of the CPU which to be powered off
*/
void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu)
{
/* Set mp0_spmc_pwr_on_cpuX = 0 */
mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
}
/**
* Power off a cluster with specified index
*
* @cluster: the cluster index which to be powered off
*/
void spm_poweroff_cluster(unsigned int cluster)
{
/* No need to power on/off cluster on single cluster platform */
assert(false);
}
/**
* Power on a cluster with specified index
*
* @cluster: the cluster index which to be powered on
*/
void spm_poweron_cluster(unsigned int cluster)
{
/* No need to power on/off cluster on single cluster platform */
assert(false);
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
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/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTSPMC_H
#define MTSPMC_H
#include <stdint.h>
int spmc_init(void);
void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
void spm_poweroff_cluster(unsigned int cluster);
void spm_poweron_cluster(unsigned int cluster);
bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
bool spm_get_cluster_powerstate(unsigned int cluster);
bool spm_get_powerstate(uint32_t mask);
void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
#endif /* MTSPMC_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
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/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTSPMC_PRIVATE_H
#define MTSPMC_PRIVATE_H
#include <lib/utils_def.h>
#include <platform_def.h>
unsigned long read_cpuectlr(void);
void write_cpuectlr(unsigned long cpuectlr);
unsigned long read_cpupwrctlr_el1(void);
void write_cpupwrctlr_el1(unsigned long cpuectlr);
/*
* per_cpu/cluster helper
*/
struct per_cpu_reg {
unsigned int cluster_addr;
unsigned int cpu_stride;
};
#define per_cpu(cluster, cpu, reg) \
(reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
/* === SPMC related registers */
#define SPM_POWERON_CONFIG_EN SPM_REG(0x000)
/* bit-fields of SPM_POWERON_CONFIG_EN */
#define PROJECT_CODE (U(0xb16) << 16)
#define BCLK_CG_EN BIT(0)
#define SPM_PWR_STATUS SPM_REG(0x16c)
#define SPM_PWR_STATUS_2ND SPM_REG(0x170)
#define SPM_CPU_PWR_STATUS SPM_REG(0x174)
/* bit-fields of SPM_PWR_STATUS */
#define MD BIT(0)
#define CONN BIT(1)
#define DDRPHY BIT(2)
#define DISP BIT(3)
#define MFG BIT(4)
#define ISP BIT(5)
#define INFRA BIT(6)
#define VDEC BIT(7)
#define MP0_CPUTOP BIT(8)
#define MP0_CPU0 BIT(9)
#define MP0_CPU1 BIT(10)
#define MP0_CPU2 BIT(11)
#define MP0_CPU3 BIT(12)
#define MCUSYS BIT(14)
#define MP0_CPU4 BIT(15)
#define MP0_CPU5 BIT(16)
#define MP0_CPU6 BIT(17)
#define MP0_CPU7 BIT(18)
#define VEN BIT(21)
/* === SPMC related registers */
#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
/* bit fields of SPM_*_PWR_CON */
#define PWR_ON_ACK BIT(31)
#define VPROC_EXT_OFF BIT(7)
#define DORMANT_EN BIT(6)
#define RESETPWRON_CONFIG BIT(5)
#define PWR_CLK_DIS BIT(4)
#define PWR_ON BIT(2)
#define PWR_RST_B BIT(0)
/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
static const struct per_cpu_reg SPM_CPU_PWR[] = {
{ .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
};
/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
{ .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
};
/* === MCUCFG related registers */
/* aa64naa32 */
#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
/* reset vectors */
#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
/* MCUSYS DREQ BIG VPROC ISO control */
#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
};
/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
static const struct per_cpu_reg MCUCFG_INITARCH[] = {
{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
};
#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu)
/* === CPC control */
#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
/* bit fields of CPC_FLOW_CTRL_CFG */
#define CPC_CTRL_ENABLE BIT(16)
#define SSPM_CORE_PWR_ON_EN BIT(7) /* for cpu-hotplug */
#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu)
/* bit fields of CPC_SPMC_PWR_STATUS */
#define CORE_SPMC_PWR_ON_ACK GENMASK(11, 0)
/* === APB Module infracfg_ao */
#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220)
#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224)
#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228)
#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0)
#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4)
#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250)
#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254)
#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258)
#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8)
#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac)
/* bit fields of INFRA_TOPAXI_PROTECTEN */
#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12)
#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12))
/* === SPARK */
#define VOLTAGE_04 U(0x40)
#define VOLTAGE_05 U(0x60)
#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)
/* bit fields of CPU0_ILDO_CONTROL5 */
#define ILDO_RET_VOSEL GENMASK(7, 0)
/* bit fields of PTP3_CPU_SPMC_SW_CFG */
#define SW_SPARK_EN BIT(0)
/* bit fields of CPU0_ILDO_CONTROL8 */
#define ILDO_BYPASS_B BIT(0)
static const struct per_cpu_reg MCUCFG_SPARK[] = {
{ .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
};
static const struct per_cpu_reg ILDO_CONTROL5[] = {
{ .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
};
static const struct per_cpu_reg ILDO_CONTROL8[] = {
{ .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
};
#endif /* MTSPMC_PRIVATE_H */