GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <emi_mpu.h>
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#if ENABLE_EMI_MPU_SW_LOCK
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static unsigned char region_lock_state[EMI_MPU_REGION_NUM];
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#endif
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#define EMI_MPU_START_MASK (0x00FFFFFF)
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#define EMI_MPU_END_MASK (0x00FFFFFF)
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#define EMI_MPU_APC_SW_LOCK_MASK (0x00FFFFFF)
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#define EMI_MPU_APC_HW_LOCK_MASK (0x80FFFFFF)
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static int _emi_mpu_set_protection(unsigned int start, unsigned int end,
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unsigned int apc)
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{
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unsigned int dgroup;
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unsigned int region;
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region = (start >> 24) & 0xFF;
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start &= EMI_MPU_START_MASK;
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dgroup = (end >> 24) & 0xFF;
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end &= EMI_MPU_END_MASK;
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if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) {
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WARN("invalid region, domain\n");
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return -1;
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}
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#if ENABLE_EMI_MPU_SW_LOCK
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if (region_lock_state[region] == 1) {
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WARN("invalid region\n");
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return -1;
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}
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if ((dgroup == 0) && ((apc >> 31) & 0x1)) {
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region_lock_state[region] = 1;
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}
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apc &= EMI_MPU_APC_SW_LOCK_MASK;
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#else
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apc &= EMI_MPU_APC_HW_LOCK_MASK;
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#endif
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if ((start >= DRAM_OFFSET) && (end >= start)) {
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start -= DRAM_OFFSET;
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end -= DRAM_OFFSET;
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} else {
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WARN("invalid range\n");
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return -1;
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}
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mmio_write_32(EMI_MPU_SA(region), start);
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mmio_write_32(EMI_MPU_EA(region), end);
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mmio_write_32(EMI_MPU_APC(region, dgroup), apc);
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#if defined(SUB_EMI_MPU_BASE)
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mmio_write_32(SUB_EMI_MPU_SA(region), start);
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mmio_write_32(SUB_EMI_MPU_EA(region), end);
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mmio_write_32(SUB_EMI_MPU_APC(region, dgroup), apc);
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#endif
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return 1;
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}
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int emi_mpu_set_protection(struct emi_region_info_t *region_info)
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{
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unsigned int start, end;
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int i;
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if (region_info->region >= EMI_MPU_REGION_NUM) {
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WARN("invalid region\n");
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return -1;
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}
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start = (unsigned int)(region_info->start >> EMI_MPU_ALIGN_BITS) |
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(region_info->region << 24);
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for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) {
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end = (unsigned int)(region_info->end >> EMI_MPU_ALIGN_BITS) |
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(i << 24);
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_emi_mpu_set_protection(start, end, region_info->apc[i]);
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}
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return 0;
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}
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void dump_emi_mpu_regions(void)
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{
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unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea;
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int region, i;
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/* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */
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for (region = 0; region < 8; ++region) {
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for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i)
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apc[i] = mmio_read_32(EMI_MPU_APC(region, i));
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sa = mmio_read_32(EMI_MPU_SA(region));
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ea = mmio_read_32(EMI_MPU_EA(region));
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INFO("region %d:\n", region);
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INFO("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n",
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sa, ea, apc[0], apc[1]);
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}
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}
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void emi_mpu_init(void)
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{
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struct emi_region_info_t region_info;
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/* SCP DRAM */
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region_info.start = 0x50000000ULL;
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region_info.end = 0x51400000ULL;
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region_info.region = 2;
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SET_ACCESS_PERMISSION(region_info.apc, 1,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
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emi_mpu_set_protection(®ion_info);
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/* DSP protect address */
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region_info.start = 0x60000000ULL; /* dram base addr */
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region_info.end = 0x610FFFFFULL;
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region_info.region = 3;
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SET_ACCESS_PERMISSION(region_info.apc, 1,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
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emi_mpu_set_protection(®ion_info);
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/* Forbidden All */
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region_info.start = 0x40000000ULL; /* dram base addr */
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region_info.end = 0x1FFFF0000ULL;
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region_info.region = 4;
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SET_ACCESS_PERMISSION(region_info.apc, 1,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
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emi_mpu_set_protection(®ion_info);
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dump_emi_mpu_regions();
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}
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+98
@@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EMI_MPU_H
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#define EMI_MPU_H
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#include <platform_def.h>
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#define ENABLE_EMI_MPU_SW_LOCK 1
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#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
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#define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
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#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
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#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
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#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4))
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#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4))
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#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
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#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100))
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#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
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#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4))
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#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
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#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4))
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#define EMI_MPU_START (0x000)
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#define EMI_MPU_END (0x93C)
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#define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000)
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#define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004)
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#define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100)
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#define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200)
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#define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4))
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#define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4))
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#define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300)
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#define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100))
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#define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800)
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#define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4))
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#define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900)
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#define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4))
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#define EMI_MPU_DOMAIN_NUM (16)
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#define EMI_MPU_REGION_NUM (32)
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#define EMI_MPU_ALIGN_BITS (16)
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#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
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#define NO_PROTECTION 0
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#define SEC_RW 1
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#define SEC_RW_NSEC_R 2
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#define SEC_RW_NSEC_W 3
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#define SEC_R_NSEC_R 4
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#define FORBIDDEN 5
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#define SEC_R_NSEC_RW 6
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#define LOCK 1
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#define UNLOCK 0
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#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
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#if (EMI_MPU_DGROUP_NUM == 1)
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#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
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do { \
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apc_ary[1] = 0; \
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apc_ary[0] = \
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(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \
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(((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \
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(((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
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(((unsigned int) d1) << 3) | ((unsigned int) d0) | \
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((unsigned int) lock << 31); \
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} while (0)
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#elif (EMI_MPU_DGROUP_NUM == 2)
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#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \
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d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
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do { \
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apc_ary[1] = \
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(((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | \
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(((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) | \
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(((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \
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(((unsigned int) d9) << 3) | ((unsigned int) d8); \
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apc_ary[0] = \
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(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \
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(((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \
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(((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
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(((unsigned int) d1) << 3) | ((unsigned int) d0) | \
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((unsigned int) lock << 31); \
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} while (0)
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#endif
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struct emi_region_info_t {
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unsigned long long start;
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unsigned long long end;
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unsigned int region;
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unsigned int apc[EMI_MPU_DGROUP_NUM];
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};
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void emi_mpu_init(void);
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#endif
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