GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <memctrl.h>
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#include <memctrl_v1.h>
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#include <tegra_def.h>
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/* Video Memory base and size (live values) */
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static uint64_t video_mem_base;
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static uint64_t video_mem_size;
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/*
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* Init SMMU.
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*/
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void tegra_memctrl_setup(void)
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{
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Tegra Memory Controller (v1)\n");
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/* allow translations for all MC engines */
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY);
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tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL);
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tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL);
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/* flush PTC and TLB */
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tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL);
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL);
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/* enable SMMU */
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tegra_mc_write_32(MC_SMMU_CONFIG_0,
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MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE);
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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/* video memory carveout */
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(video_mem_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
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}
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/*
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* Restore Memory Controller settings after "System Suspend"
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*/
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void tegra_memctrl_restore_settings(void)
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{
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tegra_memctrl_setup();
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}
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/*
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* Secure the BL31 DRAM aperture.
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*
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* phys_base = physical base of TZDRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Configuring TrustZone DRAM Memory Carveout\n");
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tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base);
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tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
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}
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static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
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unsigned long long non_overlap_area_size)
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{
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int ret;
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/*
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* Map the NS memory first, clean it and then unmap it.
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*/
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ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
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non_overlap_area_start, /* VA */
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non_overlap_area_size, /* size */
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MT_NS | MT_RW | MT_EXECUTE_NEVER |
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MT_NON_CACHEABLE); /* attrs */
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assert(ret == 0);
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zeromem((void *)non_overlap_area_start, non_overlap_area_size);
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flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
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mmap_remove_dynamic_region(non_overlap_area_start,
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non_overlap_area_size);
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}
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/*
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* Program the Video Memory carveout region
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*
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* phys_base = physical base of aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20);
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uintptr_t vmem_end_new = phys_base + size_in_bytes;
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unsigned long long non_overlap_area_size;
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/*
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* Setup the Memory controller to restrict CPU accesses to the Video
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* Memory region
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*/
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INFO("Configuring Video Memory Carveout\n");
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/*
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* Configure Memory Controller directly for the first time.
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*/
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if (video_mem_base == 0)
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goto done;
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/*
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* Clear the old regions now being exposed. The following cases
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* can occur -
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*
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* 1. clear whole old region (no overlap with new region)
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* 2. clear old sub-region below new base
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* 3. clear old sub-region above new end
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*/
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INFO("Cleaning previous Video Memory Carveout\n");
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if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
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tegra_clear_videomem(video_mem_base, video_mem_size << 20);
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} else {
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if (video_mem_base < phys_base) {
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non_overlap_area_size = phys_base - video_mem_base;
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tegra_clear_videomem(video_mem_base, non_overlap_area_size);
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}
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if (vmem_end_old > vmem_end_new) {
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non_overlap_area_size = vmem_end_old - vmem_end_new;
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tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
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}
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}
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done:
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
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/* store new values */
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video_mem_base = phys_base;
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video_mem_size = size_in_bytes >> 20;
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}
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/*
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* During boot, USB3 and flash media (SDMMC/SATA) devices need access to
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* IRAM. Because these clients connect to the MC and do not have a direct
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* path to the IRAM, the MC implements AHB redirection during boot to allow
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* path to IRAM. In this mode, accesses to a programmed memory address aperture
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* are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
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* is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
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* initialized to disable this aperture.
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*
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* Once bootup is complete, we must program IRAM base to 0xffffffff and
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* IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
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* potentially accessible in this address range. These aperture registers
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* also have an access_control/lock bit. After disabling the aperture, the
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* access_control register should be programmed to lock the registers.
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*/
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void tegra_memctrl_disable_ahb_redirection(void)
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{
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/* program the aperture registers */
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tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
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tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
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tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
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/* lock the aperture registers */
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tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
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}
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void tegra_memctrl_clear_pending_interrupts(void)
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{
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uint32_t mcerr;
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/* check if there are any pending interrupts */
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mcerr = mmio_read_32(TEGRA_MC_BASE + MC_INTSTATUS);
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if (mcerr != (uint32_t)0U) { /* should not see error here */
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WARN("MC_INTSTATUS = 0x%x (should be zero)\n", mcerr);
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mmio_write_32((TEGRA_MC_BASE + MC_INTSTATUS), mcerr);
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}
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}
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+354
@@ -0,0 +1,354 @@
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <mce.h>
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#include <memctrl.h>
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#include <memctrl_v2.h>
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#include <smmu.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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/* Video Memory base and size (live values) */
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static uint64_t video_mem_base;
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static uint64_t video_mem_size_mb;
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/*
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* Init Memory controller during boot.
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*/
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void tegra_memctrl_setup(void)
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{
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INFO("Tegra Memory Controller (v2)\n");
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/* Initialize the System memory management unit */
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tegra_smmu_init();
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/* allow platforms to program custom memory controller settings */
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plat_memctrl_setup();
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/*
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* All requests at boot time, and certain requests during
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* normal run time, are physically addressed and must bypass
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* the SMMU. The client hub logic implements a hardware bypass
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* path around the Translation Buffer Units (TBU). During
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* boot-time, the SMMU_BYPASS_CTRL register (which defaults to
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* TBU_BYPASS mode) will be used to steer all requests around
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* the uninitialized TBUs. During normal operation, this register
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* is locked into TBU_BYPASS_SID config, which routes requests
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* with special StreamID 0x7f on the bypass path and all others
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* through the selected TBU. This is done to disable SMMU Bypass
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* mode, as it could be used to circumvent SMMU security checks.
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*/
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tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
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MC_SMMU_BYPASS_CONFIG_SETTINGS);
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}
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/*
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* Restore Memory Controller settings after "System Suspend"
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*/
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void tegra_memctrl_restore_settings(void)
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{
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/* restore platform's memory controller settings */
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plat_memctrl_restore();
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/* video memory carveout region */
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if (video_mem_base != 0ULL) {
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
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(uint32_t)video_mem_base);
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assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
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== (uint32_t)video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(video_mem_base >> 32));
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assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
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== (uint32_t)(video_mem_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB,
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(uint32_t)video_mem_size_mb);
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assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
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== (uint32_t)video_mem_size_mb);
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/*
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* MCE propagates the VideoMem configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_videomem();
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}
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}
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/*
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* Secure the BL31 DRAM aperture.
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*
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* phys_base = physical base of TZDRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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/*
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* Perform platform specific steps.
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*/
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plat_memctrl_tzdram_setup(phys_base, size_in_bytes);
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}
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/*
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* Secure the BL31 TZRAM aperture.
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*
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* phys_base = physical base of TZRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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; /* do nothing */
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}
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/*
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* Save MC settings before "System Suspend" to TZDRAM
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*/
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void tegra_mc_save_context(uint64_t mc_ctx_addr)
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{
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uint32_t i, num_entries = 0;
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mc_regs_t *mc_ctx_regs;
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const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint64_t tzdram_base = params_from_bl2->tzdram_base;
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uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
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assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end));
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/* get MC context table */
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mc_ctx_regs = plat_memctrl_get_sys_suspend_ctx();
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assert(mc_ctx_regs != NULL);
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/*
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* mc_ctx_regs[0].val contains the size of the context table minus
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* the last entry. Sanity check the table size before we start with
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* the context save operation.
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*/
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while (mc_ctx_regs[num_entries].reg != 0xFFFFFFFFU) {
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num_entries++;
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}
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/* panic if the sizes do not match */
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if (num_entries != mc_ctx_regs[0].val) {
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ERROR("MC context size mismatch!");
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panic();
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}
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/* save MC register values */
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for (i = 1U; i < num_entries; i++) {
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mc_ctx_regs[i].val = mmio_read_32(mc_ctx_regs[i].reg);
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}
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/* increment by 1 to take care of the last entry */
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num_entries++;
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/* Save MC config settings */
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(void)memcpy((void *)mc_ctx_addr, mc_ctx_regs,
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sizeof(mc_regs_t) * num_entries);
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/* save the MC table address */
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO,
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(uint32_t)mc_ctx_addr);
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assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO)
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== (uint32_t)mc_ctx_addr);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI,
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(uint32_t)(mc_ctx_addr >> 32));
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assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI)
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== (uint32_t)(mc_ctx_addr >> 32));
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}
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static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
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uint64_t size_in_bytes)
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{
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uint32_t index;
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uint64_t total_128kb_blocks = size_in_bytes >> 17;
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uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
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uint64_t val;
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/*
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* Reset the access configuration registers to restrict access to
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* old Videomem aperture
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*/
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for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0;
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index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
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index += 4U) {
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tegra_mc_write_32(index, 0);
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}
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/*
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* Set the base. It must be 4k aligned, at least.
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*/
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assert((phys_base & (uint64_t)0xFFF) == 0U);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI,
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(uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK);
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/*
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* Set the aperture size
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*
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* total size = (number of 128KB blocks) + (number of remaining 4KB
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* blocks)
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||||
*
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*/
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val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
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total_128kb_blocks);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val);
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/*
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* Lock the configuration settings by enabling TZ-only lock and
|
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* locking the configuration against any future changes from NS
|
||||
* world.
|
||||
*/
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG,
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(uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT);
|
||||
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/*
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* MCE propagates the GSC configuration values across the
|
||||
* CCPLEX.
|
||||
*/
|
||||
}
|
||||
|
||||
static void tegra_unlock_videomem_nonoverlap(void)
|
||||
{
|
||||
/* Clear the base */
|
||||
tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0);
|
||||
tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0);
|
||||
|
||||
/* Clear the size */
|
||||
tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0);
|
||||
}
|
||||
|
||||
static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
|
||||
unsigned long long non_overlap_area_size)
|
||||
{
|
||||
int ret;
|
||||
|
||||
INFO("Cleaning previous Video Memory Carveout\n");
|
||||
|
||||
/*
|
||||
* Map the NS memory first, clean it and then unmap it.
|
||||
*/
|
||||
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
|
||||
non_overlap_area_start, /* VA */
|
||||
non_overlap_area_size, /* size */
|
||||
MT_DEVICE | MT_RW | MT_NS); /* attrs */
|
||||
assert(ret == 0);
|
||||
|
||||
zeromem((void *)non_overlap_area_start, non_overlap_area_size);
|
||||
flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
|
||||
|
||||
ret = mmap_remove_dynamic_region(non_overlap_area_start,
|
||||
non_overlap_area_size);
|
||||
assert(ret == 0);
|
||||
}
|
||||
|
||||
static void tegra_clear_videomem_nonoverlap(uintptr_t phys_base,
|
||||
unsigned long size_in_bytes)
|
||||
{
|
||||
uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20);
|
||||
uintptr_t vmem_end_new = phys_base + size_in_bytes;
|
||||
unsigned long long non_overlap_area_size;
|
||||
|
||||
/*
|
||||
* Clear the old regions now being exposed. The following cases
|
||||
* can occur -
|
||||
*
|
||||
* 1. clear whole old region (no overlap with new region)
|
||||
* 2. clear old sub-region below new base
|
||||
* 3. clear old sub-region above new end
|
||||
*/
|
||||
if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
|
||||
tegra_clear_videomem(video_mem_base,
|
||||
video_mem_size_mb << 20U);
|
||||
} else {
|
||||
if (video_mem_base < phys_base) {
|
||||
non_overlap_area_size = phys_base - video_mem_base;
|
||||
tegra_clear_videomem(video_mem_base, non_overlap_area_size);
|
||||
}
|
||||
if (vmem_end_old > vmem_end_new) {
|
||||
non_overlap_area_size = vmem_end_old - vmem_end_new;
|
||||
tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Program the Video Memory carveout region
|
||||
*
|
||||
* phys_base = physical base of aperture
|
||||
* size_in_bytes = size of aperture in bytes
|
||||
*/
|
||||
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
|
||||
{
|
||||
/*
|
||||
* Setup the Memory controller to restrict CPU accesses to the Video
|
||||
* Memory region
|
||||
*/
|
||||
|
||||
INFO("Configuring Video Memory Carveout\n");
|
||||
|
||||
if (video_mem_base != 0U) {
|
||||
/*
|
||||
* Lock the non overlapping memory being cleared so that
|
||||
* other masters do not accidently write to it. The memory
|
||||
* would be unlocked once the non overlapping region is
|
||||
* cleared and the new memory settings take effect.
|
||||
*/
|
||||
tegra_lock_videomem_nonoverlap(video_mem_base,
|
||||
video_mem_size_mb << 20);
|
||||
}
|
||||
|
||||
/* program the Videomem aperture */
|
||||
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
|
||||
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
|
||||
(uint32_t)(phys_base >> 32));
|
||||
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
|
||||
|
||||
/* Redundancy check for Video Protect setting */
|
||||
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
|
||||
== (uint32_t)phys_base);
|
||||
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
|
||||
== (uint32_t)(phys_base >> 32));
|
||||
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
|
||||
== (size_in_bytes >> 20));
|
||||
|
||||
/*
|
||||
* MCE propagates the VideoMem configuration values across the
|
||||
* CCPLEX.
|
||||
*/
|
||||
(void)mce_update_gsc_videomem();
|
||||
|
||||
/* Clear the non-overlapping memory */
|
||||
if (video_mem_base != 0U) {
|
||||
tegra_clear_videomem_nonoverlap(phys_base, size_in_bytes);
|
||||
tegra_unlock_videomem_nonoverlap();
|
||||
}
|
||||
|
||||
/* store new values */
|
||||
video_mem_base = phys_base;
|
||||
video_mem_size_mb = (uint64_t)size_in_bytes >> 20;
|
||||
}
|
||||
|
||||
/*
|
||||
* This feature exists only for v1 of the Tegra Memory Controller.
|
||||
*/
|
||||
void tegra_memctrl_disable_ahb_redirection(void)
|
||||
{
|
||||
; /* do nothing */
|
||||
}
|
||||
|
||||
void tegra_memctrl_clear_pending_interrupts(void)
|
||||
{
|
||||
; /* do nothing */
|
||||
}
|
||||
Reference in New Issue
Block a user