GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA186_PRIVATE_H
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#define TEGRA186_PRIVATE_H
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uint64_t tegra186_get_mc_ctx_size(void);
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#endif /* TEGRA186_PRIVATE_H */
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA_DEF_H
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#define TEGRA_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Platform BL31 specific defines.
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******************************************************************************/
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#define BL31_SIZE U(0x40000)
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/*******************************************************************************
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* MCE apertures used by the ARI interface
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*
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* Aperture 0 - Cpu0 (ARM Cortex A-57)
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* Aperture 1 - Cpu1 (ARM Cortex A-57)
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* Aperture 2 - Cpu2 (ARM Cortex A-57)
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* Aperture 3 - Cpu3 (ARM Cortex A-57)
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* Aperture 4 - Cpu4 (Denver15)
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* Aperture 5 - Cpu5 (Denver15)
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******************************************************************************/
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#define MCE_ARI_APERTURE_0_OFFSET U(0x0)
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#define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
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#define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
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#define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
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#define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
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#define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
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#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
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/* number of apertures */
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#define MCE_ARI_APERTURES_MAX U(6)
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/* each ARI aperture is 64KB */
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#define MCE_ARI_APERTURE_SIZE U(0x10000)
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/*******************************************************************************
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* CPU core id macros for the MCE_ONLINE_CORE ARI
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******************************************************************************/
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#define MCE_CORE_ID_MAX U(8)
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#define MCE_CORE_ID_MASK U(0x7)
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/*******************************************************************************
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* These values are used by the PSCI implementation during the `CPU_SUSPEND`
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* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
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* parameter.
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******************************************************************************/
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#define PSTATE_ID_CORE_IDLE U(6)
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#define PSTATE_ID_CORE_POWERDN U(7)
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#define PSTATE_ID_SOC_POWERDN U(2)
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(8)
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/*******************************************************************************
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* Chip specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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#define TEGRA186_TOP_WDT_IRQ U(49)
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#define TEGRA186_AON_WDT_IRQ U(50)
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#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */
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/*******************************************************************************
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* Clock identifier for the SE device
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******************************************************************************/
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#define TEGRA186_CLK_SE U(103)
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#define TEGRA_CLK_SE TEGRA186_CLK_SE
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/*******************************************************************************
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* Tegra Miscellanous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE U(0x00100000)
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#define HARDWARE_REVISION_OFFSET U(0x4)
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#define MISCREG_PFCFG U(0x200C)
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/*******************************************************************************
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* Tegra TSA Controller constants
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******************************************************************************/
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#define TEGRA_TSA_BASE U(0x02400000)
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/*******************************************************************************
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* TSA configuration registers
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******************************************************************************/
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#define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010)
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#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038)
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#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010)
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#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008)
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#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008)
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#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100)
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#define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018)
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#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018)
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#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028)
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#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018)
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#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008)
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#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018)
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#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028)
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#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038)
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#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008)
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#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100)
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#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018)
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#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100)
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
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/*******************************************************************************
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* Tegra General Purpose Centralised DMA constants
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******************************************************************************/
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#define TEGRA_GPCDMA_BASE ULL(0x2610000)
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
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#define TEGRA_MC_BASE U(0x02C10000)
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/* General Security Carveout register macros */
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#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
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#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
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#define MC_GSC_ENABLE_TZ_LOCK_BIT (ULL(1) << 0)
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#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
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#define MC_GSC_BASE_LO_SHIFT U(12)
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#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
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#define MC_GSC_BASE_HI_SHIFT U(0)
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#define MC_GSC_BASE_HI_MASK U(3)
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#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 U(0x70)
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#define MC_SECURITY_CFG1_0 U(0x74)
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#define MC_SECURITY_CFG3_0 U(0x9BC)
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#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
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#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
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#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
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#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
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#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
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#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
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#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
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/*
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* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
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* non-overlapping Video memory region
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*/
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#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
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#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
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#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
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#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
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#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
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/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
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#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
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#define MC_TZRAM_BASE_LO U(0x2194)
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#define MC_TZRAM_BASE_HI U(0x2198)
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#define MC_TZRAM_SIZE U(0x219C)
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#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
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#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
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#define TZRAM_ALLOW_MPCORER (U(1) << 7)
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#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
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/*******************************************************************************
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* Tegra UART Controller constants
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******************************************************************************/
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#define TEGRA_UARTA_BASE U(0x03100000)
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#define TEGRA_UARTB_BASE U(0x03110000)
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#define TEGRA_UARTC_BASE U(0x0C280000)
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#define TEGRA_UARTD_BASE U(0x03130000)
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#define TEGRA_UARTE_BASE U(0x03140000)
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#define TEGRA_UARTF_BASE U(0x03150000)
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#define TEGRA_UARTG_BASE U(0x0C290000)
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/*******************************************************************************
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* Tegra Fuse Controller related constants
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******************************************************************************/
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#define TEGRA_FUSE_BASE U(0x03820000)
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#define OPT_SUBREVISION U(0x248)
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#define SUBREVISION_MASK U(0xFF)
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/*******************************************************************************
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* GICv2 & interrupt handling related constants
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******************************************************************************/
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#define TEGRA_GICD_BASE U(0x03881000)
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#define TEGRA_GICC_BASE U(0x03882000)
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/*******************************************************************************
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* Security Engine related constants
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******************************************************************************/
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#define TEGRA_SE0_BASE U(0x03AC0000)
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#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
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#define TEGRA_PKA1_BASE U(0x03AD0000)
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#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144)
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#define TEGRA_RNG1_BASE U(0x03AE0000)
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#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
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/*******************************************************************************
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* Tegra HSP doorbell #0 constants
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******************************************************************************/
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#define TEGRA_HSP_DBELL_BASE U(0x03C90000)
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#define HSP_DBELL_1_ENABLE U(0x104)
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#define HSP_DBELL_3_TRIGGER U(0x300)
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#define HSP_DBELL_3_ENABLE U(0x304)
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE U(0x05000000)
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#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
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#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34)
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#define GPU_RESET_BIT (U(1) << 0)
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#define GPU_SET_BIT (U(1) << 0)
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#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
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#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE U(0x0C2E0000)
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#define TEGRA_TMRUS_SIZE U(0x1000)
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE U(0x0C360000)
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/*******************************************************************************
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* Tegra scratch registers constants
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******************************************************************************/
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#define TEGRA_SCRATCH_BASE U(0x0C390000)
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#define SECURE_SCRATCH_RSV0_HI U(0x654)
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#define SECURE_SCRATCH_RSV1_LO U(0x658)
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#define SECURE_SCRATCH_RSV1_HI U(0x65C)
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#define SECURE_SCRATCH_RSV6 U(0x680)
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#define SECURE_SCRATCH_RSV11_LO U(0x6A8)
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#define SECURE_SCRATCH_RSV11_HI U(0x6AC)
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#define SECURE_SCRATCH_RSV53_LO U(0x7F8)
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#define SECURE_SCRATCH_RSV53_HI U(0x7FC)
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#define SECURE_SCRATCH_RSV55_LO U(0x808)
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#define SECURE_SCRATCH_RSV55_HI U(0x80C)
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#define SECURE_SCRATCH_RSV63_LO U(0x848)
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#define SECURE_SCRATCH_RSV63_HI U(0x84C)
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#define SECURE_SCRATCH_RSV64_LO U(0x850)
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#define SECURE_SCRATCH_RSV64_HI U(0x854)
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#define SECURE_SCRATCH_RSV65_LO U(0x858)
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#define SECURE_SCRATCH_RSV65_HI U(0x85c)
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#define SECURE_SCRATCH_RSV66_LO U(0x860)
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#define SECURE_SCRATCH_RSV66_HI U(0x864)
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#define SECURE_SCRATCH_RSV68_LO U(0x870)
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#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO
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#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI
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#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6
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#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO
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#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI
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#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO
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#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI
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#define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO
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#define SCRATCH_TZDRAM_ADDR_HI SECURE_SCRATCH_RSV55_HI
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/*******************************************************************************
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* Tegra Memory Mapped Control Register Access constants
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******************************************************************************/
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#define TEGRA_MMCRAB_BASE U(0x0E000000)
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/*******************************************************************************
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* Tegra Memory Mapped Activity Monitor Register Access constants
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******************************************************************************/
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#define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000)
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#define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000)
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/*******************************************************************************
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* Tegra SMMU Controller constants
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******************************************************************************/
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#define TEGRA_SMMU0_BASE U(0x12000000)
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE U(0x30000000)
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#define TEGRA_TZRAM_SIZE U(0x40000)
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/*******************************************************************************
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* Tegra CCPLEX-BPMP IPC constants
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******************************************************************************/
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#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x3004C000)
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#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x3004D000)
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#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */
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/*******************************************************************************
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* Tegra DRAM memory base address
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******************************************************************************/
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#define TEGRA_DRAM_BASE ULL(0x80000000)
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#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
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#endif /* TEGRA_DEF_H */
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+398
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/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA_MC_DEF_H
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#define TEGRA_MC_DEF_H
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/*******************************************************************************
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* Memory Controller's PCFIFO client configuration registers
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******************************************************************************/
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#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U
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#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U
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#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000U
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29)
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#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29)
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#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U
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#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000U
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11)
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11)
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13)
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#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13)
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||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Stream ID Override Config registers
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro to calculate Security cfg register addr from StreamID Override register
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller transaction override config registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
|
||||
* MC_TXN_OVERRIDE_CONFIG_{module} registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller Reset Control registers
|
||||
******************************************************************************/
|
||||
#define MC_CLIENT_HOTRESET_CTRL0 0x200U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
|
||||
#define MC_CLIENT_HOTRESET_STATUS0 0x204U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1 0x970U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 21)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 23)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
|
||||
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure to hold the transaction override settings to use to override
|
||||
* client inputs
|
||||
******************************************************************************/
|
||||
typedef struct mc_txn_override_cfg {
|
||||
uint32_t offset;
|
||||
uint8_t cgid_tag;
|
||||
} mc_txn_override_cfg_t;
|
||||
|
||||
#define mc_make_txn_override_cfg(off, val) \
|
||||
{ \
|
||||
.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
|
||||
.cgid_tag = MC_TXN_OVERRIDE_ ## val \
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure to hold the Stream ID to use to override client inputs
|
||||
******************************************************************************/
|
||||
typedef struct mc_streamid_override_cfg {
|
||||
uint32_t offset;
|
||||
uint8_t stream_id;
|
||||
} mc_streamid_override_cfg_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure to hold the Stream ID Security Configuration settings
|
||||
******************************************************************************/
|
||||
typedef struct mc_streamid_security_cfg {
|
||||
char *name;
|
||||
uint32_t offset;
|
||||
uint32_t override_enable;
|
||||
uint32_t override_client_inputs;
|
||||
uint32_t override_client_ns_flag;
|
||||
} mc_streamid_security_cfg_t;
|
||||
|
||||
#define OVERRIDE_DISABLE 1U
|
||||
#define OVERRIDE_ENABLE 0U
|
||||
#define CLIENT_FLAG_SECURE 0U
|
||||
#define CLIENT_FLAG_NON_SECURE 1U
|
||||
#define CLIENT_INPUTS_OVERRIDE 1U
|
||||
#define CLIENT_INPUTS_NO_OVERRIDE 0U
|
||||
|
||||
/*******************************************************************************
|
||||
* StreamID to indicate no SMMU translations (requests to be steered on the
|
||||
* SMMU bypass path)
|
||||
******************************************************************************/
|
||||
#define MC_STREAM_ID_MAX 0x7FU
|
||||
|
||||
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
|
||||
{ \
|
||||
.name = # off, \
|
||||
.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
|
||||
MC_STREAMID_OVERRIDE_CFG_ ## off), \
|
||||
.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
|
||||
.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
|
||||
.override_enable = OVERRIDE_ ## access \
|
||||
}
|
||||
|
||||
#define mc_make_sid_override_cfg(name) \
|
||||
{ \
|
||||
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
|
||||
.val = 0x00000000U, \
|
||||
}
|
||||
|
||||
#define mc_make_sid_security_cfg(name) \
|
||||
{ \
|
||||
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
|
||||
.val = 0x00000000U, \
|
||||
}
|
||||
|
||||
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
|
||||
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
|
||||
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
|
||||
|
||||
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
|
||||
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
|
||||
|
||||
#define mc_set_tsa_passthrough(client) \
|
||||
do { \
|
||||
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
|
||||
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
|
||||
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
|
||||
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
} while (0)
|
||||
|
||||
#define mc_set_tsa_w_passthrough(client) \
|
||||
do { \
|
||||
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
|
||||
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
|
||||
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
|
||||
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
} while (0)
|
||||
|
||||
#define mc_set_tsa_r_passthrough(client) \
|
||||
{ \
|
||||
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
|
||||
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
|
||||
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
|
||||
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
} while (0)
|
||||
|
||||
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
|
||||
do { \
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
|
||||
MC_TXN_OVERRIDE_##normal_axi_id | \
|
||||
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
|
||||
MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
|
||||
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
|
||||
} while (0)
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* TEGRA_MC_DEF_H */
|
||||
Reference in New Issue
Block a user