GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <asm_macros.S>
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#include "bl31_data.h"
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#include "plat_psci.h"
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#include "platform_def.h"
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.global _getCoreData
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.global _setCoreData
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.global _getCoreState
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.global _setCoreState
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.global _init_global_data
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.global _get_global_data
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.global _set_global_data
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.global _initialize_psci
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.global _init_task_flags
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.global _set_task1_start
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.global _set_task1_done
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/* Function returns the specified data field value from the specified cpu
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* core data area
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* in: x0 = core mask lsb
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* x1 = data field name/offset
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* out: x0 = data value
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* uses x0, x1, x2, [x13, x14, x15]
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*/
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func _getCoreData
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/* generate a 0-based core number from the input mask */
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clz x2, x0
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mov x0, #63
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sub x0, x0, x2
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/* x0 = core number (0-based) */
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/* x1 = field offset */
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/* determine if this is bootcore or secondary core */
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cbnz x0, 1f
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/* get base address for bootcore data */
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ldr x2, =BC_PSCI_BASE
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add x2, x2, x1
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b 2f
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1: /* get base address for secondary core data */
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/* x0 = core number (0-based) */
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/* x1 = field offset */
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/* generate number of regions to offset */
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mov x2, #SEC_REGION_SIZE
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mul x2, x2, x0
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/* x1 = field offset */
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/* x2 = region offset */
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/* generate the total offset to data element */
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sub x1, x2, x1
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/* x1 = total offset to data element */
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/* get the base address */
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ldr x2, =SECONDARY_TOP
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/* apply offset to base addr */
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sub x2, x2, x1
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2:
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/* x2 = data element address */
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dc ivac, x2
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dsb sy
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isb
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/* read data */
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ldr x0, [x2]
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ret
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endfunc _getCoreData
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/* Function returns the SoC-specific state of the specified cpu
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* in: x0 = core mask lsb
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* out: x0 = data value
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* uses x0, x1, x2, [x13, x14, x15]
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*/
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func _getCoreState
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mov x1, #CORE_STATE_DATA
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/* generate a 0-based core number from the input mask */
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clz x2, x0
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mov x0, #63
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sub x0, x0, x2
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/* x0 = core number (0-based) */
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/* x1 = field offset */
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/* determine if this is bootcore or secondary core */
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cbnz x0, 1f
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/* get base address for bootcore data */
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ldr x2, =BC_PSCI_BASE
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add x2, x2, x1
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b 2f
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1: /* get base address for secondary core data */
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/* x0 = core number (0-based) */
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/* x1 = field offset */
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/* generate number of regions to offset */
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mov x2, #SEC_REGION_SIZE
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mul x2, x2, x0
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/* x1 = field offset */
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/* x2 = region offset */
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/* generate the total offset to data element */
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sub x1, x2, x1
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/* x1 = total offset to data element */
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/* get the base address */
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ldr x2, =SECONDARY_TOP
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/* apply offset to base addr */
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sub x2, x2, x1
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2:
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/* x2 = data element address */
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dc ivac, x2
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dsb sy
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isb
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/* read data */
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ldr x0, [x2]
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ret
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endfunc _getCoreState
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/* Function writes the specified data value into the specified cpu
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* core data area
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* in: x0 = core mask lsb
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* x1 = data field offset
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* x2 = data value to write/store
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* out: none
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* uses x0, x1, x2, x3, [x13, x14, x15]
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*/
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func _setCoreData
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/* x0 = core mask */
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/* x1 = field offset */
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/* x2 = data value */
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clz x3, x0
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mov x0, #63
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sub x0, x0, x3
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/* x0 = core number (0-based) */
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/* x1 = field offset */
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/* x2 = data value */
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/* determine if this is bootcore or secondary core */
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cbnz x0, 1f
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/* get base address for bootcore data */
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ldr x3, =BC_PSCI_BASE
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add x3, x3, x1
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b 2f
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1: /* get base address for secondary core data */
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/* x0 = core number (0-based) */
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/* x1 = field offset */
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/* x2 = data value */
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/* generate number of regions to offset */
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mov x3, #SEC_REGION_SIZE
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mul x3, x3, x0
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/* x1 = field offset */
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/* x2 = data value */
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/* x3 = region offset */
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/* generate the total offset to data element */
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sub x1, x3, x1
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/* x1 = total offset to data element */
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/* x2 = data value */
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ldr x3, =SECONDARY_TOP
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/* apply offset to base addr */
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sub x3, x3, x1
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2:
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/* x2 = data value */
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/* x3 = data element address */
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str x2, [x3]
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dc cvac, x3
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dsb sy
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isb
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ret
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endfunc _setCoreData
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/* Function stores the specified core state
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* in: x0 = core mask lsb
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* x1 = data value to write/store
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* out: none
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* uses x0, x1, x2, x3, [x13, x14, x15]
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*/
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func _setCoreState
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mov x2, #CORE_STATE_DATA
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clz x3, x0
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mov x0, #63
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sub x0, x0, x3
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/* x0 = core number (0-based) */
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/* x1 = data value */
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/* x2 = field offset */
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/* determine if this is bootcore or secondary core */
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cbnz x0, 1f
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/* get base address for bootcore data */
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ldr x3, =BC_PSCI_BASE
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add x3, x3, x2
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b 2f
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1: /* get base address for secondary core data */
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/* x0 = core number (0-based) */
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/* x1 = data value */
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/* x2 = field offset */
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/* generate number of regions to offset */
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mov x3, #SEC_REGION_SIZE
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mul x3, x3, x0
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/* x1 = data value */
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/* x2 = field offset */
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/* x3 = region offset */
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/* generate the total offset to data element */
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sub x2, x3, x2
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/* x1 = data value */
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/* x2 = total offset to data element */
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ldr x3, =SECONDARY_TOP
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/* apply offset to base addr */
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sub x3, x3, x2
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2:
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/* x1 = data value */
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/* x3 = data element address */
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str x1, [x3]
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dc civac, x3
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dsb sy
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isb
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ret
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endfunc _setCoreState
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/* Function sets the task1 start
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* in: w0 = value to set flag to
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* out: none
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* uses x0, x1
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*/
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func _set_task1_start
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ldr x1, =SMC_TASK1_BASE
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add x1, x1, #TSK_START_OFFSET
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str w0, [x1]
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dc cvac, x1
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dsb sy
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isb
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ret
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endfunc _set_task1_start
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/* Function sets the state of the task 1 done flag
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* in: w0 = value to set flag to
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* out: none
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* uses x0, x1
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*/
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func _set_task1_done
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ldr x1, =SMC_TASK1_BASE
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add x1, x1, #TSK_DONE_OFFSET
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str w0, [x1]
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dc cvac, x1
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dsb sy
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isb
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ret
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endfunc _set_task1_done
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/* Function initializes the smc global data entries
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* Note: the constant LAST_SMC_GLBL_OFFSET must reference the last entry in the
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* smc global region
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* in: none
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* out: none
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* uses x0, x1, x2
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*/
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func _init_global_data
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ldr x1, =SMC_GLBL_BASE
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/* x1 = SMC_GLBL_BASE */
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mov x2, #LAST_SMC_GLBL_OFFSET
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add x2, x2, x1
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1:
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str xzr, [x1]
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dc cvac, x1
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cmp x2, x1
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add x1, x1, #8
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b.hi 1b
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dsb sy
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isb
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ret
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endfunc _init_global_data
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/* Function gets the value of the specified global data element
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* in: x0 = offset of data element
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* out: x0 = requested data element
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* uses x0, x1
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*/
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func _get_global_data
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ldr x1, =SMC_GLBL_BASE
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add x1, x1, x0
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dc ivac, x1
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isb
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ldr x0, [x1]
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ret
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endfunc _get_global_data
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/* Function sets the value of the specified global data element
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* in: x0 = offset of data element
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* x1 = value to write
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* out: none
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* uses x0, x1, x2
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*/
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func _set_global_data
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ldr x2, =SMC_GLBL_BASE
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add x0, x0, x2
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str x1, [x0]
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dc cvac, x0
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dsb sy
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isb
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ret
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endfunc _set_global_data
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/* Function initializes the core data areas
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* only executed by the boot core
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* in: none
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* out: none
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* uses: x0, x1, x2, x3, x4, x5, x6, x7, [x13, x14, x15]
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*/
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func _initialize_psci
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mov x7, x30
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/* initialize the bootcore psci data */
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ldr x5, =BC_PSCI_BASE
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mov x6, #CORE_RELEASED
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str x6, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5], #8
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dc cvac, x5
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str xzr, [x5]
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dc cvac, x5
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dsb sy
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isb
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/* see if we have any secondary cores */
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mov x4, #PLATFORM_CORE_COUNT
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sub x4, x4, #1
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cbz x4, 3f
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/* initialize the secondary core's psci data */
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ldr x5, =SECONDARY_TOP
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/* core mask lsb for core 1 */
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mov x3, #2
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sub x5, x5, #SEC_REGION_SIZE
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/* x3 = core1 mask lsb */
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/* x4 = number of secondary cores */
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/* x5 = core1 psci data base address */
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2:
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/* set core state in x6 */
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mov x0, x3
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mov x6, #CORE_IN_RESET
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bl _soc_ck_disabled
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cbz x0, 1f
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mov x6, #CORE_DISABLED
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1:
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add x2, x5, #CORE_STATE_DATA
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str x6, [x2]
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dc cvac, x2
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add x2, x5, #SPSR_EL3_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #CNTXT_ID_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #START_ADDR_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #LINK_REG_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #GICC_CTLR_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #ABORT_FLAG_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #SCTLR_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #CPUECTLR_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #AUX_01_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #AUX_02_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #AUX_03_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #AUX_04_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #AUX_05_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #SCR_EL3_DATA
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str xzr, [x2]
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dc cvac, x2
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add x2, x5, #HCR_EL2_DATA
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str xzr, [x2]
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dc cvac, x2
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dsb sy
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isb
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sub x4, x4, #1
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cbz x4, 3f
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/* generate next core mask */
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lsl x3, x3, #1
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/* decrement base address to next data area */
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sub x5, x5, #SEC_REGION_SIZE
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b 2b
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3:
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mov x30, x7
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ret
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endfunc _initialize_psci
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/* Function initializes the soc init task flags
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* in: none
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* out: none
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* uses x0, x1, [x13, x14, x15]
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*/
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func _init_task_flags
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/* get the base address of the first task structure */
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ldr x0, =SMC_TASK1_BASE
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/* x0 = task1 base address */
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str wzr, [x0, #TSK_START_OFFSET]
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str wzr, [x0, #TSK_DONE_OFFSET]
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str wzr, [x0, #TSK_CORE_OFFSET]
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dc cvac, x0
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/* move to task2 structure */
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add x0, x0, #SMC_TASK_OFFSET
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str wzr, [x0, #TSK_START_OFFSET]
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str wzr, [x0, #TSK_DONE_OFFSET]
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str wzr, [x0, #TSK_CORE_OFFSET]
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dc cvac, x0
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/* move to task3 structure */
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add x0, x0, #SMC_TASK_OFFSET
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str wzr, [x0, #TSK_START_OFFSET]
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str wzr, [x0, #TSK_DONE_OFFSET]
|
||||
str wzr, [x0, #TSK_CORE_OFFSET]
|
||||
dc cvac, x0
|
||||
|
||||
/* move to task4 structure */
|
||||
add x0, x0, #SMC_TASK_OFFSET
|
||||
|
||||
str wzr, [x0, #TSK_START_OFFSET]
|
||||
str wzr, [x0, #TSK_DONE_OFFSET]
|
||||
str wzr, [x0, #TSK_CORE_OFFSET]
|
||||
dc cvac, x0
|
||||
|
||||
dsb sy
|
||||
isb
|
||||
ret
|
||||
endfunc _init_task_flags
|
||||
@@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm_macros.S>
|
||||
#include <cortex_a53.h>
|
||||
#include <drivers/console.h>
|
||||
#include <lib/cpus/aarch64/cortex_a72.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
|
||||
.globl plat_crash_console_init
|
||||
.globl plat_crash_console_putc
|
||||
.globl plat_crash_console_flush
|
||||
.globl plat_core_pos
|
||||
.globl plat_my_core_pos
|
||||
.globl plat_core_mask
|
||||
.globl plat_my_core_mask
|
||||
.globl plat_core_pos_by_mpidr
|
||||
.globl _disable_ldstr_pfetch_A53
|
||||
.globl _disable_ldstr_pfetch_A72
|
||||
.global _set_smmu_pagesz_64
|
||||
|
||||
/* int plat_crash_console_init(void)
|
||||
* Function to initialize the crash console
|
||||
* without a C Runtime to print crash report.
|
||||
* Clobber list : x0 - x4
|
||||
*/
|
||||
|
||||
/* int plat_crash_console_init(void)
|
||||
* Use normal console by default. Switch it to crash
|
||||
* mode so serial consoles become active again.
|
||||
* NOTE: This default implementation will only work for
|
||||
* crashes that occur after a normal console (marked
|
||||
* valid for the crash state) has been registered with
|
||||
* the console framework. To debug crashes that occur
|
||||
* earlier, the platform has to override these functions
|
||||
* with an implementation that initializes a console
|
||||
* driver with hardcoded parameters. See
|
||||
* docs/porting-guide.rst for more information.
|
||||
*/
|
||||
func plat_crash_console_init
|
||||
mov x3, x30
|
||||
mov x0, #CONSOLE_FLAG_CRASH
|
||||
bl console_switch_state
|
||||
mov x0, #1
|
||||
ret x3
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* void plat_crash_console_putc(int character)
|
||||
* Output through the normal console by default.
|
||||
*/
|
||||
func plat_crash_console_putc
|
||||
b console_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
||||
/* void plat_crash_console_flush(void)
|
||||
* Flush normal console by default.
|
||||
*/
|
||||
func plat_crash_console_flush
|
||||
b console_flush
|
||||
endfunc plat_crash_console_flush
|
||||
|
||||
/* This function implements a part of the critical interface between the psci
|
||||
* generic layer and the platform that allows the former to query the platform
|
||||
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
||||
* in case the MPIDR is invalid.
|
||||
*/
|
||||
func plat_core_pos_by_mpidr
|
||||
|
||||
b plat_core_pos
|
||||
|
||||
endfunc plat_core_pos_by_mpidr
|
||||
|
||||
#if (SYMMETRICAL_CLUSTERS)
|
||||
/* unsigned int plat_my_core_mask(void)
|
||||
* generate a mask bit for this core
|
||||
*/
|
||||
func plat_my_core_mask
|
||||
mrs x0, MPIDR_EL1
|
||||
b plat_core_mask
|
||||
endfunc plat_my_core_mask
|
||||
|
||||
/* unsigned int plat_core_mask(u_register_t mpidr)
|
||||
* generate a lsb-based mask bit for the core specified by mpidr in x0.
|
||||
*
|
||||
* SoC core = ((cluster * cpu_per_cluster) + core)
|
||||
* mask = (1 << SoC core)
|
||||
*/
|
||||
func plat_core_mask
|
||||
mov w1, wzr
|
||||
mov w2, wzr
|
||||
|
||||
/* extract cluster */
|
||||
bfxil w1, w0, #8, #8
|
||||
/* extract cpu # */
|
||||
bfxil w2, w0, #0, #8
|
||||
|
||||
mov w0, wzr
|
||||
|
||||
/* error checking */
|
||||
cmp w1, #NUMBER_OF_CLUSTERS
|
||||
b.ge 1f
|
||||
cmp w2, #CORES_PER_CLUSTER
|
||||
b.ge 1f
|
||||
|
||||
mov w0, #CORES_PER_CLUSTER
|
||||
mul w1, w1, w0
|
||||
add w1, w1, w2
|
||||
mov w2, #0x1
|
||||
lsl w0, w2, w1
|
||||
1:
|
||||
ret
|
||||
endfunc plat_core_mask
|
||||
|
||||
/*
|
||||
* unsigned int plat_my_core_pos(void)
|
||||
* generate a linear core number for this core
|
||||
*/
|
||||
func plat_my_core_pos
|
||||
mrs x0, MPIDR_EL1
|
||||
b plat_core_pos
|
||||
endfunc plat_my_core_pos
|
||||
|
||||
/*
|
||||
* unsigned int plat_core_pos(u_register_t mpidr)
|
||||
* Generate a linear core number for the core specified by mpidr.
|
||||
*
|
||||
* SoC core = ((cluster * cpu_per_cluster) + core)
|
||||
* Returns -1 if mpidr invalid
|
||||
*/
|
||||
func plat_core_pos
|
||||
mov w1, wzr
|
||||
mov w2, wzr
|
||||
bfxil w1, w0, #8, #8 /* extract cluster */
|
||||
bfxil w2, w0, #0, #8 /* extract cpu # */
|
||||
|
||||
mov w0, #-1
|
||||
|
||||
/* error checking */
|
||||
cmp w1, #NUMBER_OF_CLUSTERS
|
||||
b.ge 1f
|
||||
cmp w2, #CORES_PER_CLUSTER
|
||||
b.ge 1f
|
||||
|
||||
mov w0, #CORES_PER_CLUSTER
|
||||
mul w1, w1, w0
|
||||
add w0, w1, w2
|
||||
1:
|
||||
ret
|
||||
endfunc plat_core_pos
|
||||
|
||||
#endif
|
||||
|
||||
/* this function disables the load-store prefetch of the calling core
|
||||
* Note: this function is for A53 cores ONLY
|
||||
* in: none
|
||||
* out: none
|
||||
* uses x0
|
||||
*/
|
||||
func _disable_ldstr_pfetch_A53
|
||||
mrs x0, CORTEX_A53_CPUACTLR_EL1
|
||||
tst x0, #CORTEX_A53_CPUACTLR_EL1_L1PCTL
|
||||
b.ne 1f
|
||||
b 2f
|
||||
|
||||
.align 6
|
||||
1:
|
||||
dsb sy
|
||||
isb
|
||||
bic x0, x0, #CORTEX_A53_CPUACTLR_EL1_L1PCTL
|
||||
msr CORTEX_A53_CPUACTLR_EL1, x0
|
||||
isb
|
||||
|
||||
2:
|
||||
ret
|
||||
endfunc _disable_ldstr_pfetch_A53
|
||||
|
||||
|
||||
/* this function disables the load-store prefetch of the calling core
|
||||
* Note: this function is for A72 cores ONLY
|
||||
* in: none
|
||||
* out: none
|
||||
* uses x0
|
||||
*/
|
||||
func _disable_ldstr_pfetch_A72
|
||||
|
||||
mrs x0, CORTEX_A72_CPUACTLR_EL1
|
||||
tst x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
b.eq 1f
|
||||
b 2f
|
||||
|
||||
.align 6
|
||||
1:
|
||||
dsb sy
|
||||
isb
|
||||
orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
msr CORTEX_A72_CPUACTLR_EL1, x0
|
||||
isb
|
||||
|
||||
2:
|
||||
ret
|
||||
endfunc _disable_ldstr_pfetch_A72
|
||||
|
||||
/*
|
||||
* Function sets the SACR pagesize to 64k
|
||||
*/
|
||||
func _set_smmu_pagesz_64
|
||||
|
||||
ldr x1, =NXP_SMMU_ADDR
|
||||
ldr w0, [x1, #0x10]
|
||||
orr w0, w0, #1 << 16 /* setting to 64K page */
|
||||
str w0, [x1, #0x10]
|
||||
|
||||
ret
|
||||
endfunc _set_smmu_pagesz_64
|
||||
Reference in New Issue
Block a user