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GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)

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lai
2026-09-06 03:52:57 +08:00
commit b1928b41c0
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source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/common/plat_def_fip_uuid.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef PLAT_DEF_FIP_UUID_H
#define PLAT_DEF_FIP_UUID_H
/* PHy images configs */
#define UUID_DDR_IMEM_UDIMM_1D \
{{0x5b, 0xdb, 0xe3, 0x83}, {0xd1, 0x9f}, {0xc7, 0x06}, 0xd4, 0x91, {0x76, 0x4f, 0x9d, 0x23, 0x2d, 0x2d} }
#define UUID_DDR_IMEM_UDIMM_2D \
{{0xfa, 0x0e, 0xeb, 0x21}, {0xe0, 0x7f}, {0x8e, 0x65}, 0x95, 0xd8, {0x2b, 0x94, 0xf6, 0xb8, 0x28, 0x0a} }
#define UUID_DDR_DMEM_UDIMM_1D \
{{0xba, 0xbb, 0xfd, 0x7e}, {0x5b, 0xf0}, {0xeb, 0xb8}, 0xeb, 0x71, {0xb1, 0x85, 0x07, 0xdd, 0xe1, 0x32} }
#define UUID_DDR_DMEM_UDIMM_2D \
{{0xb6, 0x99, 0x61, 0xda}, {0xf9, 0x92}, {0x4b, 0x9e}, 0x0c, 0x49, {0x74, 0xa5, 0xe0, 0x5c, 0xbe, 0xc3} }
#define UUID_DDR_IMEM_RDIMM_1D \
{{0x42, 0x33, 0x66, 0x52}, {0xd8, 0x94}, {0x4d, 0xc1}, 0x91, 0xcc, {0x26, 0x8f, 0x7a, 0x67, 0xf1, 0xa2} }
#define UUID_DDR_IMEM_RDIMM_2D \
{{0x2e, 0x95, 0x73, 0xba}, {0xb5, 0xca}, {0x7c, 0xc7}, 0xef, 0xc9, {0x5e, 0xb0, 0x42, 0xec, 0x08, 0x7a} }
#define UUID_DDR_DMEM_RDIMM_1D \
{{0x1c, 0x51, 0x17, 0xed}, {0x30, 0x0d}, {0xae, 0xba}, 0x87, 0x03, {0x1f, 0x37, 0x85, 0xec, 0xe1, 0x44} }
#define UUID_DDR_DMEM_RDIMM_2D \
{{0xe9, 0x0a, 0x90, 0x78}, {0x11, 0xd6}, {0x8b, 0xba}, 0x24, 0x35, {0xec, 0x10, 0x75, 0x4f, 0x56, 0xa5} }
#define UUID_DDR_FW_KEY_CERT \
{{0xac, 0x4b, 0xb8, 0x9c}, {0x8f, 0xb9}, {0x11, 0xea}, 0xbc, 0x55, {0x02, 0x42, 0xac, 0x12, 0x00, 0x03} }
#define UUID_DDR_UDIMM_FW_CONTENT_CERT \
{{0x2c, 0x7f, 0x52, 0x54}, {0x70, 0x92}, {0x48, 0x40}, 0x8c, 0x34, {0x87, 0x4b, 0xbf, 0xbd, 0x9d, 0x89} }
#define UUID_DDR_RDIMM_FW_CONTENT_CERT \
{{0x94, 0xc3, 0x63, 0x30}, {0x7c, 0xf7}, {0x4f, 0x1d}, 0xaa, 0xcd, {0xb5, 0x80, 0xb2, 0xc2, 0x40, 0xa5} }
#define UUID_FUSE_PROV \
{{0xec, 0x45, 0x90, 0x42}, {0x30, 0x0d}, {0xae, 0xba}, 0x87, 0x03, {0x1f, 0x37, 0x85, 0xec, 0xe1, 0x44} }
#define UUID_FUSE_UP \
{{0x89, 0x46, 0xef, 0x78}, {0x11, 0xd6}, {0x8b, 0xba}, 0x24, 0x35, {0xec, 0x10, 0x75, 0x4f, 0x56, 0xa5} }
#endif /* PLAT_DEF_FIP_UUID_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/common/plat_tbbr_img_def.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef NXP_IMG_DEF_H
#define NXP_IMG_DEF_H
#include <export/common/tbbr/tbbr_img_def_exp.h>
#ifdef CONFIG_DDR_FIP_IMAGE
/* DDR FIP IMAGE ID */
#define DDR_FIP_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS
#define DDR_IMEM_UDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 1
#define DDR_IMEM_UDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 2
#define DDR_DMEM_UDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 3
#define DDR_DMEM_UDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 4
#define DDR_IMEM_RDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 5
#define DDR_IMEM_RDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 6
#define DDR_DMEM_RDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 7
#define DDR_DMEM_RDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 8
#define DDR_FW_KEY_CERT_ID MAX_IMG_IDS_WITH_SPMDS + 9
#define DDR_UDIMM_FW_CONTENT_CERT_ID MAX_IMG_IDS_WITH_SPMDS + 10
#define DDR_RDIMM_FW_CONTENT_CERT_ID MAX_IMG_IDS_WITH_SPMDS + 11
/* Max Images */
#define MAX_IMG_WITH_DDR_IDS MAX_IMG_IDS_WITH_SPMDS + 12
#else
#define MAX_IMG_WITH_DDR_IDS MAX_IMG_IDS_WITH_SPMDS
#endif
#ifdef POLICY_FUSE_PROVISION
/* FUSE FIP IMAGE ID */
#define FUSE_FIP_IMAGE_ID MAX_IMG_WITH_DDR_IDS
#define FUSE_PROV_IMAGE_ID MAX_IMG_WITH_DDR_IDS + 1
#define FUSE_UP_IMAGE_ID MAX_IMG_WITH_DDR_IDS + 2
#define MAX_IMG_WITH_FIMG_IDS MAX_IMG_WITH_DDR_IDS + 3
#else
#define MAX_IMG_WITH_FIMG_IDS MAX_IMG_WITH_DDR_IDS
#endif
#define MAX_NUMBER_IDS MAX_IMG_WITH_FIMG_IDS
#endif /* NXP_IMG_DEF_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/common/platform_oid.h
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/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#define DDR_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2200.1"
#define DDR_IMEM_UDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.2"
#define DDR_IMEM_UDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.3"
#define DDR_DMEM_UDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.4"
#define DDR_DMEM_UDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.5"
#define DDR_IMEM_RDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.6"
#define DDR_IMEM_RDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.7"
#define DDR_DMEM_RDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.8"
#define DDR_DMEM_RDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.9"
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
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#
# Copyright 2020 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
#-----------------------------------------------------------------------------
ifeq (${DDR_FIP_IO_STORAGE_ADDED},)
$(eval $(call add_define, PLAT_DEF_FIP_UUID))
$(eval $(call add_define, PLAT_TBBR_IMG_DEF))
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
DDR_FIP_IO_STORAGE_ADDED := 1
$(eval $(call add_define,CONFIG_DDR_FIP_IMAGE))
FIP_HANDLER_PATH := ${PLAT_COMMON_PATH}/fip_handler
FIP_HANDLER_COMMON_PATH := ${FIP_HANDLER_PATH}/common
DDR_FIP_IO_STORAGE_PATH := ${FIP_HANDLER_PATH}/ddr_fip
PLAT_INCLUDES += -I${FIP_HANDLER_COMMON_PATH}\
-I$(DDR_FIP_IO_STORAGE_PATH)
DDR_FIP_IO_SOURCES += $(DDR_FIP_IO_STORAGE_PATH)/ddr_io_storage.c
$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
ifeq (${BL_COMM_DDR_FIP_IO_NEEDED},yes)
BL_COMMON_SOURCES += ${DDR_FIP_IO_SOURCES}
else
ifeq (${BL2_DDR_FIP_IO_NEEDED},yes)
BL2_SOURCES += ${DDR_FIP_IO_SOURCES}
endif
ifeq (${BL31_DDR_FIP_IO_NEEDED},yes)
BL31_SOURCES += ${DDR_FIP_IO_SOURCES}
endif
endif
endif
#------------------------------------------------
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.c
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/*
* Copyright 2018-2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include <assert.h>
#include <string.h>
#include <io_block.h>
#include <io_driver.h>
#include <io_fip.h>
#include <io_memmap.h>
#include <io_storage.h>
#include <lib/utils.h>
#include <tools_share/firmware_image_package.h>
#include "ddr_io_storage.h"
#include "plat_common.h"
#include "platform_def.h"
/* TBD - Move these defined to the platform_def.h file.
* Keeping them for reference here
*/
extern uintptr_t backend_dev_handle;
static uint32_t ddr_fip;
static uintptr_t ddr_fip_dev_handle;
static io_block_spec_t ddr_fip_block_spec = {
.offset = PLAT_DDR_FIP_OFFSET,
.length = PLAT_DDR_FIP_MAX_SIZE
};
static const io_uuid_spec_t ddr_imem_udimm_1d_uuid_spec = {
.uuid = UUID_DDR_IMEM_UDIMM_1D,
};
static const io_uuid_spec_t ddr_imem_udimm_2d_uuid_spec = {
.uuid = UUID_DDR_IMEM_UDIMM_2D,
};
static const io_uuid_spec_t ddr_dmem_udimm_1d_uuid_spec = {
.uuid = UUID_DDR_DMEM_UDIMM_1D,
};
static const io_uuid_spec_t ddr_dmem_udimm_2d_uuid_spec = {
.uuid = UUID_DDR_DMEM_UDIMM_2D,
};
static const io_uuid_spec_t ddr_imem_rdimm_1d_uuid_spec = {
.uuid = UUID_DDR_IMEM_RDIMM_1D,
};
static const io_uuid_spec_t ddr_imem_rdimm_2d_uuid_spec = {
.uuid = UUID_DDR_IMEM_RDIMM_2D,
};
static const io_uuid_spec_t ddr_dmem_rdimm_1d_uuid_spec = {
.uuid = UUID_DDR_DMEM_RDIMM_1D,
};
static const io_uuid_spec_t ddr_dmem_rdimm_2d_uuid_spec = {
.uuid = UUID_DDR_DMEM_RDIMM_2D,
};
#if TRUSTED_BOARD_BOOT
static const io_uuid_spec_t ddr_fw_key_cert_uuid_spec = {
.uuid = UUID_DDR_FW_KEY_CERT,
};
static const io_uuid_spec_t ddr_udimm_fw_cert_uuid_spec = {
.uuid = UUID_DDR_UDIMM_FW_CONTENT_CERT,
};
static const io_uuid_spec_t ddr_rdimm_fw_cert_uuid_spec = {
.uuid = UUID_DDR_RDIMM_FW_CONTENT_CERT,
};
#endif
static int open_ddr_fip(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
/* By default, ARM platforms load images from the FIP */
static const struct plat_io_policy ddr_policies[] = {
[DDR_FIP_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&backend_dev_handle,
(uintptr_t)&ddr_fip_block_spec,
NULL
},
[DDR_IMEM_UDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_imem_udimm_1d_uuid_spec,
open_ddr_fip
},
[DDR_IMEM_UDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_imem_udimm_2d_uuid_spec,
open_ddr_fip
},
[DDR_DMEM_UDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_dmem_udimm_1d_uuid_spec,
open_ddr_fip
},
[DDR_DMEM_UDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_dmem_udimm_2d_uuid_spec,
open_ddr_fip
},
[DDR_IMEM_RDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_imem_rdimm_1d_uuid_spec,
open_ddr_fip
},
[DDR_IMEM_RDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_imem_rdimm_2d_uuid_spec,
open_ddr_fip
},
[DDR_DMEM_RDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_dmem_rdimm_1d_uuid_spec,
open_ddr_fip
},
[DDR_DMEM_RDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_dmem_rdimm_2d_uuid_spec,
open_ddr_fip
},
#if TRUSTED_BOARD_BOOT
[DDR_FW_KEY_CERT_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_fw_key_cert_uuid_spec,
open_ddr_fip
},
[DDR_UDIMM_FW_CONTENT_CERT_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_udimm_fw_cert_uuid_spec,
open_ddr_fip
},
[DDR_RDIMM_FW_CONTENT_CERT_ID - DDR_FIP_IMAGE_ID] = {
&ddr_fip_dev_handle,
(uintptr_t)&ddr_rdimm_fw_cert_uuid_spec,
open_ddr_fip
},
#endif
};
static int open_ddr_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(ddr_fip_dev_handle, (uintptr_t)DDR_FIP_IMAGE_ID);
if (result == 0) {
result = io_open(ddr_fip_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using FIP\n");
io_close(local_image_handle);
}
}
return result;
}
/* The image can be one of the DDR PHY images, which can be sleected via DDR
* policies
*/
int plat_get_ddr_fip_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec,
int (*check)(const uintptr_t spec))
{
int result = -1;
const struct plat_io_policy *policy;
if (image_id >= (DDR_FIP_IMAGE_ID + ARRAY_SIZE(ddr_policies))) {
return result;
}
policy = &ddr_policies[image_id - DDR_FIP_IMAGE_ID];
if (image_id == DDR_FIP_IMAGE_ID) {
result = check(policy->image_spec);
} else {
result = policy->check(policy->image_spec);
}
if (result == 0) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
}
return result;
}
int ddr_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev)
{
int io_result;
size_t ddr_fip_offset = PLAT_DDR_FIP_OFFSET;
/* Open connections to ddr fip and cache the handles */
io_result = io_dev_open(fip_dev_con, (uintptr_t)&ddr_fip,
&ddr_fip_dev_handle);
assert(io_result == 0);
switch (boot_dev) {
#if QSPI_BOOT
case BOOT_DEVICE_QSPI:
ddr_fip_offset += NXP_QSPI_FLASH_ADDR;
break;
#endif
#if NOR_BOOT
case BOOT_DEVICE_IFC_NOR:
ddr_fip_offset += NXP_NOR_FLASH_ADDR;
break;
#endif
#if FLEXSPI_NOR_BOOT
case BOOT_DEVICE_FLEXSPI_NOR:
ddr_fip_offset += NXP_FLEXSPI_FLASH_ADDR;
break;
#endif
default:
break;
}
ddr_fip_block_spec.offset = ddr_fip_offset;
return io_result;
}
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h
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/*
* Copyright 2018-2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef DDR_IO_STORAGE_H
#define DDR_IO_STORAGE_H
#include <drivers/io/io_driver.h>
#ifndef PLAT_DDR_FIP_OFFSET
#define PLAT_DDR_FIP_OFFSET 0x800000
#endif
#ifndef PLAT_DDR_FIP_MAX_SIZE
#define PLAT_DDR_FIP_MAX_SIZE 0x32000
#endif
int ddr_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev);
int plat_get_ddr_fip_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec,
int (*check)(const uintptr_t spec));
#endif /* DDR_IO_STORAGE_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
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#
# Copyright 2018-2020 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
NEED_FUSE := yes
$(eval $(call add_define, PLAT_DEF_FIP_UUID))
$(eval $(call add_define, POLICY_FUSE_PROVISION))
$(eval $(call add_define, PLAT_TBBR_IMG_DEF))
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,GPIO_NEEDED,BL2))
FIP_HANDLER_PATH := ${PLAT_COMMON_PATH}/fip_handler
FIP_HANDLER_COMMON_PATH := ${FIP_HANDLER_PATH}/common
FUSE_SOURCES := ${FIP_HANDLER_PATH}/fuse_fip/fuse_io_storage.c
PLAT_INCLUDES += -I${FIP_HANDLER_COMMON_PATH}\
-I${FIP_HANDLER_PATH}/fuse_fip
FUSE_FIP_NAME := fuse_fip.bin
fip_fuse: ${BUILD_PLAT}/${FUSE_FIP_NAME}
ifeq (${FUSE_PROV_FILE},)
$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
else
ifeq (${TRUSTED_BOARD_BOOT},1)
FUSE_PROV_FILE_SB = $(notdir ${FUSE_PROV_FILE})_prov.sb
FUSE_FIP_ARGS += --fuse-prov ${BUILD_PLAT}/${FUSE_PROV_FILE_SB}
FUSE_FIP_DEPS += ${BUILD_PLAT}/${FUSE_PROV_FILE_SB}
else
FUSE_FIP_ARGS += --fuse-prov ${FUSE_PROV_FILE}
FUSE_FIP_DEPS += ${FUSE_PROV_FILE}
endif
endif
ifeq (${FUSE_UP_FILE},)
else
ifeq (${TRUSTED_BOARD_BOOT},1)
FUSE_UP_FILE_SB = $(notdir ${FUSE_UP_FILE})_up.sb
FUSE_FIP_ARGS += --fuse-up ${BUILD_PLAT}/${FUSE_UP_FILE_SB}
FUSE_FIP_DEPS += ${BUILD_PLAT}/${FUSE_UP_FILE_SB}
else
FUSE_FIP_ARGS += --fuse-up ${FUSE_UP_FILE}
FUSE_FIP_DEPS += ${FUSE_UP_FILE}
endif
endif
ifeq (${TRUSTED_BOARD_BOOT},1)
ifeq (${MBEDTLS_DIR},)
else
$(error Error: Trusted Board Boot with X509 certificates not supported with FUSE_PROG build option)
endif
# Path to CST directory is required to generate the CSF header
# and prepend it to image before fip image gets generated
ifeq (${CST_DIR},)
$(error Error: CST_DIR not set)
endif
ifeq (${FUSE_INPUT_FILE},)
FUSE_INPUT_FILE := $(PLAT_DRIVERS_PATH)/auth/csf_hdr_parser/${CSF_FILE}
endif
ifeq (${FUSE_PROV_FILE},)
else
${BUILD_PLAT}/${FUSE_PROV_FILE_SB}: ${FUSE_PROV_FILE}
@echo " Generating CSF Header for $@ $<"
$(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
--app $< ${FUSE_INPUT_FILE}
endif
ifeq (${FUSE_UP_FILE},)
else
${BUILD_PLAT}/${FUSE_UP_FILE_SB}: ${FUSE_UP_FILE}
@echo " Generating CSF Header for $@ $<"
$(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
--app $< ${FUSE_INPUT_FILE}
endif
endif
${BUILD_PLAT}/${FUSE_FIP_NAME}: fiptool ${FUSE_FIP_DEPS}
ifeq (${FUSE_FIP_DEPS},)
$(error "Error: FUSE_PROV_FILE or/and FUSE_UP_FILE needs to point to the right file")
endif
${FIPTOOL} create ${FUSE_FIP_ARGS} $@
${FIPTOOL} info $@
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/fuse_fip/fuse_io.h
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/*
* Copyright 2018-2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef FUSE_IO_H
#define FUSE_IO_H
#include <drivers/io/io_driver.h>
/* Can be overridden from platform_def.h file.
*/
#ifndef PLAT_FUSE_FIP_OFFSET
#define PLAT_FUSE_FIP_OFFSET 0x880000
#endif
#ifndef PLAT_FUSE_FIP_MAX_SIZE
#define PLAT_FUSE_FIP_MAX_SIZE 0x80000
#endif
int fip_fuse_provisioning(uintptr_t image_buf, uint32_t size);
int fuse_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev);
int plat_get_fuse_image_source(unsigned int image_id,
uintptr_t *dev_handle,
uintptr_t *image_spec,
int (*check)(const uintptr_t spec));
#endif /* FUSE_IO_H */
source/trusted-firmware/trusted-firmware-a-2.8/plat/nxp/common/fip_handler/fuse_fip/fuse_io_storage.c
+223
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@@ -0,0 +1,223 @@
/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include <assert.h>
#include <string.h>
#include <common/debug.h>
#include <dcfg.h>
#include <drivers/delay_timer.h>
#include <fuse_prov.h>
#include <io_block.h>
#include <io_driver.h>
#include <io_fip.h>
#include <io_memmap.h>
#include <io_storage.h>
#include <lib/utils.h>
#include <nxp_gpio.h>
#include <sfp.h>
#include <sfp_error_codes.h>
#include <tools_share/firmware_image_package.h>
#include "fuse_io.h"
#include <load_img.h>
#include <plat/common/platform.h>
#include "plat_common.h"
#include "platform_def.h"
extern uintptr_t backend_dev_handle;
static uint32_t fuse_fip;
static uintptr_t fuse_fip_dev_handle;
static io_block_spec_t fuse_fip_block_spec = {
.offset = PLAT_FUSE_FIP_OFFSET,
.length = PLAT_FUSE_FIP_MAX_SIZE
};
static const io_uuid_spec_t fuse_prov_uuid_spec = {
.uuid = UUID_FUSE_PROV,
};
static const io_uuid_spec_t fuse_up_uuid_spec = {
.uuid = UUID_FUSE_UP,
};
static int open_fuse_fip(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
/* By default, ARM platforms load images from the FIP */
static const struct plat_io_policy fuse_policies[] = {
[FUSE_FIP_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
&backend_dev_handle,
(uintptr_t)&fuse_fip_block_spec,
NULL
},
[FUSE_PROV_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
&fuse_fip_dev_handle,
(uintptr_t)&fuse_prov_uuid_spec,
open_fuse_fip
},
[FUSE_UP_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
&fuse_fip_dev_handle,
(uintptr_t)&fuse_up_uuid_spec,
open_fuse_fip
}
};
static int open_fuse_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(fuse_fip_dev_handle, (uintptr_t)FUSE_FIP_IMAGE_ID);
if (result == 0) {
result = io_open(fuse_fip_dev_handle,
spec,
&local_image_handle);
if (result == 0) {
VERBOSE("Using FIP\n");
io_close(local_image_handle);
}
}
return result;
}
/* The image can be one of the DDR PHY images, which can be sleected via DDR
* policies
*/
int plat_get_fuse_image_source(unsigned int image_id,
uintptr_t *dev_handle,
uintptr_t *image_spec,
int (*check)(const uintptr_t spec))
{
int result;
const struct plat_io_policy *policy;
assert(image_id < (FUSE_FIP_IMAGE_ID + ARRAY_SIZE(fuse_policies)));
policy = &fuse_policies[image_id - FUSE_FIP_IMAGE_ID];
if (image_id == FUSE_FIP_IMAGE_ID) {
result = check(policy->image_spec);
} else {
result = policy->check(policy->image_spec);
}
if (result == 0) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
}
return result;
}
int fuse_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev)
{
int io_result;
size_t fuse_fip_offset = PLAT_FUSE_FIP_OFFSET;
/* Open connections to fuse fip and cache the handles */
io_result = io_dev_open(fip_dev_con, (uintptr_t)&fuse_fip,
&fuse_fip_dev_handle);
assert(io_result == 0);
switch (boot_dev) {
#if QSPI_BOOT
case BOOT_DEVICE_QSPI:
fuse_fip_offset += NXP_QSPI_FLASH_ADDR;
break;
#endif
#if NOR_BOOT
case BOOT_DEVICE_IFC_NOR:
fuse_fip_offset += NXP_NOR_FLASH_ADDR;
break;
#endif
#if FLEXSPI_NOR_BOOT
case BOOT_DEVICE_FLEXSPI_NOR:
fuse_fip_offset += NXP_FLEXSPI_FLASH_ADDR;
break;
#endif
default:
break;
}
fuse_fip_block_spec.offset = fuse_fip_offset;
return io_result;
}
int fip_fuse_provisioning(uintptr_t image_buf, uint32_t size)
{
uint32_t bit_num;
uint32_t *gpio_base_addr = NULL;
struct fuse_hdr_t *fuse_hdr = NULL;
uint8_t barker[] = {0x68U, 0x39U, 0x27U, 0x81U};
int ret = -1;
if (sfp_check_oem_wp() == 0) {
ret = load_img(FUSE_PROV_IMAGE_ID, &image_buf, &size);
if (ret != 0) {
ERROR("Failed to load FUSE PRIV image\n");
assert(ret == 0);
}
fuse_hdr = (struct fuse_hdr_t *)image_buf;
/* Check barker code */
if (memcmp(fuse_hdr->barker, barker, sizeof(barker)) != 0) {
ERROR("FUSE Barker code mismatch.\n");
error_handler(ERROR_FUSE_BARKER);
return 1;
}
/* Check if GPIO pin to be set for POVDD */
if (((fuse_hdr->flags >> FLAG_POVDD_SHIFT) & 0x1) != 0) {
gpio_base_addr =
select_gpio_n_bitnum(fuse_hdr->povdd_gpio,
&bit_num);
/*
* Add delay so that Efuse gets the power
* when GPIO is enabled.
*/
ret = set_gpio_bit(gpio_base_addr, bit_num);
mdelay(EFUSE_POWERUP_DELAY_mSec);
} else {
ret = (board_enable_povdd() == true) ? 0 : PLAT_ERROR_ENABLE_POVDD;
}
if (ret != 0) {
ERROR("Error enabling board POVDD: %d\n", ret);
ERROR("Only SFP mirror register will be set.\n");
}
provision_fuses(image_buf, ret == 0);
/* Check if GPIO pin to be reset for POVDD */
if (((fuse_hdr->flags >> FLAG_POVDD_SHIFT) & 0x1) != 0) {
if (gpio_base_addr == NULL) {
gpio_base_addr =
select_gpio_n_bitnum(
fuse_hdr->povdd_gpio,
&bit_num);
}
ret = clr_gpio_bit(gpio_base_addr, bit_num);
} else {
ret = board_disable_povdd() ? 0 : PLAT_ERROR_DISABLE_POVDD;
}
if (ret != 0) {
ERROR("Error disabling board POVDD: %d\n", ret);
}
}
return 0;
}