GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <mmu_def.h>
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#include <plat/common/platform.h>
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#include "plat_common.h"
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#include "platform_def.h"
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const mmap_region_t *plat_ls_get_mmap(void);
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/*
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* Table of memory regions for various BL stages to map using the MMU.
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* This doesn't include Trusted SRAM as arm_setup_page_tables() already
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* takes care of mapping it.
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*
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* The flash needs to be mapped as writable in order to erase the FIP's Table of
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* Contents in case of unrecoverable error (see plat_error_handler()).
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*/
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#ifdef IMAGE_BL2
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const mmap_region_t plat_ls_mmap[] = {
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LS_MAP_CCSR,
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{0}
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};
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#endif
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#ifdef IMAGE_BL31
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const mmap_region_t plat_ls_mmap[] = {
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LS_MAP_CCSR,
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#ifdef NXP_DCSR_ADDR
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LS_MAP_DCSR,
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#endif
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LS_MAP_OCRAM,
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{0}
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};
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#endif
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#ifdef IMAGE_BL32
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const mmap_region_t plat_ls_mmap[] = {
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LS_MAP_CCSR,
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LS_MAP_BL32_SEC_MEM,
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{0}
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};
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#endif
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/* Weak definitions may be overridden in specific NXP SoC */
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#pragma weak plat_get_ns_image_entrypoint
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#pragma weak plat_ls_get_mmap
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#if defined(IMAGE_BL31) || !defined(CONFIG_DDR_FIP_IMAGE)
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static void mmap_add_ddr_regions_statically(void)
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{
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int i = 0;
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dram_regions_info_t *info_dram_regions = get_dram_regions_info();
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/* MMU map for Non-Secure DRAM Regions */
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VERBOSE("DRAM Region %d: %p - %p\n", i,
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(void *) info_dram_regions->region[i].addr,
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size
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- 1));
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mmap_add_region(info_dram_regions->region[i].addr,
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info_dram_regions->region[i].addr,
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info_dram_regions->region[i].size,
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MT_MEMORY | MT_RW | MT_NS);
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/* MMU map for Secure DDR Region on DRAM-0 */
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if (info_dram_regions->region[i].size >
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) {
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VERBOSE("Secure DRAM Region %d: %p - %p\n", i,
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size),
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size
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+ NXP_SECURE_DRAM_SIZE
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+ NXP_SP_SHRD_DRAM_SIZE
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- 1));
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mmap_add_region((info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size),
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(info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size),
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE),
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MT_MEMORY | MT_RW | MT_SECURE);
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}
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#ifdef IMAGE_BL31
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for (i = 1; i < info_dram_regions->num_dram_regions; i++) {
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if (info_dram_regions->region[i].size == 0)
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break;
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VERBOSE("DRAM Region %d: %p - %p\n", i,
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(void *) info_dram_regions->region[i].addr,
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size
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- 1));
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mmap_add_region(info_dram_regions->region[i].addr,
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info_dram_regions->region[i].addr,
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info_dram_regions->region[i].size,
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MT_MEMORY | MT_RW | MT_NS);
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}
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#endif
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}
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#endif
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#if defined(PLAT_XLAT_TABLES_DYNAMIC)
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void mmap_add_ddr_region_dynamically(void)
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{
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int ret, i = 0;
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dram_regions_info_t *info_dram_regions = get_dram_regions_info();
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/* MMU map for Non-Secure DRAM Regions */
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VERBOSE("DRAM Region %d: %p - %p\n", i,
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(void *) info_dram_regions->region[i].addr,
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size
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- 1));
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ret = mmap_add_dynamic_region(info_dram_regions->region[i].addr,
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info_dram_regions->region[i].addr,
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info_dram_regions->region[i].size,
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MT_MEMORY | MT_RW | MT_NS);
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if (ret != 0) {
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ERROR("Failed to add dynamic memory region\n");
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panic();
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}
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/* MMU map for Secure DDR Region on DRAM-0 */
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if (info_dram_regions->region[i].size >
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) {
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VERBOSE("Secure DRAM Region %d: %p - %p\n", i,
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size),
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size
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+ NXP_SECURE_DRAM_SIZE
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+ NXP_SP_SHRD_DRAM_SIZE
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- 1));
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ret = mmap_add_dynamic_region((info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size),
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(info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size),
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE),
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MT_MEMORY | MT_RW | MT_SECURE);
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if (ret != 0) {
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ERROR("Failed to add dynamic memory region\n");
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panic();
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}
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}
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#ifdef IMAGE_BL31
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for (i = 1; i < info_dram_regions->num_dram_regions; i++) {
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if (info_dram_regions->region[i].size == 0) {
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break;
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}
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VERBOSE("DRAM Region %d: %p - %p\n", i,
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(void *) info_dram_regions->region[i].addr,
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(void *) (info_dram_regions->region[i].addr
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+ info_dram_regions->region[i].size
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- 1));
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ret = mmap_add_dynamic_region(info_dram_regions->region[i].addr,
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info_dram_regions->region[i].addr,
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info_dram_regions->region[i].size,
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MT_MEMORY | MT_RW | MT_NS);
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if (ret != 0) {
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ERROR("Failed to add dynamic memory region\n");
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panic();
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}
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}
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#endif
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}
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#endif
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/*
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* Set up the page tables for the generic and platform-specific memory regions.
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* The extents of the generic memory regions are specified by the function
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* arguments and consist of:
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* - Trusted SRAM seen by the BL image;
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* - Code section;
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* - Read-only data section;
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* - Coherent memory region, if applicable.
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*/
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void ls_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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,
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uintptr_t coh_start,
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uintptr_t coh_limit
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#endif
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)
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{
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/*
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* Map the Trusted SRAM with appropriate memory attributes.
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* Subsequent mappings will adjust the attributes for specific regions.
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*/
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VERBOSE("Memory seen by this BL image: %p - %p\n",
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(void *) total_base, (void *) (total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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/* Re-map the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *) code_start, (void *) code_limit);
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mmap_add_region(code_start, code_start,
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code_limit - code_start,
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MT_CODE | MT_SECURE);
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/* Re-map the read-only data section */
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VERBOSE("Read-only data region: %p - %p\n",
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(void *) rodata_start, (void *) rodata_limit);
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mmap_add_region(rodata_start, rodata_start,
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rodata_limit - rodata_start,
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MT_RO_DATA | MT_SECURE);
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#if USE_COHERENT_MEM
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/* Re-map the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *) coh_start, (void *) coh_limit);
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mmap_add_region(coh_start, coh_start,
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coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* Now (re-)map the platform-specific memory regions */
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mmap_add(plat_ls_get_mmap());
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#if defined(IMAGE_BL31) || !defined(CONFIG_DDR_FIP_IMAGE)
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mmap_add_ddr_regions_statically();
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#endif
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/* Create the page tables to reflect the above mappings */
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init_xlat_tables();
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}
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/*******************************************************************************
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* Returns NXP platform specific memory map regions.
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******************************************************************************/
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const mmap_region_t *plat_ls_get_mmap(void)
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{
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return plat_ls_mmap;
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}
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/*
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* This function get the number of clusters and cores count per cluster
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* in the SoC.
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*/
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void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count,
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uint8_t *num_clusters, uint8_t *cores_per_cluster)
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{
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const soc_info_t *soc_info = get_soc_info();
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*num_clusters = NUMBER_OF_CLUSTERS;
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*cores_per_cluster = CORES_PER_CLUSTER;
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unsigned int i;
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for (i = 0U; i < ps_count; i++) {
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if (soc_list[i].version == soc_info->svr_reg.bf_ver.version) {
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*num_clusters = soc_list[i].num_clusters;
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*cores_per_cluster = soc_list[i].cores_per_cluster;
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break;
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}
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}
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VERBOSE("NUM of cluster = 0x%x, Cores per cluster = 0x%x\n",
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*num_clusters, *cores_per_cluster);
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}
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