GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright 2017-2018, 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NS_ACCESS_H
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#define NS_ACCESS_H
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#include <csu.h>
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enum csu_cslx_ind {
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CSU_CSLX_PCIE2_IO = 0,
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CSU_CSLX_PCIE1_IO,
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CSU_CSLX_MG2TPR_IP,
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CSU_CSLX_IFC_MEM,
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CSU_CSLX_OCRAM,
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CSU_CSLX_GIC,
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CSU_CSLX_PCIE1,
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CSU_CSLX_OCRAM2,
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CSU_CSLX_QSPI_MEM,
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CSU_CSLX_PCIE2,
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CSU_CSLX_SATA,
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CSU_CSLX_USB1,
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CSU_CSLX_QM_BM_SWPORTAL,
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CSU_CSLX_PCIE3 = 16,
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CSU_CSLX_PCIE3_IO,
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CSU_CSLX_USB3 = 20,
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CSU_CSLX_USB2,
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CSU_CSLX_PFE = 23,
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CSU_CSLX_SERDES = 32,
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CSU_CSLX_QDMA,
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CSU_CSLX_LPUART2,
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CSU_CSLX_LPUART1,
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CSU_CSLX_LPUART4,
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CSU_CSLX_LPUART3,
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CSU_CSLX_LPUART6,
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CSU_CSLX_LPUART5,
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CSU_CSLX_DSPI1 = 41,
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CSU_CSLX_QSPI,
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CSU_CSLX_ESDHC,
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CSU_CSLX_IFC = 45,
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CSU_CSLX_I2C1,
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CSU_CSLX_USB_2,
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CSU_CSLX_I2C3 = 48,
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CSU_CSLX_I2C2,
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CSU_CSLX_DUART2 = 50,
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CSU_CSLX_DUART1,
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CSU_CSLX_WDT2,
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CSU_CSLX_WDT1,
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CSU_CSLX_EDMA,
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CSU_CSLX_SYS_CNT,
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CSU_CSLX_DMA_MUX2,
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CSU_CSLX_DMA_MUX1,
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CSU_CSLX_DDR,
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CSU_CSLX_QUICC,
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CSU_CSLX_DCFG_CCU_RCPM = 60,
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CSU_CSLX_SECURE_BOOTROM,
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CSU_CSLX_SFP,
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CSU_CSLX_TMU,
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CSU_CSLX_SECURE_MONITOR,
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CSU_CSLX_SCFG,
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CSU_CSLX_FM = 66,
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CSU_CSLX_SEC5_5,
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CSU_CSLX_BM,
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CSU_CSLX_QM,
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CSU_CSLX_GPIO2 = 70,
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CSU_CSLX_GPIO1,
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CSU_CSLX_GPIO4,
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CSU_CSLX_GPIO3,
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CSU_CSLX_PLATFORM_CONT,
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CSU_CSLX_CSU,
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CSU_CSLX_IIC4 = 77,
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CSU_CSLX_WDT4,
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CSU_CSLX_WDT3,
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CSU_CSLX_ESDHC2 = 80,
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CSU_CSLX_WDT5 = 81,
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CSU_CSLX_SAI2,
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CSU_CSLX_SAI1,
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CSU_CSLX_SAI4,
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CSU_CSLX_SAI3,
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CSU_CSLX_FTM2 = 86,
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CSU_CSLX_FTM1,
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CSU_CSLX_FTM4,
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CSU_CSLX_FTM3,
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CSU_CSLX_FTM6 = 90,
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CSU_CSLX_FTM5,
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CSU_CSLX_FTM8,
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CSU_CSLX_FTM7,
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CSU_CSLX_DSCR = 121,
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};
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struct csu_ns_dev_st ns_dev[] = {
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{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
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{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
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{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
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{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
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{CSU_CSLX_OCRAM, CSU_S_SUP_RW},
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{CSU_CSLX_GIC, CSU_ALL_RW},
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{CSU_CSLX_PCIE1, CSU_ALL_RW},
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{CSU_CSLX_OCRAM2, CSU_S_SUP_RW},
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{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
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{CSU_CSLX_PCIE2, CSU_ALL_RW},
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{CSU_CSLX_SATA, CSU_ALL_RW},
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{CSU_CSLX_USB1, CSU_ALL_RW},
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{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
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{CSU_CSLX_PCIE3, CSU_ALL_RW},
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{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
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{CSU_CSLX_USB3, CSU_ALL_RW},
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{CSU_CSLX_USB2, CSU_ALL_RW},
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{CSU_CSLX_PFE, CSU_ALL_RW},
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{CSU_CSLX_SERDES, CSU_ALL_RW},
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{CSU_CSLX_QDMA, CSU_ALL_RW},
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{CSU_CSLX_LPUART2, CSU_ALL_RW},
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{CSU_CSLX_LPUART1, CSU_ALL_RW},
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{CSU_CSLX_LPUART4, CSU_ALL_RW},
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{CSU_CSLX_LPUART3, CSU_ALL_RW},
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{CSU_CSLX_LPUART6, CSU_ALL_RW},
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{CSU_CSLX_LPUART5, CSU_ALL_RW},
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{CSU_CSLX_DSPI1, CSU_ALL_RW},
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{CSU_CSLX_QSPI, CSU_ALL_RW},
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{CSU_CSLX_ESDHC, CSU_ALL_RW},
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{CSU_CSLX_IFC, CSU_ALL_RW},
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{CSU_CSLX_I2C1, CSU_ALL_RW},
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{CSU_CSLX_USB_2, CSU_ALL_RW},
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{CSU_CSLX_I2C3, CSU_ALL_RW},
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{CSU_CSLX_I2C2, CSU_ALL_RW},
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{CSU_CSLX_DUART2, CSU_ALL_RW},
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{CSU_CSLX_DUART1, CSU_ALL_RW},
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{CSU_CSLX_WDT2, CSU_ALL_RW},
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{CSU_CSLX_WDT1, CSU_ALL_RW},
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{CSU_CSLX_EDMA, CSU_ALL_RW},
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{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
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{CSU_CSLX_DDR, CSU_ALL_RW},
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{CSU_CSLX_QUICC, CSU_ALL_RW},
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{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
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{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
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{CSU_CSLX_SFP, CSU_ALL_RW},
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{CSU_CSLX_TMU, CSU_ALL_RW},
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{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
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{CSU_CSLX_SCFG, CSU_ALL_RW},
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{CSU_CSLX_FM, CSU_ALL_RW},
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{CSU_CSLX_SEC5_5, CSU_ALL_RW},
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{CSU_CSLX_BM, CSU_ALL_RW},
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{CSU_CSLX_QM, CSU_ALL_RW},
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{CSU_CSLX_GPIO2, CSU_ALL_RW},
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{CSU_CSLX_GPIO1, CSU_ALL_RW},
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{CSU_CSLX_GPIO4, CSU_ALL_RW},
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{CSU_CSLX_GPIO3, CSU_ALL_RW},
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{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
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{CSU_CSLX_CSU, CSU_ALL_RW},
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{CSU_CSLX_IIC4, CSU_ALL_RW},
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{CSU_CSLX_WDT4, CSU_ALL_RW},
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{CSU_CSLX_WDT3, CSU_ALL_RW},
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{CSU_CSLX_ESDHC2, CSU_ALL_RW},
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{CSU_CSLX_WDT5, CSU_ALL_RW},
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{CSU_CSLX_SAI2, CSU_ALL_RW},
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{CSU_CSLX_SAI1, CSU_ALL_RW},
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{CSU_CSLX_SAI4, CSU_ALL_RW},
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{CSU_CSLX_SAI3, CSU_ALL_RW},
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{CSU_CSLX_FTM2, CSU_ALL_RW},
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{CSU_CSLX_FTM1, CSU_ALL_RW},
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{CSU_CSLX_FTM4, CSU_ALL_RW},
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{CSU_CSLX_FTM3, CSU_ALL_RW},
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{CSU_CSLX_FTM6, CSU_ALL_RW},
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{CSU_CSLX_FTM5, CSU_ALL_RW},
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{CSU_CSLX_FTM8, CSU_ALL_RW},
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{CSU_CSLX_FTM7, CSU_ALL_RW},
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{CSU_CSLX_DSCR, CSU_ALL_RW},
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};
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#endif /* NS_ACCESS_H */
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@@ -0,0 +1,125 @@
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/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include <dcfg_lsch2.h>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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/* DDR Regions Info */
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#define NUM_DRAM_REGIONS U(3)
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#define NXP_DRAM0_ADDR ULL(0x80000000)
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#define NXP_DRAM0_MAX_SIZE ULL(0x80000000) /* 2 GB */
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#define NXP_DRAM1_ADDR ULL(0x880000000)
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#define NXP_DRAM1_MAX_SIZE ULL(0x780000000) /* 30 GB */
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#define NXP_DRAM2_ADDR ULL(0x8800000000)
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#define NXP_DRAM2_MAX_SIZE ULL(0x7800000000) /* 480 GB */
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/*DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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/*
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* SVR Definition (not include major and minor rev)
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* A: without security
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* AE: with security
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*/
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#define SVR_LS1026A 0x870709
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#define SVR_LS1026AE 0x870708
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#define SVR_LS1046A 0x870701
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#define SVR_LS1046AE 0x870700
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/* Number of cores in platform */
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/* Used by common code for array initialization */
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#define NUMBER_OF_CLUSTERS U(1)
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#define CORES_PER_CLUSTER U(4)
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#define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
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/*
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* Required LS standard platform porting definitions
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* for CCI-400
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*/
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#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER U(1)
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#define NXP_UART_CLK_DIVIDER U(2)
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS U(1)
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/*
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* set this switch to 1 if you need to keep the debug block
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* clocked during system power-down
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*/
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#define DEBUG_ACTIVE 0
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/*
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* pwr mgmt features supported in the soc-specific code:
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* value == 0x0 the soc code does not support this feature
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* value != 0x0 the soc code supports this feature
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*/
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#define SOC_CORE_RELEASE 0x1
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#define SOC_CORE_RESTART 0x1
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#define SOC_CORE_OFF 0x1
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#define SOC_CORE_STANDBY 0x1
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#define SOC_CORE_PWR_DWN 0x1
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#define SOC_CLUSTER_STANDBY 0x1
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#define SOC_CLUSTER_PWR_DWN 0x1
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#define SOC_SYSTEM_STANDBY 0x1
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#define SOC_SYSTEM_PWR_DWN 0x1
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#define SOC_SYSTEM_OFF 0x1
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#define SOC_SYSTEM_RESET 0x1
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/* Start: Macros used by lib/psci files */
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*
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* CACHE_WRITEBACK_GRANULE is defined in soc.def
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*/
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/* One cache line needed for bakery locks on ARM platforms */
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#ifndef __ASSEMBLER__
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/* CCI slave interfaces */
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static const int cci_map[] = {
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NXP_CCI_CLUSTER0_SL_IFACE_IX,
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};
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void soc_init_lowlevel(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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#endif
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#endif /* SOC_H */
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