GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018,2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_MACROS_S__
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#define __PLAT_MACROS_S__
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.section .rodata.gic_reg_name, "aS"
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/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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/* Applicable only to GICv3 with SRE enabled */
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icc_regs:
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.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
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/* Registers common to both GICv2 and GICv3 */
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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/** Macro : plat_crash_print_regs
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* This macro allows the crash reporting routine to print GIC registers
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* in case of an unhandled exception in BL31. This aids in debugging and
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* this macro can be defined to be empty in case GIC register reporting is
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* not desired.
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* The below required platform porting macro
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* prints out relevant GIC registers whenever an
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* unhandled exception is taken in BL31.
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* Clobbers: x0 - x10, x26, x27, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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print_gic_regs:
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ldr x26, =QTI_GICD_BASE
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ldr x27, =QTI_GICC_BASE
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/* Check for GICv3 system register access */
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mrs x7, id_aa64pfr0_el1
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ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x7, #1
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b.ne print_gicv2
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/* Check for SRE enable */
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mrs x8, ICC_SRE_EL3
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tst x8, #ICC_SRE_SRE_BIT
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b.eq print_gicv2
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/* Load the icc reg list to x6 */
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adr x6, icc_regs
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/* Load the icc regs to gp regs used by str_in_crash_buf_print */
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mrs x8, ICC_HPPIR0_EL1
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mrs x9, ICC_HPPIR1_EL1
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mrs x10, ICC_CTLR_EL3
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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b print_gic_common
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print_gicv2:
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/* Load the gicc reg list to x6 */
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adr x6, gicc_regs
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/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x27, #GICC_HPPIR]
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ldr w9, [x27, #GICC_AHPPIR]
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ldr w10, [x27, #GICC_CTLR]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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print_gic_common:
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/* Print the GICD_ISPENDR regs */
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add x7, x26, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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gicd_ispendr_loop:
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sub x4, x7, x26
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cmp x4, #0x280
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b.eq exit_print_gic_regs
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bl asm_print_hex
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b gicd_ispendr_loop
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exit_print_gic_regs:
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.endm
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#endif /* __PLAT_MACROS_S__ */
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@@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_BOARD_DEF_H
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#define QTI_BOARD_DEF_H
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/*
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* Required platform porting definitions common to all ARM
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* development platforms
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*/
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/*
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* Defines used to retrieve QTI SOC Version
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*/
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#define JEDEC_QTI_BKID U(0x0)
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#define JEDEC_QTI_MFID U(0x70)
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#define QTI_SOC_CONTINUATION_SHIFT U(24)
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#define QTI_SOC_IDENTIFICATION_SHIFT U(16)
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x1000
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/*
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* PLAT_QTI_MMAP_ENTRIES depends on the number of entries in the
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* plat_qti_mmap array defined for each BL stage.
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*/
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#define PLAT_QTI_MMAP_ENTRIES 12
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/*
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* Platform specific page table and MMU setup constants
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*/
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#define MAX_XLAT_TABLES 12
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#endif /* QTI_BOARD_DEF_H */
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_CPU_H
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#define QTI_CPU_H
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/* KRYO-4xx Gold MIDR */
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#define QTI_KRYO4_GOLD_MIDR 0x517F804D
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/* KRYO-4xx Silver MIDR */
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#define QTI_KRYO4_SILVER_MIDR 0x517F805D
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/* KRYO-6xx Gold MIDR */
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#define QTI_KRYO6_GOLD_MIDR 0x412FD410
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/* KRYO-6xx Silver MIDR */
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#define QTI_KRYO6_SILVER_MIDR 0x412FD050
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#endif /* QTI_CPU_H */
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+12
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/*
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* Copyright (c) 2018,2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_INTERRUPT_SVC_H
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#define QTI_INTERRUPT_SVC_H
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int qti_interrupt_svc_init(void);
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#endif /* QTI_INTERRUPT_SVC_H */
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@@ -0,0 +1,62 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_PLAT_H
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#define QTI_PLAT_H
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#include <stdint.h>
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#include <common/bl_common.h>
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#include <lib/cassert.h>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/*
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* Utility functions common to QTI platforms
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*/
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int qti_mmap_add_dynamic_region(uintptr_t base_pa, size_t size,
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unsigned int attr);
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int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
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/*
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* Utility functions common to ARM standard platforms
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*/
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void qti_setup_page_tables(
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uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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);
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/*
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* Mandatory functions required in ARM standard platforms
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*/
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void plat_qti_gic_driver_init(void);
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void plat_qti_gic_init(void);
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void plat_qti_gic_cpuif_enable(void);
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void plat_qti_gic_cpuif_disable(void);
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void plat_qti_gic_pcpu_init(void);
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/*
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* Optional functions required in ARM standard platforms
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*/
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unsigned int plat_qti_core_pos_by_mpidr(u_register_t mpidr);
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unsigned int plat_qti_my_cluster_pos(void);
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void gic_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr);
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void qti_pmic_prepare_reset(void);
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void qti_pmic_prepare_shutdown(void);
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typedef struct chip_id_info {
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uint16_t jtag_id;
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uint16_t chipinfo_id;
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} chip_id_info_t;
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#endif /* QTI_PLAT_H */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_RNG_H
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#define QTI_RNG_H
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#include <stdint.h>
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int qti_rng_get_data(uint8_t *out, uint32_t out_len);
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#endif /* QTI_RNG_H */
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_UART_CONSOLE_H
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#define QTI_UART_CONSOLE_H
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#include <drivers/console.h>
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#ifndef __ASSEMBLER__
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int qti_console_uart_register(console_t *console, uintptr_t uart_base_addr);
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#endif /* __ASSEMBLER__ */
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#endif /* QTI_UART_CONSOLE_H */
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/*
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* Copyright (c) 2020, Google LLC. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SPMI_ARB_H
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#define SPMI_ARB_H
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#include <stdint.h>
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/*******************************************************************************
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* WARNING: This driver does not arbitrate access with the kernel. These APIs
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* must only be called when the kernel is known to be quiesced (such as before
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* boot or while the system is shutting down).
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******************************************************************************/
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/* 32-bit addresses combine (U)SID, PID and register address. */
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int spmi_arb_read8(uint32_t addr);
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int spmi_arb_write8(uint32_t addr, uint8_t data);
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#endif /* SPMI_ARB_H */
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