GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <msm8916_mmap.h>
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#define APCS_TCM_START_ADDR 0x10
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#define APCS_TCM_REDIRECT_EN_0 BIT_32(0)
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_panic_handler
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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.globl plat_reset_handler
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.globl platform_mem_init
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.globl msm8916_entry_point
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/* -------------------------------------------------
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* int plat_crash_console_init(void)
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* Initialize the crash console.
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* Out: x0 - 1 on success, 0 on error
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* Clobber list : x0 - x4
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* -------------------------------------------------
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*/
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func plat_crash_console_init
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mov x1, #BLSP_UART2_BASE
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/*
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* If the non-secure world has been actively using the UART there might
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* be still some characters left to be sent in the FIFO. In that case,
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* resetting the transmitter too early might cause all output to become
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* corrupted. To avoid that, try to flush (wait until FIFO empty) first.
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*/
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mov x4, lr
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bl console_uartdm_core_flush
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mov lr, x4
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mov x0, #1
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b console_uartdm_core_init
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endfunc plat_crash_console_init
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/* -------------------------------------------------
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* int plat_crash_console_putc(int c)
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* Print a character on the crash console.
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* In : w0 - character to be printed
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* Out: w0 - printed character on success
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* Clobber list : x1, x2
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* -------------------------------------------------
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*/
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func plat_crash_console_putc
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mov x1, #BLSP_UART2_BASE
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b console_uartdm_core_putc
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endfunc plat_crash_console_putc
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/* -------------------------------------------------
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* void plat_crash_console_flush(void)
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* Force a write of all buffered data that has not
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* been output.
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* Clobber list : x1, x2
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* -------------------------------------------------
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*/
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func plat_crash_console_flush
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mov x1, #BLSP_UART2_BASE
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b console_uartdm_core_flush
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endfunc plat_crash_console_flush
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/* -------------------------------------------------
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* void plat_panic_handler(void) __dead
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* Called when an unrecoverable error occurs.
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* -------------------------------------------------
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*/
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func plat_panic_handler
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/* Try to shutdown/reset */
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mov_imm x0, MPM_PS_HOLD
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str wzr, [x0]
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1: b 1b
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endfunc plat_panic_handler
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/* -------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* Out: x0 - index of the calling CPU
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* -------------------------------------------------
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*/
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func plat_my_core_pos
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/* There is just a single cluster so this is very simple */
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mrs x0, mpidr_el1
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and x0, x0, #MPIDR_CPU_MASK
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ret
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endfunc plat_my_core_pos
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/* -------------------------------------------------
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* uintptr_t plat_get_my_entrypoint(void)
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* Distinguish cold and warm boot and return warm boot
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* entry address if available.
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* Out: x0 - warm boot entry point or 0 on cold boot
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* -------------------------------------------------
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*/
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func plat_get_my_entrypoint
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ldr x0, msm8916_entry_point
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ret
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endfunc plat_get_my_entrypoint
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/* -------------------------------------------------
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* void plat_reset_handler(void)
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* Perform additional initialization after reset.
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* Clobber list : x0 - x18, x30
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* -------------------------------------------------
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*/
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func plat_reset_handler
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/*
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* Check if the CPU is running at the correct address.
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* During cold boot the CPU enters here at the wrong address
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* using the "boot remapper". (It remaps the BL31_BASE to
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* the CPU reset address 0x0).
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*/
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mov x0, #BL31_BASE
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adr x1, bl31_entrypoint
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cmp x0, x1
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b.ne _remapped_cold_boot
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/* Already running at correct address, just return directly */
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ret
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_remapped_cold_boot:
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/*
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* The previous boot stage seems to use the L2 cache as TCM.
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* Disable the TCM redirect before enabling caches to avoid
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* strange crashes.
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*/
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mov x2, #APCS_CFG
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ldr w3, [x2, #APCS_TCM_START_ADDR]
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and w3, w3, #~APCS_TCM_REDIRECT_EN_0
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str w3, [x2, #APCS_TCM_START_ADDR]
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/* Enter BL31 again at the real address */
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br x0
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endfunc plat_reset_handler
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/* -------------------------------------------------
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* void platform_mem_init(void)
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* Performs additional memory initialization early
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* in the boot process.
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* -------------------------------------------------
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*/
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func platform_mem_init
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/* Nothing to do here, all memory is already initialized */
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ret
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endfunc platform_mem_init
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.data
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.align 3
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/* -------------------------------------------------
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* Warm boot entry point for CPU. Set by PSCI code.
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* -------------------------------------------------
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*/
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msm8916_entry_point:
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.quad 0
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+154
@@ -0,0 +1,154 @@
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/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* Based on aarch64/skeleton_console.S:
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <console_macros.S>
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/* UART DM registers */
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#define UART_DM_DMEN 0x03c /* DMA / data packing */
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#define UART_DM_SR 0x0a4 /* status register */
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#define UART_DM_CR 0x0a8 /* command register */
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#define UART_DM_TF 0x100 /* transmit FIFO */
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#define UART_DM_DMEN_TX_SC BIT_32(4) /* TX single character mode */
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#define UART_DM_SR_TXRDY_BIT 2 /* TX FIFO has space */
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#define UART_DM_SR_TXEMT_BIT 3 /* TX FIFO is empty */
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#define UART_DM_CR_RESET_RX (U(0x01) << 4) /* reset receiver */
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#define UART_DM_CR_RESET_TX (U(0x02) << 4) /* reset transmitter */
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#define UART_DM_CR_TX_ENABLE BIT_32(2) /* enable transmitter */
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.globl console_uartdm_register
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.globl console_uartdm_core_init
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.globl console_uartdm_putc
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.globl console_uartdm_core_putc
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.globl console_uartdm_flush
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.globl console_uartdm_core_flush
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/* -----------------------------------------------------------
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* int console_uartdm_register(console_t *console,
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* uintptr_t base_addr)
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* Function to initialize and register the console. The caller
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* needs to pass an empty console_t structure in which *MUST*
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* be allocated in persistent memory (e.g. a global or static
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* local variable, *NOT* on the stack).
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* In : x0 - pointer to empty console_t structure
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* x1 - base address
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* Out: x0 - 1 on success, 0 on error
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* Clobber list : x0 - x7
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* -----------------------------------------------------------
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*/
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func console_uartdm_register
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str x1, [x0, #CONSOLE_T_BASE]
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mov x7, lr
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bl console_uartdm_core_init
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mov lr, x7
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/* Register the new console */
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finish_console_register uartdm putc=1, flush=1
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endfunc console_uartdm_register
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/* -----------------------------------------------------------
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* void console_uartdm_core_init(unused, uintptr_t base_addr)
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* Function to initialize the console.
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* In : x0 - unused
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* x1 - base address
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* Out: void
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* Clobber list : x1, x2, x3
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* -----------------------------------------------------------
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*/
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func console_uartdm_core_init
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/* Reset receiver */
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mov w3, #UART_DM_CR_RESET_RX
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str w3, [x1, #UART_DM_CR]
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/* Reset transmitter */
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mov w3, #UART_DM_CR_RESET_TX
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str w3, [x1, #UART_DM_CR]
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/*
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* Disable BAM/DMA modes but enable single-character mode for TX.
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* The single character mode allows simplifying the putc implementation
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* since characters can be written directly to the FIFO instead of
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* having to initiate a new transfer and waiting for its completion.
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*/
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mov w3, #UART_DM_DMEN_TX_SC
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str w3, [x1, #UART_DM_DMEN]
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/* Enable transmitter */
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mov w3, #UART_DM_CR_TX_ENABLE
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str w3, [x1, #UART_DM_CR]
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ret
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endfunc console_uartdm_core_init
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/* -----------------------------------------------------------
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* int console_uartdm_putc(int c, console_t *console)
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* Function to output a character over the console.
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* In : w0 - character to be printed
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* x1 - pointer to console_t struct
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* Out: w0 - printed character on success, < 0 on error.
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* Clobber list : x0, x1, x2
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* -----------------------------------------------------------
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*/
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func console_uartdm_putc
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ldr x1, [x1, #CONSOLE_T_BASE]
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b console_uartdm_core_putc
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endfunc console_uartdm_putc
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/* -----------------------------------------------------------
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* int console_uartdm_core_putc(int c, uintptr_t base_addr)
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* Function to output a character over the console.
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* In : w0 - character to be printed
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* x1 - base address
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* Out: w0 - printed character on success, < 0 on error.
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* Clobber list : x2
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* -----------------------------------------------------------
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*/
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func console_uartdm_core_putc
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1: /* Loop until TX FIFO has space */
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ldr w2, [x1, #UART_DM_SR]
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tbz w2, #UART_DM_SR_TXRDY_BIT, 1b
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/* Write character to FIFO */
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str w0, [x1, #UART_DM_TF]
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ret
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endfunc console_uartdm_core_putc
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/* -----------------------------------------------------------
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* void console_uartdm_flush(console_t *console)
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* Function to force a write of all buffered data
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* that has not been output.
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* In : x0 - pointer to console_t struct
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* Out: void
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* Clobber list : x0, x1, x2, x3, x4, x5
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* -----------------------------------------------------------
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*/
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func console_uartdm_flush
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ldr x1, [x0, #CONSOLE_T_BASE]
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b console_uartdm_core_flush
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endfunc console_uartdm_flush
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/* -----------------------------------------------------------
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* void console_uartdm_core_flush(unused, uintptr_t base_addr)
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* Function to force a write of all buffered data
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* that has not been output.
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* In : x0 - unused
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* x1 - base address
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* Out: void
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* Clobber list : x2
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* -----------------------------------------------------------
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*/
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func console_uartdm_core_flush
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1: /* Loop until TX FIFO is empty */
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ldr w2, [x1, #UART_DM_SR]
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tbz w2, #UART_DM_SR_TXEMT_BIT, 1b
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ret
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endfunc console_uartdm_core_flush
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+41
@@ -0,0 +1,41 @@
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/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MSM8916_MMAP_H
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#define MSM8916_MMAP_H
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#define PCNOC_BASE 0x00000000
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#define PCNOC_SIZE 0x8000000 /* 128 MiB */
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#define APCS_BASE 0x0b000000
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#define APCS_SIZE 0x800000 /* 8 MiB */
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#define MPM_BASE (PCNOC_BASE + 0x04a0000)
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#define MPM_PS_HOLD (MPM_BASE + 0xb000)
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#define TLMM_BASE (PCNOC_BASE + 0x1000000)
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#define TLMM_GPIO_CFG(n) (TLMM_BASE + ((n) * 0x1000))
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#define GCC_BASE (PCNOC_BASE + 0x1800000)
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#define APPS_SMMU_BASE (PCNOC_BASE + 0x1e00000)
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#define APPS_SMMU_QCOM (APPS_SMMU_BASE + 0xf0000)
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#define BLSP_UART1_BASE (PCNOC_BASE + 0x78af000)
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#define BLSP_UART2_BASE (PCNOC_BASE + 0x78b0000)
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#define APCS_QGIC2_BASE (APCS_BASE + 0x00000)
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#define APCS_QGIC2_GICD (APCS_QGIC2_BASE + 0x0000)
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#define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000)
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#define APCS_BANKED_ACS (APCS_BASE + 0x08000)
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#define APCS_BANKED_SAW2 (APCS_BASE + 0x09000)
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#define APCS_CFG (APCS_BASE + 0x10000)
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#define APCS_GLB (APCS_BASE + 0x11000)
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#define APCS_L2_SAW2 (APCS_BASE + 0x12000)
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#define APCS_QTMR (APCS_BASE + 0x20000)
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#define APCS_ALIAS_ACS(cpu) (APCS_BASE + 0x88000 + ((cpu) * 0x10000))
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#define APCS_ALIAS_SAW2(cpu) (APCS_BASE + 0x89000 + ((cpu) * 0x10000))
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#endif /* MSM8916_MMAP_H */
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@@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include <arm_macros.S>
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#include <msm8916_mmap.h>
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/* ---------------------------------------------
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* The below required platform porting macro
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* prints out relevant GIC registers whenever
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* an unhandled exception is taken in BL31.
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* Clobbers: x0 - x10, x16, x17, sp
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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mov_imm x16, APCS_QGIC2_GICD
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mov_imm x17, APCS_QGIC2_GICC
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arm_print_gic_regs
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.endm
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#endif /* PLAT_MACROS_S */
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+57
@@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <plat/common/common_def.h>
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/*
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* There is at least 1 MiB available for BL31. However, at the moment the
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* "msm8916_entry_point" variable in the data section is read through the
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* 64 KiB region of the "boot remapper" after reset. For simplicity, limit
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* the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and
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* the overall limit to 128 KiB. This could be increased if needed by placing
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* the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31.
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*/
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#define BL31_LIMIT (BL31_BASE + 0x20000) /* 128 KiB */
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#define BL31_PROGBITS_LIMIT (BL31_BASE + 0x10000) /* 64 KiB */
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#define CACHE_WRITEBACK_GRANULE U(64)
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#define PLATFORM_STACK_SIZE U(0x1000)
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/* CPU topology: single cluster with 4 cores */
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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/* Power management */
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_RET_STATE U(2)
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#define PLAT_MAX_OFF_STATE U(3)
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/* Translation tables */
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 4
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
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/* Timer frequency */
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#define PLAT_SYSCNT_FREQ 19200000
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/*
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* The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7
|
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* erroneously swapped for some reason. PIDR2 is actually at 0xFD8.
|
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* Override the address in <drivers/arm/gicv2.h> to avoid a failing assert().
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||||
*/
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#define GICD_PIDR2_GICV2 U(0xFD8)
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#endif /* PLATFORM_DEF_H */
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+12
@@ -0,0 +1,12 @@
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/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
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#ifndef UARTDM_CONSOLE_H
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#define UARTDM_CONSOLE_H
|
||||
|
||||
int console_uartdm_register(console_t *console, uintptr_t base_addr);
|
||||
|
||||
#endif /* UARTDM_CONSOLE_H */
|
||||
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/generic_delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_mmu_helpers.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include "msm8916_gicv2.h"
|
||||
#include <msm8916_mmap.h>
|
||||
#include <platform_def.h>
|
||||
#include <uartdm_console.h>
|
||||
|
||||
static const mmap_region_t msm8916_mmap[] = {
|
||||
MAP_REGION_FLAT(PCNOC_BASE, PCNOC_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
|
||||
MAP_REGION_FLAT(APCS_BASE, APCS_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
|
||||
{},
|
||||
};
|
||||
|
||||
static struct {
|
||||
entry_point_info_t bl32;
|
||||
entry_point_info_t bl33;
|
||||
} image_ep_info = {
|
||||
/* BL32 entry point */
|
||||
SET_STATIC_PARAM_HEAD(bl32, PARAM_EP, VERSION_1,
|
||||
entry_point_info_t, SECURE),
|
||||
.bl32.pc = BL32_BASE,
|
||||
|
||||
/* BL33 entry point */
|
||||
SET_STATIC_PARAM_HEAD(bl33, PARAM_EP, VERSION_1,
|
||||
entry_point_info_t, NON_SECURE),
|
||||
.bl33.pc = PRELOADED_BL33_BASE,
|
||||
.bl33.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
|
||||
};
|
||||
|
||||
static console_t console;
|
||||
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
return PLAT_SYSCNT_FREQ;
|
||||
}
|
||||
|
||||
#define CLK_ENABLE BIT_32(0)
|
||||
#define CLK_OFF BIT_32(31)
|
||||
|
||||
#define GPIO_BLSP_UART2_TX 4
|
||||
#define GPIO_BLSP_UART2_RX 5
|
||||
#define GPIO_CFG_FUNC_BLSP_UART2 (U(0x2) << 2)
|
||||
#define GPIO_CFG_DRV_STRENGTH_16MA (U(0x7) << 6)
|
||||
|
||||
#define GCC_BLSP1_AHB_CBCR (GCC_BASE + 0x01008)
|
||||
#define GCC_BLSP1_UART2_APPS_CBCR (GCC_BASE + 0x0302c)
|
||||
#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x45004)
|
||||
#define BLSP1_AHB_CLK_ENA BIT_32(10)
|
||||
|
||||
/*
|
||||
* The previous boot stage seems to disable most of the UART setup before exit
|
||||
* so it must be enabled here again before the UART console can be used.
|
||||
*/
|
||||
static void msm8916_enable_blsp_uart2(void)
|
||||
{
|
||||
/* Route GPIOs to BLSP UART2 */
|
||||
mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_TX),
|
||||
GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA);
|
||||
mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_RX),
|
||||
GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA);
|
||||
|
||||
/* Enable AHB clock */
|
||||
mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA);
|
||||
while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF)
|
||||
;
|
||||
|
||||
/* Enable BLSP UART2 clock */
|
||||
mmio_setbits_32(GCC_BLSP1_UART2_APPS_CBCR, CLK_ENABLE);
|
||||
while (mmio_read_32(GCC_BLSP1_UART2_APPS_CBCR) & CLK_OFF)
|
||||
;
|
||||
}
|
||||
|
||||
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||
u_register_t arg2, u_register_t arg3)
|
||||
{
|
||||
/* Initialize the debug console as early as possible */
|
||||
msm8916_enable_blsp_uart2();
|
||||
console_uartdm_register(&console, BLSP_UART2_BASE);
|
||||
}
|
||||
|
||||
void bl31_plat_arch_setup(void)
|
||||
{
|
||||
mmap_add_region(BL31_BASE, BL31_BASE, BL31_END - BL31_BASE,
|
||||
MT_RW_DATA | MT_SECURE);
|
||||
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
|
||||
BL_CODE_END - BL_CODE_BASE,
|
||||
MT_CODE | MT_SECURE);
|
||||
mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
|
||||
BL_RO_DATA_END - BL_RO_DATA_BASE,
|
||||
MT_RO_DATA | MT_SECURE);
|
||||
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
|
||||
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
|
||||
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
|
||||
|
||||
mmap_add(msm8916_mmap);
|
||||
init_xlat_tables();
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
|
||||
static void msm8916_configure_timer(void)
|
||||
{
|
||||
/* Set timer frequency */
|
||||
mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, plat_get_syscnt_freq2());
|
||||
|
||||
/* Make frame 0 available to non-secure world */
|
||||
mmio_write_32(APCS_QTMR + CNTNSAR, BIT_32(CNTNSAR_NS_SHIFT(0)));
|
||||
mmio_write_32(APCS_QTMR + CNTACR_BASE(0),
|
||||
BIT_32(CNTACR_RPCT_SHIFT) | BIT_32(CNTACR_RVCT_SHIFT) |
|
||||
BIT_32(CNTACR_RFRQ_SHIFT) | BIT_32(CNTACR_RVOFF_SHIFT) |
|
||||
BIT_32(CNTACR_RWVT_SHIFT) | BIT_32(CNTACR_RWPT_SHIFT));
|
||||
}
|
||||
|
||||
/*
|
||||
* The APCS register regions always start with a SECURE register that should
|
||||
* be cleared to 0 to only allow secure access. Since BL31 handles most of
|
||||
* the CPU power management, most of them can be cleared to secure access only.
|
||||
*/
|
||||
#define APCS_GLB_SECURE_STS_NS BIT_32(0)
|
||||
#define APCS_GLB_SECURE_PWR_NS BIT_32(1)
|
||||
#define APCS_BOOT_START_ADDR_SEC (APCS_CFG + 0x04)
|
||||
#define REMAP_EN BIT_32(0)
|
||||
#define APCS_AA64NAA32_REG (APCS_CFG + 0x0c)
|
||||
|
||||
static void msm8916_configure_cpu_pm(void)
|
||||
{
|
||||
unsigned int cpu;
|
||||
|
||||
/* Disallow non-secure access to boot remapper / TCM registers */
|
||||
mmio_write_32(APCS_CFG, 0);
|
||||
|
||||
/*
|
||||
* Disallow non-secure access to power management registers.
|
||||
* However, allow STS and PWR since those also seem to control access
|
||||
* to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these
|
||||
* bits are not set, CPU frequency control fails in the non-secure world.
|
||||
*/
|
||||
mmio_write_32(APCS_GLB, APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS);
|
||||
|
||||
/* Disallow non-secure access to L2 SAW2 */
|
||||
mmio_write_32(APCS_L2_SAW2, 0);
|
||||
|
||||
/* Disallow non-secure access to CPU ACS and SAW2 */
|
||||
for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) {
|
||||
mmio_write_32(APCS_ALIAS_ACS(cpu), 0);
|
||||
mmio_write_32(APCS_ALIAS_SAW2(cpu), 0);
|
||||
}
|
||||
|
||||
/* Make sure all further warm boots end up in BL31 and aarch64 state */
|
||||
CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned);
|
||||
mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN);
|
||||
mmio_write_32(APCS_AA64NAA32_REG, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU,
|
||||
* which allows routing context bank interrupts to one of 3 interrupt numbers
|
||||
* ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number
|
||||
* by default to avoid special setup on the non-secure side.
|
||||
*/
|
||||
#define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038)
|
||||
#define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c)
|
||||
#define SMMU_CFG_CLK_ENA BIT_32(12)
|
||||
#define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000)
|
||||
#define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff)
|
||||
|
||||
static void msm8916_configure_smmu(void)
|
||||
{
|
||||
/* Enable SMMU configuration clock to enable register access */
|
||||
mmio_setbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA);
|
||||
while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF)
|
||||
;
|
||||
|
||||
/* Route all context bank interrupts to non-secure interrupt */
|
||||
mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL);
|
||||
|
||||
/* Disable configuration clock again */
|
||||
mmio_clrbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA);
|
||||
}
|
||||
|
||||
void bl31_platform_setup(void)
|
||||
{
|
||||
INFO("BL31: Platform setup start\n");
|
||||
generic_delay_timer_init();
|
||||
msm8916_configure_timer();
|
||||
msm8916_gicv2_init();
|
||||
msm8916_configure_cpu_pm();
|
||||
msm8916_configure_smmu();
|
||||
INFO("BL31: Platform setup done\n");
|
||||
}
|
||||
|
||||
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
|
||||
{
|
||||
switch (type) {
|
||||
case SECURE:
|
||||
return &image_ep_info.bl32;
|
||||
case NON_SECURE:
|
||||
return &image_ep_info.bl33;
|
||||
default:
|
||||
assert(sec_state_is_valid(type));
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include <msm8916_mmap.h>
|
||||
#include "msm8916_pm.h"
|
||||
|
||||
#define CPU_PWR_CTL 0x4
|
||||
#define APC_PWR_GATE_CTL 0x14
|
||||
|
||||
#define CPU_PWR_CTL_CLAMP BIT_32(0)
|
||||
#define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1)
|
||||
#define CPU_PWR_CTL_L1_RST_DIS BIT_32(2)
|
||||
#define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3)
|
||||
#define CPU_PWR_CTL_CORE_RST BIT_32(4)
|
||||
#define CPU_PWR_CTL_COREPOR_RST BIT_32(5)
|
||||
#define CPU_PWR_CTL_GATE_CLK BIT_32(6)
|
||||
#define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7)
|
||||
|
||||
#define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
|
||||
#define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24)
|
||||
|
||||
/* Boot a secondary CPU core for the first time. */
|
||||
void msm8916_cpu_boot(unsigned int core)
|
||||
{
|
||||
uintptr_t acs = APCS_ALIAS_ACS(core);
|
||||
uint32_t pwr_ctl;
|
||||
|
||||
pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP |
|
||||
CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST;
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
|
||||
mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN |
|
||||
APC_PWR_GATE_CTL_GHDS_CNT(16));
|
||||
dsb();
|
||||
udelay(2);
|
||||
|
||||
pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP;
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
|
||||
pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS;
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
udelay(2);
|
||||
|
||||
pwr_ctl &= ~CPU_PWR_CTL_CLAMP;
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
udelay(2);
|
||||
|
||||
pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST);
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
|
||||
pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP;
|
||||
mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
|
||||
dsb();
|
||||
}
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include "msm8916_gicv2.h"
|
||||
#include <msm8916_mmap.h>
|
||||
|
||||
#define IRQ_SEC_SGI_0 8
|
||||
#define IRQ_SEC_SGI_1 9
|
||||
#define IRQ_SEC_SGI_2 10
|
||||
#define IRQ_SEC_SGI_3 11
|
||||
#define IRQ_SEC_SGI_4 12
|
||||
#define IRQ_SEC_SGI_5 13
|
||||
#define IRQ_SEC_SGI_6 14
|
||||
#define IRQ_SEC_SGI_7 15
|
||||
|
||||
#define IRQ_SEC_PHY_TIMER (16 + 2) /* PPI #2 */
|
||||
|
||||
static const interrupt_prop_t msm8916_interrupt_props[] = {
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
};
|
||||
|
||||
static const gicv2_driver_data_t msm8916_gic_data = {
|
||||
.gicd_base = APCS_QGIC2_GICD,
|
||||
.gicc_base = APCS_QGIC2_GICC,
|
||||
.interrupt_props = msm8916_interrupt_props,
|
||||
.interrupt_props_num = ARRAY_SIZE(msm8916_interrupt_props),
|
||||
};
|
||||
|
||||
void msm8916_gicv2_init(void)
|
||||
{
|
||||
gicv2_driver_init(&msm8916_gic_data);
|
||||
gicv2_distif_init();
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MSM8916_GICV2_H
|
||||
#define MSM8916_GICV2_H
|
||||
|
||||
void msm8916_gicv2_init(void);
|
||||
|
||||
#endif /* MSM8916_GICV2_H */
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/psci/psci.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <msm8916_mmap.h>
|
||||
#include "msm8916_pm.h"
|
||||
|
||||
static int msm8916_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
VERBOSE("PSCI: Booting CPU %d\n", core);
|
||||
msm8916_cpu_boot(core);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void msm8916_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
|
||||
static void __dead2 msm8916_system_reset(void)
|
||||
{
|
||||
mmio_write_32(MPM_PS_HOLD, 0);
|
||||
mdelay(1000);
|
||||
|
||||
ERROR("PSCI: System reset failed\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
static const plat_psci_ops_t msm8916_psci_ops = {
|
||||
.pwr_domain_on = msm8916_pwr_domain_on,
|
||||
.pwr_domain_on_finish = msm8916_pwr_domain_on_finish,
|
||||
.system_off = msm8916_system_reset,
|
||||
.system_reset = msm8916_system_reset,
|
||||
};
|
||||
|
||||
/* Defined and used in msm8916_helpers.S */
|
||||
extern uintptr_t msm8916_entry_point;
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
msm8916_entry_point = sec_entrypoint;
|
||||
*psci_ops = &msm8916_psci_ops;
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MSM8916_PM_H
|
||||
#define MSM8916_PM_H
|
||||
|
||||
void msm8916_cpu_boot(unsigned int core);
|
||||
|
||||
#endif /* MSM8916_PM_H */
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = {
|
||||
PLATFORM_SYSTEM_COUNT,
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER,
|
||||
};
|
||||
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
if (MPIDR_AFFLVL3_VAL(mpidr) > 0 ||
|
||||
MPIDR_AFFLVL2_VAL(mpidr) > 0 ||
|
||||
MPIDR_AFFLVL1_VAL(mpidr) > 0 ||
|
||||
core >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return core;
|
||||
}
|
||||
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return plat_power_domain_tree_desc;
|
||||
}
|
||||
@@ -0,0 +1,62 @@
|
||||
#
|
||||
# Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include drivers/arm/gic/v2/gicv2.mk
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS}
|
||||
|
||||
PLAT_INCLUDES := -Iinclude/plat/arm/common/${ARCH} \
|
||||
-Iplat/qti/msm8916/include
|
||||
|
||||
BL31_SOURCES += ${GICV2_SOURCES} \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
lib/cpus/${ARCH}/cortex_a53.S \
|
||||
plat/common/plat_gicv2.c \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/qti/msm8916/msm8916_bl31_setup.c \
|
||||
plat/qti/msm8916/msm8916_cpu_boot.c \
|
||||
plat/qti/msm8916/msm8916_gicv2.c \
|
||||
plat/qti/msm8916/msm8916_pm.c \
|
||||
plat/qti/msm8916/msm8916_topology.c \
|
||||
plat/qti/msm8916/${ARCH}/msm8916_helpers.S \
|
||||
plat/qti/msm8916/${ARCH}/uartdm_console.S
|
||||
|
||||
# Only BL31 is supported at the moment and is entered on a single CPU
|
||||
RESET_TO_BL31 := 1
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
|
||||
# Build config flags
|
||||
# ------------------
|
||||
BL31_BASE ?= 0x86500000
|
||||
BL32_BASE ?= 0x86000000
|
||||
PRELOADED_BL33_BASE ?= 0x8f600000
|
||||
|
||||
# Have different sections for code and rodata
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# Single cluster
|
||||
WARMBOOT_ENABLE_DCACHE_EARLY := 1
|
||||
|
||||
# Disable features unsupported in ARMv8.0
|
||||
ENABLE_AMU := 0
|
||||
ENABLE_SPE_FOR_LOWER_ELS := 0
|
||||
ENABLE_SVE_FOR_NS := 0
|
||||
|
||||
# MSM8916 uses ARM Cortex-A53 r0p0 so likely all the errata apply
|
||||
ERRATA_A53_819472 := 1
|
||||
ERRATA_A53_824069 := 1
|
||||
ERRATA_A53_826319 := 1
|
||||
ERRATA_A53_827319 := 1
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_836870 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 0 # Workaround works only for >= r0p3
|
||||
ERRATA_A53_1530924 := 1
|
||||
|
||||
$(eval $(call add_define,BL31_BASE))
|
||||
$(eval $(call add_define,BL32_BASE))
|
||||
Reference in New Issue
Block a user