GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTISECLIB_CB_INTERFACE_H
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#define QTISECLIB_CB_INTERFACE_H
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#include <stdarg.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <qtiseclib_defs.h>
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/* Standard Library API's */
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void *qtiseclib_cb_memcpy(void *dst, const void *src, size_t len);
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int qtiseclib_cb_strcmp(const char *s1, const char *s2);
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void *qtiseclib_cb_memset(void *s, int c, size_t n);
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void *qtiseclib_cb_memmove(void *dest, const void *src, size_t n);
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#define QTISECLIB_CB_ERROR(...) qtiseclib_cb_log(QTISECLIB_LOG_LEVEL_ERROR, __VA_ARGS__)
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#define QTISECLIB_CB_NOTICE(...) qtiseclib_cb_log(QTISECLIB_LOG_LEVEL_NOTICE, __VA_ARGS__)
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#define QTISECLIB_CB_WARN(...) qtiseclib_cb_log(QTISECLIB_LOG_LEVEL_WARNING, __VA_ARGS__)
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#define QTISECLIB_CB_INFO(...) qtiseclib_cb_log(QTISECLIB_LOG_LEVEL_INFO, __VA_ARGS__)
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void qtiseclib_cb_log(unsigned int loglvl, const char *fmt, ...);
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void qtiseclib_cb_spin_lock(qtiseclib_cb_spinlock_t *lock);
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void qtiseclib_cb_spin_unlock(qtiseclib_cb_spinlock_t *lock);
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unsigned int qtiseclib_cb_plat_my_core_pos(void);
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int qtiseclib_cb_plat_core_pos_by_mpidr(u_register_t mpidr);
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unsigned int qtiseclib_cb_plat_my_cluster_pos(void);
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/* GIC platform wrappers */
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void qtiseclib_cb_gic_pcpu_init(void);
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void qtiseclib_cb_ic_raise_sgi(int sgi_num, u_register_t target);
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void qtiseclib_cb_set_spi_routing(unsigned int id, unsigned int irm,
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u_register_t target);
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/* Crash reporting api's wrappers */
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void qtiseclib_cb_switch_console_to_crash_state(void);
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void qtiseclib_cb_udelay(uint32_t usec);
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void qtiseclib_cb_console_flush(void);
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#if QTI_SDI_BUILD
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int qtiseclib_cb_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
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int qtiseclib_cb_mmap_add_dynamic_region(unsigned long long base_pa,
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size_t size,
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qtiseclib_mmap_attr_t attr);
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void qtiseclib_cb_flush_dcache_all(void);
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void qtiseclib_cb_get_ns_ctx(qtiseclib_dbg_a64_ctxt_regs_type *ns_ctx);
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#endif
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#endif /* QTISECLIB_CB_INTERFACE_H */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTISECLIB_DEFS_H
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#define QTISECLIB_DEFS_H
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#include <stdint.h>
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#ifndef u_register_t
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typedef uintptr_t u_register_t;
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#endif
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/*
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* Different Log Level supported in qtiseclib.
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* TODO: Currently no filtering done on QTISECLIB logs.
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*/
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#define QTISECLIB_LOG_LEVEL_NONE 0
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#define QTISECLIB_LOG_LEVEL_ERROR 10
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#define QTISECLIB_LOG_LEVEL_NOTICE 20
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#define QTISECLIB_LOG_LEVEL_WARNING 30
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#define QTISECLIB_LOG_LEVEL_INFO 40
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#define QTISECLIB_LOG_LEVEL_VERBOSE 50
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#define QTI_GICV3_IRM_PE 0
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#define QTI_GICV3_IRM_ANY 1
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/* Common interrupt number/ID defs. */
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#define QTISECLIB_INT_ID_RESET_SGI (0xf)
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#define QTISECLIB_INT_ID_CPU_WAKEUP_SGI (0x8)
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#define QTISECLIB_INT_INVALID_INT_NUM (0xFFFFFFFFU)
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typedef struct qtiseclib_cb_spinlock {
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volatile uint32_t lock;
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} qtiseclib_cb_spinlock_t;
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#if QTI_SDI_BUILD
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/* External CPU Dump Structure - 64 bit EL */
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typedef struct {
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uint64_t x0;
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uint64_t x1;
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uint64_t x2;
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uint64_t x3;
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uint64_t x4;
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uint64_t x5;
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uint64_t x6;
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uint64_t x7;
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uint64_t x8;
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uint64_t x9;
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uint64_t x10;
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uint64_t x11;
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uint64_t x12;
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uint64_t x13;
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uint64_t x14;
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uint64_t x15;
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uint64_t x16;
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uint64_t x17;
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uint64_t x18;
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uint64_t x19;
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uint64_t x20;
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uint64_t x21;
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uint64_t x22;
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uint64_t x23;
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uint64_t x24;
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uint64_t x25;
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uint64_t x26;
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uint64_t x27;
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uint64_t x28;
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uint64_t x29;
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uint64_t x30;
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uint64_t pc;
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uint64_t currentEL;
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uint64_t sp_el3;
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uint64_t elr_el3;
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uint64_t spsr_el3;
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uint64_t sp_el2;
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uint64_t elr_el2;
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uint64_t spsr_el2;
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uint64_t sp_el1;
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uint64_t elr_el1;
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uint64_t spsr_el1;
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uint64_t sp_el0;
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uint64_t __reserved1;
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uint64_t __reserved2;
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uint64_t __reserved3;
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uint64_t __reserved4;
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uint64_t __reserved5;
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uint64_t __reserved6;
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uint64_t __reserved7;
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uint64_t __reserved8;
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} qtiseclib_dbg_a64_ctxt_regs_type;
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typedef enum qtiseclib_mmap_attr_s {
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QTISECLIB_MAP_NS_RO_XN_DATA = 1,
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QTISECLIB_MAP_RW_XN_NC_DATA = 2,
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QTISECLIB_MAP_RW_XN_DATA = 3,
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} qtiseclib_mmap_attr_t;
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#endif /* QTI_SDI_BUILD */
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#endif /* QTISECLIB_DEFS_H */
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+99
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTISECLIB_INTERFACE_H
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#define QTISECLIB_INTERFACE_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <qtiseclib_defs.h>
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typedef struct memprot_ipa_info_s {
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uint64_t mem_addr;
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uint64_t mem_size;
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} memprot_info_t;
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typedef struct memprot_dst_vm_perm_info_s {
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uint32_t dst_vm;
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uint32_t dst_vm_perm;
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uint64_t ctx;
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uint32_t ctx_size;
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} memprot_dst_vm_perm_info_t;
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/*
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* QTISECLIB Published API's.
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*/
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/*
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* Assembly API's
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*/
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/*
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* CPUSS common reset handler for all CPU wake up (both cold & warm boot).
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* Executes on all core. This API assume serialization across CPU
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* already taken care before invoking.
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*
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* Clobbers: x0 - x17, x30
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*/
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void qtiseclib_cpuss_reset_asm(uint32_t bl31_cold_boot_state);
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/*
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* Execute CPU (Kryo4 gold) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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*
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* Clobbers: x0 - x16
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*/
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void qtiseclib_kryo4_gold_reset_asm(void);
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/*
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* Execute CPU (Kryo46 gold) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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*
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* Clobbers: x0 - x16
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*/
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void qtiseclib_kryo6_gold_reset_asm(void);
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/*
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* Execute CPU (Kryo4 silver) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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*
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* Clobbers: x0 - x16
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*/
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void qtiseclib_kryo4_silver_reset_asm(void);
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/*
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* Execute CPU (Kryo6 silver) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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*
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* Clobbers: x0 - x16
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*/
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void qtiseclib_kryo6_silver_reset_asm(void);
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/*
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* C Api's
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*/
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void qtiseclib_bl31_platform_setup(void);
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void qtiseclib_invoke_isr(uint32_t irq, void *handle);
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void qtiseclib_panic(void);
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int qtiseclib_mem_assign(const memprot_info_t *mem_info,
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uint32_t mem_info_list_cnt,
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const uint32_t *source_vm_list,
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uint32_t src_vm_list_cnt,
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const memprot_dst_vm_perm_info_t *dest_vm_list,
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uint32_t dst_vm_list_cnt);
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int qtiseclib_psci_init(uintptr_t warmboot_entry);
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int qtiseclib_psci_node_power_on(u_register_t mpidr);
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void qtiseclib_psci_node_on_finish(const uint8_t *states);
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void qtiseclib_psci_cpu_standby(uint8_t pwr_state);
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void qtiseclib_psci_node_power_off(const uint8_t *states);
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void qtiseclib_psci_node_suspend(const uint8_t *states);
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void qtiseclib_psci_node_suspend_finish(const uint8_t *states);
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void qtiseclib_disable_cluster_coherency(uint8_t state);
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#endif /* QTISECLIB_INTERFACE_H */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTISECLIB_DEFS_PLAT_H
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#define QTISECLIB_DEFS_PLAT_H
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#define QTISECLIB_PLAT_CLUSTER_COUNT 1
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#define QTISECLIB_PLAT_CORE_COUNT 8
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#define BL31_BASE 0x80b00000
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#define BL31_SIZE 0x00100000
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/* Chipset specific secure interrupt number/ID defs. */
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#define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204)
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#define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC (0xE6)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC (0xE7)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC (0xE8)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC (0xE9)
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#define QTISECLIB_INT_ID_XPU_SEC (0xE3)
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#define QTISECLIB_INT_ID_XPU_NON_SEC (0xE4)
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#define QTISECLIB_INT_ID_A2_NOC_ERROR (0x194)
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#define QTISECLIB_INT_ID_CONFIG_NOC_ERROR (0xE2)
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#define QTISECLIB_INT_ID_DC_NOC_ERROR (0x122)
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#define QTISECLIB_INT_ID_MEM_NOC_ERROR (0x6C)
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#define QTISECLIB_INT_ID_SYSTEM_NOC_ERROR (0xC6)
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#define QTISECLIB_INT_ID_MMSS_NOC_ERROR (0xBA)
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#endif /* QTISECLIB_DEFS_PLAT_H */
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __QTISECLIB_DEFS_PLAT_H__
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#define __QTISECLIB_DEFS_PLAT_H__
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#define QTISECLIB_PLAT_CLUSTER_COUNT 1
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#define QTISECLIB_PLAT_CORE_COUNT 8
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#define BL31_BASE 0xC0000000
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#define BL31_SIZE 0x00100000
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/*----------------------------------------------------------------------------*/
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/* AOP CMD DB address space for mapping */
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/*----------------------------------------------------------------------------*/
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#define QTI_AOP_CMD_DB_BASE 0x80860000
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#define QTI_AOP_CMD_DB_SIZE 0x00020000
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/* Chipset specific secure interrupt number/ID defs. */
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#define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204)
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#define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC (0xE6)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC (0xE7)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC (0xE8)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC (0xE9)
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#define QTISECLIB_INT_ID_XPU_SEC (0xE3)
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#define QTISECLIB_INT_ID_XPU_NON_SEC (0xE4)
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//NOC INterrupt
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#define QTISECLIB_INT_ID_A1_NOC_ERROR (0xC9)
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#define QTISECLIB_INT_ID_A2_NOC_ERROR (0xEA)
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#define QTISECLIB_INT_ID_CONFIG_NOC_ERROR (0xE2)
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#define QTISECLIB_INT_ID_DC_NOC_ERROR (0x122)
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#define QTISECLIB_INT_ID_MEM_NOC_ERROR (0x6C)
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#define QTISECLIB_INT_ID_SYSTEM_NOC_ERROR (0xC8)
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#define QTISECLIB_INT_ID_MMSS_NOC_ERROR (0xBA)
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#define QTISECLIB_INT_ID_LPASS_AGNOC_ERROR (0x143)
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#define QTISECLIB_INT_ID_NSP_NOC_ERROR (0x1CE)
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#endif /* __QTISECLIB_DEFS_PLAT_H__ */
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