GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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/* Enable the dynamic translation tables library. */
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#define PLAT_XLAT_TABLES_DYNAMIC 1
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#include <common_def.h>
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#include <qti_board_def.h>
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#include <qtiseclib_defs_plat.h>
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/*
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* MPIDR_PRIMARY_CPU
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* You just need to have the correct core_affinity_val i.e. [7:0]
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* and cluster_affinity_val i.e. [15:8]
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* the other bits will be ignored
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*/
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/*----------------------------------------------------------------------------*/
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#define MPIDR_PRIMARY_CPU 0x0000
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/*----------------------------------------------------------------------------*/
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#define QTI_PWR_LVL0 MPIDR_AFFLVL0
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#define QTI_PWR_LVL1 MPIDR_AFFLVL1
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#define QTI_PWR_LVL2 MPIDR_AFFLVL2
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#define QTI_PWR_LVL3 MPIDR_AFFLVL3
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/*
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* Macros for local power states encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define QTI_LOCAL_STATE_RUN 0
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/*
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* Local power state for clock-gating. Valid only for CPU and not cluster power
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* domains
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*/
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#define QTI_LOCAL_STATE_STB 1
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/*
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* Local power state for retention. Valid for CPU and cluster power
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* domains
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*/
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#define QTI_LOCAL_STATE_RET 2
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/*
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* Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC
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* power domains
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*/
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#define QTI_LOCAL_STATE_OFF 3
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/*
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* Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC
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* power domains
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*/
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#define QTI_LOCAL_STATE_DEEPOFF 4
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF
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/******************************************************************************
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* Required platform porting definitions common to all ARM standard platforms
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*****************************************************************************/
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/*
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* Platform specific page table and MMU setup constants.
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*/
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#define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36)
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
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/*
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* One cache line needed for bakery locks on ARM platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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/*----------------------------------------------------------------------------*/
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/* PSCI power domain topology definitions */
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/*----------------------------------------------------------------------------*/
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/* One domain each to represent RSC and PDC level */
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#define PLAT_PDC_COUNT 1
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#define PLAT_RSC_COUNT 1
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/* There is one top-level FCM cluster */
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#define PLAT_CLUSTER_COUNT 1
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/* No. of cores in the FCM cluster */
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#define PLAT_CLUSTER0_CORE_COUNT 8
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#define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT)
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#define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\
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PLAT_RSC_COUNT +\
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PLAT_CLUSTER_COUNT +\
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL 3
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/*****************************************************************************/
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/* Memory mapped Generic timer interfaces */
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/*****************************************************************************/
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/*----------------------------------------------------------------------------*/
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/* GIC-600 constants */
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/*----------------------------------------------------------------------------*/
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#define BASE_GICD_BASE 0x17A00000
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#define BASE_GICR_BASE 0x17A60000
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#define BASE_GICC_BASE 0x0
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#define BASE_GICH_BASE 0x0
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#define BASE_GICV_BASE 0x0
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#define QTI_GICD_BASE BASE_GICD_BASE
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#define QTI_GICR_BASE BASE_GICR_BASE
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#define QTI_GICC_BASE BASE_GICC_BASE
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* UART related constants. */
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/*----------------------------------------------------------------------------*/
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/* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */
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#define GENI4_CFG 0x0
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#define GENI4_IMAGE_REGS 0x100
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#define GENI4_DATA 0x600
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/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */
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#define GENI_STATUS_REG (GENI4_CFG + 0x00000040)
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#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1)
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#define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170)
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/* MASTER/TX ENGINE REGISTERS */
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#define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000)
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/* FIFO, STATUS REGISTERS AND MASKS */
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#define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100)
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#define GENI_M_CMD_TX (0x08000000)
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/*----------------------------------------------------------------------------*/
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/* Device address space for mapping. Excluding starting 4K */
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/*----------------------------------------------------------------------------*/
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#define QTI_DEVICE_BASE 0x1000
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#define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at DDR as per memory map. BL31_BASE is calculated using the
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* current BL31 debug size plus a little space for growth.
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*/
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/*----------------------------------------------------------------------------*/
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/* AOSS registers */
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/*----------------------------------------------------------------------------*/
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#define QTI_PS_HOLD_REG 0x0C264000
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/*----------------------------------------------------------------------------*/
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/* AOP CMD DB address space for mapping */
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/*----------------------------------------------------------------------------*/
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#define QTI_AOP_CMD_DB_BASE 0x80820000
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#define QTI_AOP_CMD_DB_SIZE 0x00020000
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/*----------------------------------------------------------------------------*/
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/* SOC hw version register */
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/*----------------------------------------------------------------------------*/
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#define QTI_SOC_VERSION_MASK U(0xFFFF)
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#define QTI_SOC_REVISION_REG 0x1FC8000
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#define QTI_SOC_REVISION_MASK U(0xFFFF)
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/*----------------------------------------------------------------------------*/
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/* LC PON register offsets */
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/*----------------------------------------------------------------------------*/
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#define PON_PS_HOLD_RESET_CTL 0x85a
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#define PON_PS_HOLD_RESET_CTL2 0x85b
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/*----------------------------------------------------------------------------*/
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#endif /* PLATFORM_DEF_H */
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_MAP_CHIPINFO_H
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#define QTI_MAP_CHIPINFO_H
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#include <stdint.h>
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#include <qti_plat.h>
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#define QTI_JTAG_ID_REG 0x786130
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#define QTI_SOC_VERSION_MASK U(0xFFFF)
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#define QTI_SOC_REVISION_REG 0x1FC8000
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#define QTI_SOC_REVISION_MASK U(0xFFFF)
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#define QTI_JTAG_ID_SHIFT 12
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#define QTI_JTAG_ID_SC7180 U(0x012C)
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#define QTI_JTAG_ID_SC7180P U(0x0195)
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#define QTI_CHIPINFO_ID_SC7180 U(0x01A9)
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#define QTI_CHIPINFO_ID_SC7180P U(0x01EF)
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#define QTI_DEFAULT_CHIPINFO_ID U(0xFFFF)
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static const chip_id_info_t g_map_jtag_chipinfo_id[] = {
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{QTI_JTAG_ID_SC7180, QTI_CHIPINFO_ID_SC7180},
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{QTI_JTAG_ID_SC7180P, QTI_CHIPINFO_ID_SC7180P},
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};
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#endif /* QTI_MAP_CHIPINFO_H */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_RNG_IO_H
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#define QTI_RNG_IO_H
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#define SEC_PRNG_STATUS 0x00791004
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#define SEC_PRNG_STATUS_DATA_AVAIL_BMSK 0x1
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#define SEC_PRNG_DATA_OUT 0x00791000
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#endif /* QTI_RNG_IO_H */
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+30
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QTI_SECURE_IO_CFG_H
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#define QTI_SECURE_IO_CFG_H
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#include <stdint.h>
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/*
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* List of peripheral/IO memory areas that are protected from
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* non-secure world but not required to be secure.
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*/
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#define APPS_SMMU_TBU_PWR_STATUS 0x15002204
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#define APPS_SMMU_CUSTOM_CFG 0x15002300
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#define APPS_SMMU_STATS_SYNC_INV_TBU_ACK 0x150025DC
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#define APPS_SMMU_SAFE_SEC_CFG 0x15002648
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#define APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x15002670
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static const uintptr_t qti_secure_io_allowed_regs[] = {
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APPS_SMMU_TBU_PWR_STATUS,
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APPS_SMMU_CUSTOM_CFG,
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APPS_SMMU_STATS_SYNC_INV_TBU_ACK,
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APPS_SMMU_SAFE_SEC_CFG,
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APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
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};
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#endif /* QTI_SECURE_IO_CFG_H */
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@@ -0,0 +1,128 @@
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Make for SC7180 QTI platform.
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QTI_PLAT_PATH := plat/qti
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CHIPSET := ${PLAT}
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# Turn On Separate code & data.
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SEPARATE_CODE_AND_RODATA := 1
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USE_COHERENT_MEM := 0
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WARMBOOT_ENABLE_DCACHE_EARLY := 1
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HW_ASSISTED_COHERENCY := 1
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# Disable the PSCI platform compatibility layer
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ENABLE_PLAT_COMPAT := 0
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#Enable errata for cortex_a55 and cortex_a76
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ERRATA_A55_1530923 := 1
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ERRATA_A76_1165522 := 1
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# Enable PSCI v1.0 extended state ID format
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PSCI_EXTENDED_STATE_ID := 1
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ARM_RECOM_STATE_ID_ENC := 1
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COLD_BOOT_SINGLE_CPU := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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RESET_TO_BL31 := 0
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MULTI_CONSOLE_API := 1
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QTI_SDI_BUILD := 0
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$(eval $(call assert_boolean,QTI_SDI_BUILD))
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$(eval $(call add_define,QTI_SDI_BUILD))
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#disable CTX_INCLUDE_AARCH32_REGS to support sc7180 gold cores
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override CTX_INCLUDE_AARCH32_REGS := 0
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WORKAROUND_CVE_2017_5715 := 0
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DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
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# Enable stack protector.
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ENABLE_STACK_PROTECTOR := strong
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QTI_EXTERNAL_INCLUDES := -I${QTI_PLAT_PATH}/${CHIPSET}/inc \
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-I${QTI_PLAT_PATH}/common/inc \
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-I${QTI_PLAT_PATH}/common/inc/$(ARCH) \
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-I${QTI_PLAT_PATH}/qtiseclib/inc \
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-I${QTI_PLAT_PATH}/qtiseclib/inc/${CHIPSET} \
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QTI_BL31_SOURCES := $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_helpers.S \
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$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_silver.S \
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$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_gold.S \
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$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_uart_console.S \
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$(QTI_PLAT_PATH)/common/src/pm_ps_hold.c \
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$(QTI_PLAT_PATH)/common/src/qti_stack_protector.c \
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$(QTI_PLAT_PATH)/common/src/qti_common.c \
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$(QTI_PLAT_PATH)/common/src/qti_bl31_setup.c \
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$(QTI_PLAT_PATH)/common/src/qti_gic_v3.c \
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$(QTI_PLAT_PATH)/common/src/qti_interrupt_svc.c \
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$(QTI_PLAT_PATH)/common/src/qti_syscall.c \
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$(QTI_PLAT_PATH)/common/src/qti_topology.c \
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$(QTI_PLAT_PATH)/common/src/qti_pm.c \
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$(QTI_PLAT_PATH)/common/src/qti_rng.c \
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$(QTI_PLAT_PATH)/common/src/spmi_arb.c \
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$(QTI_PLAT_PATH)/qtiseclib/src/qtiseclib_cb_interface.c \
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PLAT_INCLUDES := -Iinclude/plat/common/ \
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PLAT_INCLUDES += ${QTI_EXTERNAL_INCLUDES}
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
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plat/common/aarch64/crash_console_helpers.S \
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common/desc_image_load.c \
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lib/bl_aux_params/bl_aux_params.c \
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include lib/coreboot/coreboot.mk
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#PSCI Sources.
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PSCI_SOURCES := plat/common/plat_psci_common.c \
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# GIC-600 configuration
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GICV3_SUPPORT_GIC600 := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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#Timer sources
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TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \
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drivers/delay_timer/delay_timer.c \
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#GIC sources.
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GIC_SOURCES := plat/common/plat_gicv3.c \
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${GICV3_SOURCES} \
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CPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \
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lib/cpus/aarch64/cortex_a55.S \
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BL31_SOURCES += ${QTI_BL31_SOURCES} \
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${PSCI_SOURCES} \
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${GIC_SOURCES} \
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${TIMER_SOURCES} \
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${CPU_SOURCES} \
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LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}
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# Override this on the command line to point to the qtiseclib library which
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# will be available in coreboot.org
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QTISECLIB_PATH ?=
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ifeq ($(QTISECLIB_PATH),)
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# if No lib then use stub implementation for qtiseclib interface
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$(warning QTISECLIB_PATH is not provided while building, using stub implementation. \
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Please refer docs/plat/qti.rst for more details \
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THIS FIRMWARE WILL NOT BOOT!)
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BL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
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else
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# use library provided by QTISECLIB_PATH
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LDFLAGS += -L $(dir $(QTISECLIB_PATH))
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LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH)))
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endif
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