GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
This commit is contained in:
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/runtime_svc.h>
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#include <cortex_a57.h>
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#include <platform_def.h>
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#include "rcar_def.h"
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.globl plat_get_my_entrypoint
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.extern plat_set_my_stack
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.globl platform_mem_init
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_invalidate_icache
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.globl plat_report_exception
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.globl plat_secondary_reset
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.globl plat_reset_handler
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.globl plat_my_core_pos
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.extern rcar_log_init
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.extern console_rcar_init
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.extern console_rcar_putc
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.extern console_rcar_flush
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#if IMAGE_BL2
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#define INT_ID_MASK (0x3ff)
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.extern bl2_interrupt_error_type
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.extern bl2_interrupt_error_id
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.globl bl2_enter_bl31
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.extern gicv2_acknowledge_interrupt
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.extern rcar_swdt_exec
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#endif
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/* -----------------------------------------------------
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* void platform_get_core_pos (mpidr)
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* -----------------------------------------------------
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*/
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func platform_get_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc platform_get_core_pos
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/* -----------------------------------------------------
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* void platform_my_core_pos
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b platform_get_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* void platform_get_my_entrypoint (unsigned int mpid);
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*
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* Main job of this routine is to distinguish between
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* a cold and warm boot.
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* On a cold boot the secondaries first wait for the
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* platform to be initialized after which they are
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* hotplugged in. The primary proceeds to perform the
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* platform initialization.
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* On a warm boot, each cpu jumps to the address in its
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* mailbox.
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*
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* TODO: Not a good idea to save lr in a temp reg
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* -----------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mrs x0, mpidr_el1
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mov x9, x30 /* lr */
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#if defined(IMAGE_BL2)
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/* always cold boot on bl2 */
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mov x0, #0
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ret x9
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#else
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ldr x1, =BOOT_KIND_BASE
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ldr x21, [x1]
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/* Check the reset info */
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and x1, x21, #0x000c
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cmp x1, #0x0008
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beq el3_panic
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cmp x1, #0x000c
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beq el3_panic
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/* Check the boot kind */
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and x1, x21, #0x0003
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cmp x1, #0x0002
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beq el3_panic
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cmp x1, #0x0003
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beq el3_panic
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/* warm boot or cold boot */
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and x1, x21, #1
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cmp x1, #0
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bne warm_reset
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/* Cold boot */
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mov x0, #0
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b exit
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warm_reset:
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/* --------------------------------------------------------------------
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* A per-cpu mailbox is maintained in the trusted SDRAM. Its flushed out
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* of the caches after every update using normal memory so its safe to
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* read it here with SO attributes
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* ---------------------------------------------------------------------
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*/
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ldr x10, =MBOX_BASE
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bl platform_get_core_pos
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lsl x0, x0, #CACHE_WRITEBACK_SHIFT
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ldr x0, [x10, x0]
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cbz x0, _panic
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exit:
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ret x9
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_panic:
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b do_panic
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#endif
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* plat_secondary_reset
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*
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* ---------------------------------------------
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*/
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func plat_secondary_reset
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mrs x0, sctlr_el3
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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mrs x0, cptr_el3
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bic w0, w0, #TCPAC_BIT
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bic w0, w0, #TTA_BIT
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bic w0, w0, #TFP_BIT
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msr cptr_el3, x0
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mov_imm x0, PARAMS_BASE
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mov_imm x2, BL31_BASE
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ldr x3, =BOOT_KIND_BASE
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mov x1, #0x1
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str x1, [x3]
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br x2 /* jump to BL31 */
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nop
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nop
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nop
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endfunc plat_secondary_reset
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/* ---------------------------------------------
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* plat_enter_bl31
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*
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* ---------------------------------------------
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*/
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func bl2_enter_bl31
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mov x20, x0
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/*
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* MMU needs to be disabled because both BL2 and BL31 execute
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* in EL3, and therefore share the same address space.
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* BL31 will initialize the address space according to its
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* own requirement.
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*/
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#if RCAR_BL2_DCACHE == 1
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/* Disable mmu and data cache */
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bl disable_mmu_el3
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/* Data cache clean and invalidate */
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mov x0, #DCCISW
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bl dcsw_op_all
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/* TLB invalidate all, EL3 */
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tlbi alle3
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#endif /* RCAR_BL2_DCACHE == 1 */
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bl disable_mmu_icache_el3
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/* Invalidate instruction cache */
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ic iallu
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dsb sy
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isb
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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exception_return
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endfunc bl2_enter_bl31
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/* -----------------------------------------------------
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* void platform_mem_init (void);
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*
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* Zero out the mailbox registers in the shared memory
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* and set the rcar_boot_kind_flag.
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* The mmu is turned off right now and only the primary can
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* ever execute this code. Secondaries will read the
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* mailboxes using SO accesses.
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* -----------------------------------------------------
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*/
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func platform_mem_init
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#if !IMAGE_BL2
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ldr x0, =MBOX_BASE
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mov w1, #PLATFORM_CORE_COUNT
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loop:
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str xzr, [x0], #CACHE_WRITEBACK_GRANULE
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subs w1, w1, #1
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b.gt loop
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#endif
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* void plat_report_exception(unsigned int type)
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* Function to report an unhandled exception
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* with platform-specific means.
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* ---------------------------------------------
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*/
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func plat_report_exception
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/* Switch to SP_EL0 */
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msr spsel, #0
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#if IMAGE_BL2
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mov w1, #FIQ_SP_EL0
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cmp w0, w1
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beq rep_exec_fiq_elx
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b rep_exec_panic_type
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rep_exec_fiq_elx:
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bl gicv2_acknowledge_interrupt
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mov x2, #INT_ID_MASK
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and x0, x0, x2
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mov x1, #ARM_IRQ_SEC_WDT
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cmp x0, x1
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bne rep_exec_panic_id
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mrs x0, ELR_EL3
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b rcar_swdt_exec
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rep_exec_panic_type:
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/* x0 is interrupt TYPE */
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b bl2_interrupt_error_type
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rep_exec_panic_id:
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/* x0 is interrupt ID */
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b bl2_interrupt_error_id
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rep_exec_end:
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#endif
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ret
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endfunc plat_report_exception
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize log area
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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#if IMAGE_BL2
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mov x0, #0
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#else
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mov x1, sp
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mov_imm x2, RCAR_CRASH_STACK
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mov sp, x2
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str x1, [sp, #-16]!
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str x30, [sp, #-16]!
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bl console_rcar_init
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ldr x30, [sp], #16
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ldr x1, [sp], #16
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mov sp, x1
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#endif
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ret
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to store a character to log area
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov x1, sp
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mov_imm x2, RCAR_CRASH_STACK
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mov sp, x2
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str x1, [sp, #-16]!
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str x30, [sp, #-16]!
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str x3, [sp, #-16]!
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str x4, [sp, #-16]!
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str x5, [sp, #-16]!
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str x6, [sp, #-16]!
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str x7, [sp, #-16]!
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bl console_rcar_putc
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ldr x7, [sp], #16
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ldr x6, [sp], #16
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ldr x5, [sp], #16
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ldr x4, [sp], #16
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ldr x3, [sp], #16
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ldr x30, [sp], #16
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ldr x1, [sp], #16
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mov sp, x1
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ret
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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b console_rcar_flush
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endfunc plat_crash_console_flush
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/* --------------------------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Before adding code in this function, refer to the guidelines in
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* docs/firmware-design.md to determine whether the code should reside
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* within the FIRST_RESET_HANDLER_CALL block or not.
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*
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* For R-Car H3:
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* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57
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* - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
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* For R-Car M3/M3N:
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* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57
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* - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
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*
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* --------------------------------------------------------------------
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*/
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func plat_reset_handler
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/*
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* On R-Car H3 : x2 := 0
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* On R-Car M3/M3N: x2 := 1
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*/
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/* read PRR */
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ldr x0, =0xFFF00044
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ldr w0, [x0]
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ubfx w0, w0, 8, 8
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/* H3? */
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cmp w0, #0x4F
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b.eq RCARH3
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/* set R-Car M3/M3N */
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mov x2, #1
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b CHK_A5x
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RCARH3:
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/* set R-Car H3 */
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mov x2, #0
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/* --------------------------------------------------------------------
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* Determine whether this code is executed on a Cortex-A53 or on a
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* Cortex-A57 core.
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* --------------------------------------------------------------------
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*/
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CHK_A5x:
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mrs x0, midr_el1
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ubfx x1, x0, MIDR_PN_SHIFT, #12
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cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq A57
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ret
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A57:
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/* Get data from CORTEX_A57_L2CTLR_EL1 */
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mrs x0, CORTEX_A57_L2CTLR_EL1
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/*
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* On R-Car H3/M3/M3N
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*
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* L2 Tag RAM latency is bit8-6 of CORTEX_A57_L2CTLR_EL1
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* L2 Data RAM setup is bit5 of CORTEX_A57_L2CTLR_EL1
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* L2 Data RAM latency is bit2-0 of CORTEX_A57_L2CTLR_EL1
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*/
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/* clear bit of L2 RAM */
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/* ~(0x1e7) -> x1 */
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mov x1, #0x1e7
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neg x1, x1
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/* clear bit of L2 RAM -> x0 */
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and x0, x0, x1
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/* L2 Tag RAM latency (3 cycles) */
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orr x0, x0, #0x2 << 6
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/* If M3/M3N then L2 RAM setup is 0 */
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cbnz x2, M3_L2
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/* L2 Data RAM setup (1 cycle) */
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orr x0, x0, #0x1 << 5
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M3_L2:
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/* L2 Data RAM latency (4 cycles) */
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orr x0, x0, #0x3
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/* Store data to L2CTLR_EL1 */
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msr CORTEX_A57_L2CTLR_EL1, x0
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apply_l2_ram_latencies:
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ret
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endfunc plat_reset_handler
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/* ---------------------------------------------
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* void plat_invalidate_icache(void)
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* Instruction Cache Invalidate All to PoU
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* ---------------------------------------------
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*/
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func plat_invalidate_icache
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ic iallu
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ret
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endfunc plat_invalidate_icache
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+271
@@ -0,0 +1,271 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include "rcar_def.h"
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#include "rcar_private.h"
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#include "rcar_version.h"
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#if (IMAGE_BL2)
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extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
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extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
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#endif
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const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
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__attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS;
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#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
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RCAR_SHARED_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
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FLASH0_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
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DRAM1_NS_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
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DEVICE_RCAR_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
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DEVICE_RCAR_SIZE2, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
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DEVICE_SRAM_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
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DEVICE_SRAM_STACK_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
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RCAR_BL31_CRASH_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
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RCAR_BL31_LOG_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#if IMAGE_BL2
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#define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
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DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
|
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#define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
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DEVICE_RCAR_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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||||
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#define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
|
||||
RCAR_SYSRAM_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
|
||||
#define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
|
||||
REG1_SIZE, \
|
||||
MT_DEVICE | MT_RW | MT_SECURE)
|
||||
|
||||
#define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
|
||||
ROM0_SIZE, \
|
||||
MT_MEMORY | MT_RO | MT_SECURE)
|
||||
|
||||
#define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
|
||||
REG2_SIZE, \
|
||||
MT_DEVICE | MT_RW | MT_SECURE)
|
||||
|
||||
#define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
|
||||
DRAM_40BIT_SIZE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
#endif
|
||||
|
||||
#ifdef BL32_BASE
|
||||
#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \
|
||||
BL32_LIMIT - BL32_BASE, \
|
||||
MT_MEMORY | MT_RW | MT_SECURE)
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL2
|
||||
static const mmap_region_t rcar_mmap[] = {
|
||||
MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
|
||||
MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
|
||||
MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
|
||||
MAP_RAM0, /* 0xE6300000 - 0xE6303FFF System RAM area */
|
||||
MAP_REG1, /* 0xE6400000 - 0xEAFFFFFF SoC register area */
|
||||
MAP_ROM, /* 0xEB100000 - 0xEB127FFF boot ROM area */
|
||||
MAP_REG2, /* 0xEC000000 - 0xFFFFFFFF SoC register area */
|
||||
MAP_DRAM1, /* 0x0400000000 - 0x07FFFFFFFF DRAM area(4GB over) */
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL31
|
||||
static const mmap_region_t rcar_mmap[] = {
|
||||
MAP_SHARED_RAM,
|
||||
MAP_ATFW_CRASH,
|
||||
MAP_ATFW_LOG,
|
||||
MAP_DEVICE_RCAR,
|
||||
MAP_DEVICE_RCAR2,
|
||||
MAP_SRAM,
|
||||
MAP_SRAM_STACK,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IMAGE_BL32
|
||||
static const mmap_region_t rcar_mmap[] = {
|
||||
MAP_DEVICE0,
|
||||
MAP_DEVICE1,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
|
||||
CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
|
||||
<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
|
||||
|
||||
/*
|
||||
* Macro generating the code for the function setting up the pagetables as per
|
||||
* the platform memory map & initialize the mmu, for the given exception level
|
||||
*/
|
||||
#if USE_COHERENT_MEM
|
||||
void rcar_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit)
|
||||
{
|
||||
mmap_add_region(total_base, total_base, total_size,
|
||||
MT_MEMORY | MT_RW | MT_SECURE);
|
||||
mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
|
||||
MT_MEMORY | MT_RO | MT_SECURE);
|
||||
mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
|
||||
MT_DEVICE | MT_RW | MT_SECURE);
|
||||
mmap_add(rcar_mmap);
|
||||
|
||||
init_xlat_tables();
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
#else
|
||||
void rcar_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit)
|
||||
{
|
||||
mmap_add_region(total_base, total_base, total_size,
|
||||
MT_MEMORY | MT_RW | MT_SECURE);
|
||||
mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
|
||||
MT_MEMORY | MT_RO | MT_SECURE);
|
||||
mmap_add(rcar_mmap);
|
||||
|
||||
init_xlat_tables();
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
uintptr_t plat_get_ns_image_entrypoint(void)
|
||||
{
|
||||
#if (IMAGE_BL2)
|
||||
uint32_t cert, len;
|
||||
uintptr_t dst;
|
||||
int32_t ret;
|
||||
|
||||
ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
|
||||
if (ret) {
|
||||
ERROR("%s : cert file load error", __func__);
|
||||
return NS_IMAGE_OFFSET;
|
||||
}
|
||||
|
||||
rcar_read_certificate((uint64_t) cert, &len, &dst);
|
||||
|
||||
return dst;
|
||||
#else
|
||||
return NS_IMAGE_OFFSET;
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
unsigned int freq;
|
||||
|
||||
freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
|
||||
if (freq == 0)
|
||||
panic();
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
void plat_rcar_gic_init(void)
|
||||
{
|
||||
gicv2_distif_init();
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
|
||||
static const interrupt_prop_t interrupt_props[] = {
|
||||
#if IMAGE_BL2
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
#else
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
|
||||
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
||||
#endif
|
||||
};
|
||||
|
||||
static const gicv2_driver_data_t plat_gicv2_driver_data = {
|
||||
.interrupt_props = interrupt_props,
|
||||
.interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
|
||||
.gicd_base = RCAR_GICD_BASE,
|
||||
.gicc_base = RCAR_GICC_BASE,
|
||||
};
|
||||
|
||||
void plat_rcar_gic_driver_init(void)
|
||||
{
|
||||
gicv2_driver_init(&plat_gicv2_driver_data);
|
||||
}
|
||||
Reference in New Issue
Block a user