GK SDK 源码库: XMIPCLinuxV100R005C00SPC030 (kernel/tools/open_source excluded)
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a12.h>
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#include <plat_private.h>
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#include <plat_pmu_macros.S>
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.globl cpuson_entry_point
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.globl cpuson_flags
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.globl platform_cpu_warmboot
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.globl plat_secondary_cold_boot_setup
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.globl plat_report_exception
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_reset_handler
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.globl plat_panic_handler
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/*
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* void plat_reset_handler(void);
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*
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* Determine the SOC type and call the appropriate reset
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* handler.
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*
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*/
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func plat_reset_handler
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bx lr
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endfunc plat_reset_handler
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func plat_my_core_pos
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ldcopr r0, MPIDR
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and r1, r0, #MPIDR_CPU_MASK
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#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
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and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
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#else
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and r0, r0, #MPIDR_CLUSTER_MASK
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#endif
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add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
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bx lr
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endfunc plat_my_core_pos
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/* --------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* rk3288 does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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ldcopr r0, MPIDR
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#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
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ldr r1, =(PLAT_RK_MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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#else
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ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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#endif
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and r0, r1
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cmp r0, #PLAT_RK_PRIMARY_CPU
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moveq r0, #1
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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/* --------------------------------------------------------------------
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* void plat_panic_handler(void)
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* Call system reset function on panic. Set up an emergency stack so we
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* can run C functions (it only needs to last for a few calls until we
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* reboot anyway).
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* --------------------------------------------------------------------
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*/
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func plat_panic_handler
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bl plat_set_my_stack
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b rockchip_soc_soft_reset
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endfunc plat_panic_handler
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/* --------------------------------------------------------------------
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* void platform_cpu_warmboot (void);
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* cpus online or resume entrypoint
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* --------------------------------------------------------------------
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*/
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func platform_cpu_warmboot _align=16
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push { r4 - r7, lr }
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ldcopr r0, MPIDR
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and r5, r0, #MPIDR_CPU_MASK
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#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
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and r6, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
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#else
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and r6, r0, #MPIDR_CLUSTER_MASK
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#endif
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mov r0, r6
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func_rockchip_clst_warmboot
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/* --------------------------------------------------------------------
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* big cluster id is 1
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* big cores id is from 0-3, little cores id 4-7
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* --------------------------------------------------------------------
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*/
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add r7, r5, r6, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
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/* --------------------------------------------------------------------
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* get per cpuup flag
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* --------------------------------------------------------------------
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*/
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ldr r4, =cpuson_flags
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add r4, r4, r7, lsl #2
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ldr r1, [r4]
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/* --------------------------------------------------------------------
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* check cpuon reason
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* --------------------------------------------------------------------
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*/
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cmp r1, #PMU_CPU_AUTO_PWRDN
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beq boot_entry
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cmp r1, #PMU_CPU_HOTPLUG
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beq boot_entry
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/* --------------------------------------------------------------------
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* If the boot core cpuson_flags or cpuson_entry_point is not
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* expection. force the core into wfe.
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* --------------------------------------------------------------------
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*/
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wfe_loop:
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wfe
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b wfe_loop
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boot_entry:
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mov r1, #0
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str r1, [r4]
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/* --------------------------------------------------------------------
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* get per cpuup boot addr
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* --------------------------------------------------------------------
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*/
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ldr r5, =cpuson_entry_point
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ldr r2, [r5, r7, lsl #2] /* ehem. #3 */
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pop { r4 - r7, lr }
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bx r2
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endfunc platform_cpu_warmboot
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/* --------------------------------------------------------------------
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* Per-CPU Secure entry point - resume or power up
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* --------------------------------------------------------------------
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*/
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.section tzfw_coherent_mem, "a"
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.align 3
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cpuson_entry_point:
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.rept PLATFORM_CORE_COUNT
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.quad 0
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.endr
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cpuson_flags:
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.rept PLATFORM_CORE_COUNT
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.word 0
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.endr
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rockchip_clst_warmboot_data
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+57
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat_private.h>
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void plat_configure_mmu_svc_mon(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit)
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{
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mmap_add_region(total_base, total_base, total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
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MT_MEMORY | MT_RO | MT_SECURE);
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mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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mmap_add(plat_rk_mmap);
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rockchip_plat_mmu_svc_mon();
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init_xlat_tables();
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enable_mmu_svc_mon(0);
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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/*
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* generic pm code does cci handling, but rockchip arm32 platforms
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* have ever only 1 cluster, so nothing to do.
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*/
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void plat_cci_init(void)
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{
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}
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void plat_cci_enable(void)
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{
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}
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void plat_cci_disable(void)
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{
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}
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+56
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl pmu_cpuson_entrypoint
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.macro pmusram_entry_func _name
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.section .pmusram.entry, "ax"
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.type \_name, %function
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.cfi_startproc
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\_name:
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.endm
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pmusram_entry_func pmu_cpuson_entrypoint
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#if PSRAM_CHECK_WAKEUP_CPU
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check_wake_cpus:
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ldcopr r0, MPIDR
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and r1, r0, #MPIDR_CPU_MASK
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#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
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and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
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#else
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and r0, r0, #MPIDR_CLUSTER_MASK
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#endif
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orr r0, r0, r1
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/* primary_cpu */
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ldr r1, boot_mpidr
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cmp r0, r1
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beq sys_wakeup
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/*
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* If the core is not the primary cpu,
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* force the core into wfe.
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*/
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wfe_loop:
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wfe
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b wfe_loop
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sys_wakeup:
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#endif
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#if PSRAM_DO_DDR_RESUME
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ddr_resume:
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ldr r2, =__bl32_sram_stack_end
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mov sp, r2
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bl dmc_resume
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#endif
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bl sram_restore
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sys_resume:
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bl sp_min_warm_entrypoint
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endfunc pmu_cpuson_entrypoint
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